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ORCIDBibTeX records: Dean L. Lewis
@article{DBLP:journals/tc/KimAHHJKKLLLLPPRSSWZKCLLL15,
author = {Daehyun Kim and
Krit Athikulwongse and
Michael B. Healy and
Mohammad M. Hossain and
Moongon Jung and
Ilya Khorosh and
Gokul Kumar and
Young{-}Joon Lee and
Dean L. Lewis and
Tzu{-}Wei Lin and
Chang Liu and
Shreepad Panth and
Mohit Pathak and
Minzhen Ren and
Guanhao Shen and
Taigon Song and
Dong Hyuk Woo and
Xin Zhao and
Joungho Kim and
Ho Choi and
Gabriel H. Loh and
Hsien{-}Hsin S. Lee and
Sung Kyu Lim},
title = {Design and Analysis of 3D-MAPS {(3D} Massively Parallel Processor
with Stacked Memory)},
journal = {{IEEE} Trans. Computers},
volume = {64},
number = {1},
pages = {112--125},
year = {2015},
url = {https://doi.org/10.1109/TC.2013.192},
doi = {10.1109/TC.2013.192},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/KimAHHJKKLLLLPPRSSWZKCLLL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/basesearch/Lewis12b,
author = {Dean L. Lewis},
title = {Design for pre-bond testability in 3D integrated circuits},
school = {Georgia Institute of Technology, Atlanta, GA, {USA}},
year = {2012},
url = {https://hdl.handle.net/1853/45756},
timestamp = {Wed, 04 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/basesearch/Lewis12b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimAHHJKKLLLLPPRSSWZKCLLL12,
author = {Dae Hyun Kim and
Krit Athikulwongse and
Michael B. Healy and
Mohammad M. Hossain and
Moongon Jung and
Ilya Khorosh and
Gokul Kumar and
Young{-}Joon Lee and
Dean L. Lewis and
Tzu{-}Wei Lin and
Chang Liu and
Shreepad Panth and
Mohit Pathak and
Minzhen Ren and
Guanhao Shen and
Taigon Song and
Dong Hyuk Woo and
Xin Zhao and
Joungho Kim and
Ho Choi and
Gabriel H. Loh and
Hsien{-}Hsin S. Lee and
Sung Kyu Lim},
title = {3D-MAPS: 3D Massively parallel processor with stacked memory},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {188--190},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6176969},
doi = {10.1109/ISSCC.2012.6176969},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KimAHHJKKLLLLPPRSSWZKCLLL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoLLL11,
author = {Xin Zhao and
Dean L. Lewis and
Hsien{-}Hsin S. Lee and
Sung Kyu Lim},
title = {Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {732--745},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2098130},
doi = {10.1109/TCAD.2010.2098130},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoLLL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/LewisPZLL11,
author = {Dean L. Lewis and
Shreepad Panth and
Xin Zhao and
Sung Kyu Lim and
Hsien{-}Hsin S. Lee},
title = {Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded
cores},
booktitle = {{IEEE} 29th International Conference on Computer Design, {ICCD} 2011,
Amherst, MA, USA, October 9-12, 2011},
pages = {90--95},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICCD.2011.6081381},
doi = {10.1109/ICCD.2011.6081381},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/LewisPZLL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/HealyAGHKLLLLJOPSSWZLLL10,
author = {Michael B. Healy and
Krit Athikulwongse and
Rohan Goel and
Mohammad M. Hossain and
Dae Hyun Kim and
Young{-}Joon Lee and
Dean L. Lewis and
Tzu{-}Wei Lin and
Chang Liu and
Moongon Jung and
Brian Ouellette and
Mohit Pathak and
Hemant Sane and
Guanhao Shen and
Dong Hyuk Woo and
Xin Zhao and
Gabriel H. Loh and
Hsien{-}Hsin S. Lee and
Sung Kyu Lim},
editor = {Jacqueline Snyder and
Rakesh Patel and
Tom Andre},
title = {Design and analysis of 3D-MAPS: {A} many-core 3D processor with stacked
memory},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2010, San Jose,
California, USA, 19-22 September, 2010, Proceedings},
pages = {1--4},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/CICC.2010.5617464},
doi = {10.1109/CICC.2010.5617464},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/HealyAGHKLLLLJOPSSWZLLL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/WooSLL10,
author = {Dong Hyuk Woo and
Nak Hee Seong and
Dean L. Lewis and
Hsien{-}Hsin S. Lee},
editor = {Matthew T. Jacob and
Chita R. Das and
Pradip Bose},
title = {An optimized 3D-stacked memory architecture by exploiting excessive,
high-density {TSV} bandwidth},
booktitle = {16th International Conference on High-Performance Computer Architecture
{(HPCA-16} 2010), 9-14 January 2010, Bangalore, India},
pages = {1--12},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HPCA.2010.5416628},
doi = {10.1109/HPCA.2010.5416628},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpca/WooSLL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/3dic/LewisL09,
author = {Dean L. Lewis and
Hsien{-}Hsin S. Lee},
title = {Architectural evaluation of 3D stacked {RRAM} caches},
booktitle = {{IEEE} International Conference on 3D System Integration, 3DIC 2009,
San Francisco, California, USA, 28-30 September 2009},
pages = {1--4},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/3DIC.2009.5306582},
doi = {10.1109/3DIC.2009.5306582},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/3dic/LewisL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhaoLLL09,
author = {Xin Zhao and
Dean L. Lewis and
Hsien{-}Hsin S. Lee and
Sung Kyu Lim},
editor = {Jaijeet S. Roychowdhury},
title = {Pre-bond testable low-power clock tree design for 3D stacked ICs},
booktitle = {2009 International Conference on Computer-Aided Design, {ICCAD} 2009,
San Jose, CA, USA, November 2-5, 2009},
pages = {184--190},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1687399.1687433},
doi = {10.1145/1687399.1687433},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ZhaoLLL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LewisYL09,
author = {Dean L. Lewis and
Sudhakar Yalamanchili and
Hsien{-}Hsin S. Lee},
title = {High Performance Non-blocking Switch Design in 3D Die-Stacking Technology},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2009, 13-15
May 2009, Tampa, Florida, {USA}},
pages = {25--30},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISVLSI.2009.53},
doi = {10.1109/ISVLSI.2009.53},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LewisYL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LewisL09,
author = {Dean L. Lewis and
Hsien{-}Hsin S. Lee},
title = {Testing Circuit-Partitioned 3D {IC} Designs},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2009, 13-15
May 2009, Tampa, Florida, {USA}},
pages = {139--144},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISVLSI.2009.48},
doi = {10.1109/ISVLSI.2009.48},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LewisL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/LewisL07,
author = {Dean L. Lewis and
Hsien{-}Hsin S. Lee},
editor = {Jill Sibert and
Janusz Rajski},
title = {A scanisland based design enabling prebond testability in die-stacked
microprocessors},
booktitle = {2007 {IEEE} International Test Conference, {ITC} 2007, Santa Clara,
California, USA, October 21-26, 2007},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/TEST.2007.4437621},
doi = {10.1109/TEST.2007.4437621},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/LewisL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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