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ORCIDBibTeX records: Taewhan Kim
@article{DBLP:journals/tcad/BaekK24,
author = {Kyeonghyeon Baek and
Taewhan Kim},
title = {CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous
Transistor Folding and Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {2},
pages = {627--640},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2023.3320631},
doi = {10.1109/TCAD.2023.3320631},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/BaekK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/KimPBCK24,
author = {Suwan Kim and
Hyunbum Park and
Kyeonghyeon Baek and
Kyumyung Choi and
Taewhan Kim},
editor = {Iris Hui{-}Ru Jiang and
Gracieli Posser},
title = {Methodology of Resolving Design Rule Checking Violations Coupled with
Fully Compatible Prediction Model},
booktitle = {Proceedings of the 2024 International Symposium on Physical Design,
{ISPD} 2024, Taipei, Taiwan, March 12-15, 2024},
pages = {103--111},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3626184.3633324},
doi = {10.1145/3626184.3633324},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ispd/KimPBCK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JeongKP23,
author = {Eunsol Jeong and
Taewhan Kim and
Heechun Park},
title = {Eliminating Minimum Implant Area Violations With Design Quality Preservation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {5},
pages = {611--621},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3225551},
doi = {10.1109/TVLSI.2022.3225551},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JeongKP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChangAPCK23,
author = {Kyungjoon Chang and
Jaehoon Ahn and
Heechun Park and
Kyu{-}Myung Choi and
Taewhan Kim},
title = {{DTOC:} integrating Deep-learning driven Timing Optimization into
the state-of-the-art Commercial {EDA} tool},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137234},
doi = {10.23919/DATE56975.2023.10137234},
timestamp = {Wed, 07 Jun 2023 22:08:03 +0200},
biburl = {https://dblp.org/rec/conf/date/ChangAPCK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/JeongCJK23,
author = {Jooyeon Jeong and
Sehyeon Chung and
Kyeongrok Jo and
Taewhan Kim},
title = {Synthesis and Utilization of Standard Cells Amenable to Gear Ratio
of Gate-Metal Pitches for Improving Pin Accessibility},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137264},
doi = {10.23919/DATE56975.2023.10137264},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/JeongCJK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/KimK23,
author = {Hwapyong Kim and
Taewhan Kim},
editor = {Himanshu Thapliyal and
Ronald F. DeMara and
Inna Partin{-}Vaisband and
Srinivas Katkoori},
title = {Placement Legalization Amenable to Mixed-cell-height Standard Cells
Integrating into State-of-the-art Commercial {EDA} Tool},
booktitle = {Proceedings of the Great Lakes Symposium on {VLSI} 2023, {GLSVLSI}
2023, Knoxville, TN, USA, June 5-7, 2023},
pages = {321--326},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3583781.3590278},
doi = {10.1145/3583781.3590278},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/KimK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KimK23,
author = {Suwan Kim and
Taewhan Kim},
title = {Design and Technology Co-Optimization for Useful Skew Scheduling on
Multi-Bit Flip-Flops},
booktitle = {{IEEE/ACM} International Conference on Computer Aided Design, {ICCAD}
2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023},
pages = {1--9},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCAD57390.2023.10323866},
doi = {10.1109/ICCAD57390.2023.10323866},
timestamp = {Wed, 03 Jan 2024 08:34:26 +0100},
biburl = {https://dblp.org/rec/conf/iccad/KimK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ParkK23,
author = {Sora Park and
Taewhan Kim},
title = {Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock
Gating},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,
Monterey, CA, USA, May 21-25, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISCAS46773.2023.10181800},
doi = {10.1109/ISCAS46773.2023.10181800},
timestamp = {Mon, 31 Jul 2023 09:04:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ParkK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/WonKK23,
author = {Doyeon Won and
Soomin Kim and
Taewhan Kim},
title = {Machine Learning Driven Synthesis of Clock Gating},
booktitle = {{IEEE/ACM} International Symposium on Low Power Electronics and Design,
{ISLPED} 2023, Vienna, Austria, August 7-8, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISLPED58423.2023.10244402},
doi = {10.1109/ISLPED58423.2023.10244402},
timestamp = {Fri, 15 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/WonKK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/KimK23,
author = {Jinmyoung Kim and
Taewhan Kim},
title = {Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips},
booktitle = {20th International SoC Design Conference, {ISOCC} 2023, Jeju, Republic
of Korea, October 25-28, 2023},
pages = {121--122},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISOCC59558.2023.10395980},
doi = {10.1109/ISOCC59558.2023.10395980},
timestamp = {Thu, 22 Feb 2024 20:44:54 +0100},
biburl = {https://dblp.org/rec/conf/isocc/KimK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/KimK23a,
author = {Chaehyun Kim and
Taewhan Kim},
title = {Maximizing Power Saving Through State-Driven Clock Gating},
booktitle = {20th International SoC Design Conference, {ISOCC} 2023, Jeju, Republic
of Korea, October 25-28, 2023},
pages = {123--124},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISOCC59558.2023.10396230},
doi = {10.1109/ISOCC59558.2023.10396230},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/KimK23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/JeonK23,
author = {Kihwan Jeon and
Taewhan Kim},
title = {Fast Refinement on Placement Legalization for Designs with Mixed-Height
Cells},
booktitle = {20th International SoC Design Conference, {ISOCC} 2023, Jeju, Republic
of Korea, October 25-28, 2023},
pages = {345--346},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISOCC59558.2023.10396066},
doi = {10.1109/ISOCC59558.2023.10396066},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/JeonK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/HaK23,
author = {Ilseon Ha and
Taewhan Kim},
title = {Optimizing Timing for Multi-bit Flip-Flop Intensive Designs Compatible
with Commercial {EDA} Flow},
booktitle = {20th International SoC Design Conference, {ISOCC} 2023, Jeju, Republic
of Korea, October 25-28, 2023},
pages = {347--348},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISOCC59558.2023.10396028},
doi = {10.1109/ISOCC59558.2023.10396028},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/HaK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/Kim23,
author = {Taewhan Kim},
title = {Challenges on Design and Technology Co-Optimization: Design Automation
Perspective},
booktitle = {66th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2023, Tempe, AZ, USA, August 6-9, 2023},
pages = {212--216},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MWSCAS57524.2023.10405868},
doi = {10.1109/MWSCAS57524.2023.10405868},
timestamp = {Sat, 24 Feb 2024 20:42:53 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/Kim23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/YangK23,
author = {Jaewan Yang and
Taewhan Kim},
editor = {J{\"{u}}rgen Becker and
Andrew Marshall and
Tanja Harbaum and
Amlan Ganguly and
Fahad Siddiqui and
Kieran McLaughlin},
title = {Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful
Clock Skew Scheduling},
booktitle = {36th {IEEE} International System-on-Chip Conference, {SOCC} 2023,
Santa Clara, CA, USA, September 5-8, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/SOCC58585.2023.10256966},
doi = {10.1109/SOCC58585.2023.10256966},
timestamp = {Tue, 21 Nov 2023 07:48:13 +0100},
biburl = {https://dblp.org/rec/conf/socc/YangK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ce/LimKCLKH22,
author = {Hyoungjoon Lim and
Soohyun Kim and
Kyong{-}Mee Chung and
Kangjae Lee and
Taewhan Kim and
Joon Heo},
title = {Is college students' trajectory associated with academic performance?},
journal = {Comput. Educ.},
volume = {178},
pages = {104397},
year = {2022},
url = {https://doi.org/10.1016/j.compedu.2021.104397},
doi = {10.1016/J.COMPEDU.2021.104397},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ce/LimKCLKH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ParkK22,
author = {Heechun Park and
Taewhan Kim},
title = {Speeding-up neuromorphic computation for neural networks: Structure
optimization approach},
journal = {Integr.},
volume = {82},
pages = {104--114},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2021.09.001},
doi = {10.1016/J.VLSI.2021.09.001},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ParkK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChungK22,
author = {Sehyeon Chung and
Taewhan Kim},
title = {{ECO} routing based on network flow method},
journal = {Integr.},
volume = {86},
pages = {1--8},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.04.002},
doi = {10.1016/J.VLSI.2022.04.002},
timestamp = {Thu, 25 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChungK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcse/KangK22,
author = {Jongsung Kang and
Taewhan Kim},
title = {Improving Speed of MUX-FSM-based Stochastic Computing for On-device
Neural Networks},
journal = {J. Comput. Sci. Eng.},
volume = {16},
number = {2},
pages = {79--87},
year = {2022},
url = {https://doi.org/10.5626/jcse.2022.16.2.79},
doi = {10.5626/JCSE.2022.16.2.79},
timestamp = {Mon, 05 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcse/KangK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AhnK22,
author = {Byungmin Ahn and
Taewhan Kim},
title = {Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks:
Signed-Digit Representation-Based Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {3},
pages = {656--668},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3064914},
doi = {10.1109/TCAD.2021.3064914},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AhnK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HeoJCKC22,
author = {Jeongwoo Heo and
Kwangok Jeong and
Jungyun Choi and
Taewhan Kim and
Kyumyung Choi},
title = {Hardware Performance Monitoring Methodology at Near-Threshold Computing
and Advanced Technology Nodes: From Design to Postsilicon},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {6},
pages = {1929--1942},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3095824},
doi = {10.1109/TCAD.2021.3095824},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HeoJCKC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KimK22,
author = {Suwan Kim and
Taewhan Kim},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {Pin Accessibility-driven Placement Optimization with Accurate and
Comprehensive Prediction Model},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {778--783},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774753},
doi = {10.23919/DATE54114.2022.9774753},
timestamp = {Wed, 25 May 2022 22:56:19 +0200},
biburl = {https://dblp.org/rec/conf/date/KimK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/JeongPK22,
author = {Eunsol Jeong and
Heechun Park and
Taewhan Kim},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {A Systematic Removal of Minimum Implant Area Violations under Timing
Constraint},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {933--938},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774701},
doi = {10.23919/DATE54114.2022.9774701},
timestamp = {Wed, 25 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/JeongPK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KimK22,
author = {Soomin Kim and
Taewhan Kim},
editor = {Tulika Mitra and
Evangeline F. Y. Young and
Jinjun Xiong},
title = {Design and Technology Co-Optimization Utilizing Multi-Bit Flip-Flop
Cells},
booktitle = {Proceedings of the 41st {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2022, San Diego, California, USA, 30 October 2022
- 3 November 2022},
pages = {15:1--15:7},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3508352.3549351},
doi = {10.1145/3508352.3549351},
timestamp = {Tue, 06 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/KimK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/BaekPKCK22,
author = {Kyeonghyeon Baek and
Hyunbum Park and
Suwan Kim and
Kyumyung Choi and
Taewhan Kim},
editor = {Tulika Mitra and
Evangeline F. Y. Young and
Jinjun Xiong},
title = {Pin Accessibility and Routing Congestion Aware {DRC} Hotspot Prediction
Using Graph Neural Network and U-Net},
booktitle = {Proceedings of the 41st {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2022, San Diego, California, USA, 30 October 2022
- 3 November 2022},
pages = {26:1--26:9},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3508352.3549346},
doi = {10.1145/3508352.3549346},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/BaekPKCK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ParkK22,
author = {Sora Park and
Taewhan Kim},
title = {Selective Clock Gating Based on Comprehensive Power Saving Analysis},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {230--231},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937589},
doi = {10.1109/ISCAS48785.2022.9937589},
timestamp = {Thu, 17 Nov 2022 15:59:17 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ParkK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WonK22,
author = {Doyeon Won and
Taewhan Kim},
title = {Improving Pin Accessibility of Standard Cells Through Fin Depopulation},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {2621--2622},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937885},
doi = {10.1109/ISCAS48785.2022.9937885},
timestamp = {Thu, 17 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/WonK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KimK22,
author = {Soomin Kim and
Taewhan Kim},
title = {Optimizing Timing in Placement Through {I/O} Signal Flipping on Multi-bit
Flip-flops},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {2623--2624},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937267},
doi = {10.1109/ISCAS48785.2022.9937267},
timestamp = {Wed, 03 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KimK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ChungJK22,
author = {Sehyeon Chung and
Jooyeon Jeong and
Taewhan Kim},
editor = {Hai Helen Li and
Charles Augustine and
Ayse Kivilcim Coskun and
Swaroop Ghosh},
title = {Improving Performance and Power by Co-Optimizing Middle-of-Line Routing,
Pin Pattern Generation, and Contact over Active Gates in Standard
Cell Layout Synthesis},
booktitle = {{ISLPED} '22: {ACM/IEEE} International Symposium on Low Power Electronics
and Design, Boston, MA, USA, August 1 - 3, 2022},
pages = {17:1--17:6},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3531437.3539712},
doi = {10.1145/3531437.3539712},
timestamp = {Mon, 15 Aug 2022 14:55:22 +0200},
biburl = {https://dblp.org/rec/conf/islped/ChungJK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KimCKP22,
author = {Suwan Kim and
Sehyeon Chung and
Taewhan Kim and
Heechun Park},
editor = {Hai Helen Li and
Charles Augustine and
Ayse Kivilcim Coskun and
Swaroop Ghosh},
title = {Tightly Linking 3D Via Allocation Towards Routing Optimization for
Monolithic 3D ICs},
booktitle = {{ISLPED} '22: {ACM/IEEE} International Symposium on Low Power Electronics
and Design, Boston, MA, USA, August 1 - 3, 2022},
pages = {26:1--26:6},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3531437.3539714},
doi = {10.1145/3531437.3539714},
timestamp = {Mon, 15 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/KimCKP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/ChangK22,
author = {Kyungjoon Chang and
Taewhan Kim},
title = {Analysis of Impacting Multi-stack Standard Cells on Chip Implementation},
booktitle = {19th International SoC Design Conference, {ISOCC} 2022, Gangneung-si,
Republic of Korea, October 19-22, 2022},
pages = {119--120},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISOCC56007.2022.10031298},
doi = {10.1109/ISOCC56007.2022.10031298},
timestamp = {Wed, 15 Feb 2023 22:08:05 +0100},
biburl = {https://dblp.org/rec/conf/isocc/ChangK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/AhnK22,
author = {Jaehoon Ahn and
Taewhan Kim},
editor = {Mustafa Badaroglu and
Shantanu Dutt},
title = {Neural Network Model for Detour Net Prediction},
booktitle = {Proceedings of the 24th {ACM/IEEE} Workshop on System Level Interconnect
Pathfinding, {SLIP} 2022, San Diego, California, 3 November 2022},
pages = {6:1--6:5},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3557988.3569710},
doi = {10.1145/3557988.3569710},
timestamp = {Mon, 19 Feb 2024 16:17:50 +0100},
biburl = {https://dblp.org/rec/conf/slip/AhnK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HanK21,
author = {Changho Han and
Taewhan Kim},
title = {Synthesis of representative critical path circuits considering {BEOL}
variations for deep sub-micron circuits},
journal = {Integr.},
volume = {78},
pages = {1--10},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.12.003},
doi = {10.1016/J.VLSI.2020.12.003},
timestamp = {Thu, 08 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HanK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/AhnK21,
author = {Byungmin Ahn and
Taewhan Kim},
title = {Common Kernels and Convolutions in Binary- and Ternary-Weight Neural
Networks},
journal = {J. Circuits Syst. Comput.},
volume = {30},
number = {9},
pages = {2150158:1--2150158:19},
year = {2021},
url = {https://doi.org/10.1142/S0218126621501589},
doi = {10.1142/S0218126621501589},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/AhnK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HyunK21,
author = {Gyoung{-}Hwan Hyun and
Taewhan Kim},
title = {Allocation of Multibit Retention Flip-Flops for Power Gated Circuits:
Algorithm-Design Unified Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {5},
pages = {892--903},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3013243},
doi = {10.1109/TCAD.2020.3013243},
timestamp = {Fri, 22 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HyunK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimPK21,
author = {Taehwan Kim and
Heechun Park and
Taewhan Kim},
title = {Allocation of Always-On State Retention Storage for Power Gated Circuits
- Steady-State- Driven Approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {499--511},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3047056},
doi = {10.1109/TVLSI.2020.3047056},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimPK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeoK21,
author = {Jeongwoo Heo and
Taewhan Kim},
title = {Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline
Controller},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1437--1450},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3073383},
doi = {10.1109/TVLSI.2021.3073383},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HeoK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KimJK21,
author = {Suwan Kim and
Kyeongrok Jo and
Taewhan Kim},
title = {Boosting Pin Accessibility Through Cell Layout Topology Diversification},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {183--188},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431567},
doi = {10.1145/3394885.3431567},
timestamp = {Mon, 03 May 2021 16:42:27 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KimJK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KangK21,
author = {Jongsung Kang and
Taewhan Kim},
title = {Speeding up {MUX-FSM} based Stochastic Computing for On-device Neural
Networks},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1526--1529},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474193},
doi = {10.23919/DATE51398.2021.9474193},
timestamp = {Wed, 21 Jul 2021 10:04:34 +0200},
biburl = {https://dblp.org/rec/conf/date/KangK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/BaekK21,
author = {Kyeonghyeon Baek and
Taewhan Kim},
title = {Simultaneous Transistor Folding and Placement in Standard Cell Layout
Synthesis},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--8},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643537},
doi = {10.1109/ICCAD51958.2021.9643537},
timestamp = {Thu, 21 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/BaekK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/JoK21,
author = {Kyeongrok Jo and
Taewhan Kim},
title = {Optimal Transistor Placement Combined with Global In-cell Routing
in Standard Cell Layout Synthesis},
booktitle = {39th {IEEE} International Conference on Computer Design, {ICCD} 2021,
Storrs, CT, USA, October 24-27, 2021},
pages = {517--524},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCD53106.2021.00085},
doi = {10.1109/ICCD53106.2021.00085},
timestamp = {Tue, 28 Dec 2021 14:09:48 +0100},
biburl = {https://dblp.org/rec/conf/iccd/JoK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/YoonCK21,
author = {Jaejoon Yoon and
Sehyeon Chung and
Taewhan Kim},
title = {Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops},
booktitle = {18th International SoC Design Conference, {ISOCC} 2021, Jeju Island,
South Korea, Republic of, October 6-9, 2021},
pages = {169--170},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISOCC53507.2021.9613897},
doi = {10.1109/ISOCC53507.2021.9613897},
timestamp = {Mon, 06 Dec 2021 17:33:24 +0100},
biburl = {https://dblp.org/rec/conf/isocc/YoonCK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/ParkCJACK21,
author = {Heechun Park and
Kyungjoon Chang and
Jooyeon Jeong and
Jaehoon Ahn and
Ki{-}Seok Chung and
Taewhan Kim},
title = {Challenges on {DTCO} Methodology Towards Deep Submicron Interconnect
Technology},
booktitle = {18th International SoC Design Conference, {ISOCC} 2021, Jeju Island,
South Korea, Republic of, October 6-9, 2021},
pages = {215--218},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISOCC53507.2021.9614026},
doi = {10.1109/ISOCC53507.2021.9614026},
timestamp = {Mon, 06 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/ParkCJACK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/KimK21,
author = {Soomin Kim and
Taewhan Kim},
title = {Minimally Allocating Always-on State Retention Storage for Supporting
Power Gating Circuits},
booktitle = {22nd International Symposium on Quality Electronic Design, {ISQED}
2021, Santa Clara, CA, USA, April 7-9, 2021},
pages = {482--487},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISQED51717.2021.9424279},
doi = {10.1109/ISQED51717.2021.9424279},
timestamp = {Wed, 03 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/KimK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/KimK21,
author = {Suwan Kim and
Taewhan Kim},
title = {Practical Approach to Cell Replacement for Resolving Pin Inaccessibility},
booktitle = {64th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2021, Lansing, MI, USA, August 9-11, 2021},
pages = {224--227},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MWSCAS47672.2021.9531691},
doi = {10.1109/MWSCAS47672.2021.9531691},
timestamp = {Wed, 22 Sep 2021 16:10:31 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/KimK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/JeongK21,
author = {Jooyeon Jeong and
Taewhan Kim},
title = {Utilizing Middle-of-Line Resource in Filler Cells for Fixing Routing
Failures},
booktitle = {64th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2021, Lansing, MI, USA, August 9-11, 2021},
pages = {228--231},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MWSCAS47672.2021.9531808},
doi = {10.1109/MWSCAS47672.2021.9531808},
timestamp = {Wed, 22 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/JeongK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/JeongPJK21,
author = {Eunsol Jeong and
Heechun Park and
Jooyeon Jeong and
Taewhan Kim},
title = {Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement},
booktitle = {64th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2021, Lansing, MI, USA, August 9-11, 2021},
pages = {232--235},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MWSCAS47672.2021.9531756},
doi = {10.1109/MWSCAS47672.2021.9531756},
timestamp = {Wed, 22 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/JeongPJK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/KimJP20,
author = {Taewhan Kim and
Kangsoo Jung and
Seog Park},
title = {Sparsity Reduction Technique Using Grouping Method for Matrix Factorization
in Differentially Private Recommendation Systems},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {103-D},
number = {7},
pages = {1683--1692},
year = {2020},
url = {https://doi.org/10.1587/transinf.2019EDP7238},
doi = {10.1587/TRANSINF.2019EDP7238},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicetd/KimJP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KangK20,
author = {Jongsung Kang and
Taewhan Kim},
title = {{PV-MAC:} Multiply-and-accumulate unit structure exploiting precision
variability in on-device convolutional neural networks},
journal = {Integr.},
volume = {71},
pages = {76--85},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2019.11.003},
doi = {10.1016/J.VLSI.2019.11.003},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KangK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KimJCKC20,
author = {Taehwan Kim and
Kwangok Jeong and
Jungyun Choi and
Taewhan Kim and
Kyu{-}Myung Choi},
title = {{SRAM} on-chip monitoring methodology for high yield and energy efficient
memory operation at near threshold voltage},
journal = {Integr.},
volume = {74},
pages = {81--92},
year = {2020},
url = {https://doi.org/10.1016/j.vlsi.2020.04.005},
doi = {10.1016/J.VLSI.2020.04.005},
timestamp = {Thu, 25 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/KimJCKC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HeoJKC20,
author = {Jeongwoo Heo and
Kwangok Jeong and
Taewhan Kim and
Kyu{-}Myung Choi},
title = {Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting
to Near-Threshold Computing and Advanced Process Nodes},
booktitle = {25th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2020, Beijing, China, January 13-16, 2020},
pages = {139--144},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ASP-DAC47756.2020.9045392},
doi = {10.1109/ASP-DAC47756.2020.9045392},
timestamp = {Mon, 30 Mar 2020 12:39:40 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/HeoJKC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HeoK20,
author = {Jeongwoo Heo and
Taewhan Kim},
title = {Lightening Asynchronous Pipeline Controller Through Resynthesis and
Optimization},
booktitle = {25th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2020, Beijing, China, January 13-16, 2020},
pages = {587--592},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ASP-DAC47756.2020.9045358},
doi = {10.1109/ASP-DAC47756.2020.9045358},
timestamp = {Mon, 30 Mar 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/HeoK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/AhnK20,
author = {Byungmin Ahn and
Taewhan Kim},
title = {Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2020, Grenoble, France, March 9-13, 2020},
pages = {73--78},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.23919/DATE48585.2020.9116367},
doi = {10.23919/DATE48585.2020.9116367},
timestamp = {Thu, 25 Jun 2020 12:55:44 +0200},
biburl = {https://dblp.org/rec/conf/date/AhnK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/0007HK20,
author = {Taehwan Kim and
Gyoung{-}Hwan Hyun and
Taewhan Kim},
editor = {David Atienza Alonso and
Qinru Qiu and
Sherief Reda and
Yiran Chen},
title = {Steady state driven power gating for lightening always-on state retention
storage},
booktitle = {{ISLPED} '20: {ACM/IEEE} International Symposium on Low Power Electronics
and Design, Boston, Massachusetts, August 10-12, 2020},
pages = {79--84},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3370748.3406556},
doi = {10.1145/3370748.3406556},
timestamp = {Tue, 05 Jul 2022 15:18:16 +0200},
biburl = {https://dblp.org/rec/conf/islped/0007HK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ParkK19,
author = {Heechun Park and
Taewhan Kim},
title = {Hybrid asynchronous circuit generation amenable to conventional {EDA}
flow},
journal = {Integr.},
volume = {64},
pages = {29--39},
year = {2019},
url = {https://doi.org/10.1016/j.vlsi.2018.07.006},
doi = {10.1016/J.VLSI.2018.07.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ParkK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JoADSKC19,
author = {Kyeongrok Jo and
Seyong Ahn and
Jungho Do and
Taejoong Song and
Taewhan Kim and
Kyu{-}Myung Choi},
title = {Design Rule Evaluation Framework Using Automatic Cell Layout Generator
for Design Technology Co-Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {8},
pages = {1933--1946},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2910579},
doi = {10.1109/TVLSI.2019.2910579},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JoADSKC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HyunK19,
author = {Gyoung{-}Hwan Hyun and
Taewhan Kim},
editor = {David Z. Pan},
title = {Flip-flop State Driven Clock Gating: Concept, Design, and Methodology},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2019, Westminster, CO, USA, November 4-7, 2019},
pages = {1--6},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1109/ICCAD45719.2019.8942061},
doi = {10.1109/ICCAD45719.2019.8942061},
timestamp = {Wed, 19 Feb 2020 16:38:01 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HyunK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HyunK19a,
author = {Gyoung{-}Hwan Hyun and
Taewhan Kim},
editor = {David Z. Pan},
title = {Allocation of State Retention Registers Boosting Practical Applicability
to Power Gated Circuits},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2019, Westminster, CO, USA, November 4-7, 2019},
pages = {1--6},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1109/ICCAD45719.2019.8942064},
doi = {10.1109/ICCAD45719.2019.8942064},
timestamp = {Wed, 19 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HyunK19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/KimJKC19,
author = {Taehwan Kim and
Kwangok Jeong and
Taewhan Kim and
Kyu{-}Myung Choi},
title = {{SRAM} On-Chip Monitoring Methodology for Energy Efficient Memory
Operation at Near Threshold Voltage},
booktitle = {2019 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2019,
Miami, FL, USA, July 15-17, 2019},
pages = {146--151},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISVLSI.2019.00035},
doi = {10.1109/ISVLSI.2019.00035},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/KimJKC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/KimK18,
author = {Youngchan Kim and
Taewhan Kim},
title = {Synthesis and exploration of clock spines},
journal = {{IET} Comput. Digit. Tech.},
volume = {12},
number = {5},
pages = {241--248},
year = {2018},
url = {https://doi.org/10.1049/iet-cdt.2017.0234},
doi = {10.1049/IET-CDT.2017.0234},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/KimK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/JoAKC18,
author = {Kyeongrok Jo and
Seyong Ahn and
Taewhan Kim and
Kyu{-}Myung Choi},
editor = {Youngsoo Shin},
title = {Cohesive techniques for cell layout optimization supporting 2D metal-1
routing completion},
booktitle = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2018, Jeju, Korea (South), January 22-25, 2018},
pages = {500--506},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASPDAC.2018.8297373},
doi = {10.1109/ASPDAC.2018.8297373},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/JoAKC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ParkK18,
author = {Heechun Park and
Taewhan Kim},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Structure optimizations of neuromorphic computing architectures for
deep neural network},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {183--188},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342000},
doi = {10.23919/DATE.2018.8342000},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/ParkK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YangK18,
author = {Giyoung Yang and
Taewhan Kim},
editor = {Iris Bahar},
title = {Design and algorithm for clock gating and flip-flop co-optimization},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {14},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240793},
doi = {10.1145/3240765.3240793},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/iccad/YangK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/KimK18,
author = {Juyeon Kim and
Taewhan Kim},
title = {Energy-optimal dynamic voltage scaling in multicore platforms with
reconfigurable power distribution network},
booktitle = {19th International Symposium on Quality Electronic Design, {ISQED}
2018, Santa Clara, CA, USA, March 13-14, 2018},
pages = {31--36},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISQED.2018.8357261},
doi = {10.1109/ISQED.2018.8357261},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/KimK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/KimK18a,
author = {Joohan Kim and
Taewhan Kim},
title = {Clock buffer and flip-flop co-optimization for reducing peak current
noise},
booktitle = {19th International Symposium on Quality Electronic Design, {ISQED}
2018, Santa Clara, CA, USA, March 13-14, 2018},
pages = {94--99},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISQED.2018.8357271},
doi = {10.1109/ISQED.2018.8357271},
timestamp = {Tue, 15 May 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/KimK18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/AhnK18,
author = {Byungmin Ahn and
Taewhan Kim},
title = {Memory Access Driven Memory Layout and Block Replacement Techniques
for Compressed Deep Neural Networks},
booktitle = {31st {IEEE} International System-on-Chip Conference, {SOCC} 2018,
Arlington, VA, USA, September 4-7, 2018},
pages = {221--226},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/SOCC.2018.8618552},
doi = {10.1109/SOCC.2018.8618552},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/AhnK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KimK17,
author = {Joohan Kim and
Taewhan Kim},
title = {Boundary optimization of buffered clock trees for low power},
journal = {Integr.},
volume = {56},
pages = {86--95},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.10.004},
doi = {10.1016/J.VLSI.2016.10.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KimK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JooK17,
author = {Deokjin Joo and
Taewhan Kim},
title = {Clock buffer polarity assignment under useful skew constraints},
journal = {Integr.},
volume = {57},
pages = {52--61},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2016.11.007},
doi = {10.1016/J.VLSI.2016.11.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JooK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MoonK17,
author = {Hyoungseok Moon and
Taewhan Kim},
title = {Loosely coupled multi-bit flip-flop allocation for power reduction},
journal = {Integr.},
volume = {58},
pages = {125--133},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.006},
doi = {10.1016/J.VLSI.2017.02.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MoonK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimK17,
author = {Juyeon Kim and
Taewhan Kim},
title = {Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {4},
pages = {641--654},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2016.2597213},
doi = {10.1109/TCAD.2016.2597213},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KimK17,
author = {Youngchan Kim and
Taewhan Kim},
title = {Algorithm for synthesis and exploration of clock spines},
booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2017, Chiba, Japan, January 16-19, 2017},
pages = {263--268},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASPDAC.2017.7858330},
doi = {10.1109/ASPDAC.2017.7858330},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KimK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YiK17,
author = {Dongyoun Yi and
Taewhan Kim},
editor = {Sri Parameswaran},
title = {Switch cell optimization of power-gated modern system-on-chips},
booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
pages = {555--560},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICCAD.2017.8203826},
doi = {10.1109/ICCAD.2017.8203826},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/YiK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-ipr/JeonK16,
author = {Hyoungjun Jeon and
Taewhan Kim},
title = {Grey-level context-driven histogram equalisation},
journal = {{IET} Image Process.},
volume = {10},
number = {5},
pages = {349--358},
year = {2016},
url = {https://doi.org/10.1049/iet-ipr.2015.0491},
doi = {10.1049/IET-IPR.2015.0491},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-ipr/JeonK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KimJK16,
author = {Juyeon Kim and
Deokjin Joo and
Taewhan Kim},
title = {Optimal utilization of adjustable delay clock buffers for timing correction
in designs with multiple power modes},
journal = {Integr.},
volume = {52},
pages = {91--101},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.08.005},
doi = {10.1016/J.VLSI.2015.08.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KimJK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AhnKPK16,
author = {Seyong Ahn and
Minseok Kang and
Marios C. Papaefthymiou and
Taewhan Kim},
title = {Design Methodology for Synthesizing Resonant Clock Networks in the
Presence of Dynamic Voltage/Frequency Scaling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {12},
pages = {2068--2081},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2016.2543022},
doi = {10.1109/TCAD.2016.2543022},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AhnKPK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/JooK16,
author = {Deokjin Joo and
Taewhan Kim},
title = {Clock buffer polarity assignment utilizing useful clock skews for
power noise reduction},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {226--231},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7428015},
doi = {10.1109/ASPDAC.2016.7428015},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/JooK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MoonK16,
author = {Hyoungseok Moon and
Taewhan Kim},
title = {Design and allocation of loosely coupled multi-bit flip-flops for
power reduction in post-placement optimization},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {268--273},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7428022},
doi = {10.1109/ASPDAC.2016.7428022},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/MoonK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YiK16,
author = {Dongyoun Yi and
Taewhan Kim},
editor = {Frank Liu},
title = {Allocation of multi-bit flip-flops in logic synthesis for power optimization},
booktitle = {Proceedings of the 35th International Conference on Computer-Aided
Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016},
pages = {33},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2966986.2966998},
doi = {10.1145/2966986.2966998},
timestamp = {Fri, 23 Jun 2023 22:29:48 +0200},
biburl = {https://dblp.org/rec/conf/iccad/YiK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/HeoK16,
author = {Jeongwoo Heo and
Taewhan Kim},
title = {Timing Analysis and Optimization Based on Flexible Flip-Flop Timing
Model},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2016, Pittsburgh,
PA, USA, July 11-13, 2016},
pages = {42--46},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISVLSI.2016.41},
doi = {10.1109/ISVLSI.2016.41},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/HeoK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ParkK16,
author = {Heechun Park and
Taewhan Kim},
title = {Synthesizing Asynchronous Circuits toward Practical Use},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2016, Pittsburgh,
PA, USA, July 11-13, 2016},
pages = {47--52},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISVLSI.2016.29},
doi = {10.1109/ISVLSI.2016.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ParkK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-ipr/CaiK15,
author = {Lu Cai and
Taewhan Kim},
title = {Context-driven hybrid image inpainting},
journal = {{IET} Image Process.},
volume = {9},
number = {10},
pages = {866--873},
year = {2015},
url = {https://doi.org/10.1049/iet-ipr.2015.0184},
doi = {10.1049/IET-IPR.2015.0184},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-ipr/CaiK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParkK15,
author = {Heechun Park and
Taewhan Kim},
title = {Synthesis of {TSV} Fault-Tolerant 3-D Clock Trees},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {34},
number = {2},
pages = {266--279},
year = {2015},
url = {https://doi.org/10.1109/TCAD.2014.2379645},
doi = {10.1109/TCAD.2014.2379645},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ParkK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KimK15,
author = {Juyeon Kim and
Taewhan Kim},
title = {Useful clock skew scheduling using adjustable delay buffers in multi-power
mode designs},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {466--471},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7059050},
doi = {10.1109/ASPDAC.2015.7059050},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KimK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/AhnKPK15,
author = {Seyong Ahn and
Minseok Kang and
Marios C. Papaefthymiou and
Taewhan Kim},
title = {Synthesis of resonant clock networks supporting dynamic voltage /
frequency scaling},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {484--489},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7059053},
doi = {10.1109/ASPDAC.2015.7059053},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/AhnKPK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SeoKKK15,
author = {Hyungjung Seo and
Juyeon Kim and
Minseok Kang and
Taewhan Kim},
editor = {Diana Marculescu and
Frank Liu},
title = {Synthesis for Power-Aware Clock Spines},
booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
pages = {126--131},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCAD.2015.7372559},
doi = {10.1109/ICCAD.2015.7372559},
timestamp = {Mon, 26 Jun 2023 16:43:56 +0200},
biburl = {https://dblp.org/rec/conf/iccad/SeoKKK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/SeoHK15,
author = {Hyungjung Seo and
Jeongwoo Heo and
Taewhan Kim},
title = {Clock skew optimization for maximizing time margin by utilizing flexible
flip-flop timing},
booktitle = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}
2015, Santa Clara, CA, USA, March 2-4, 2015},
pages = {35--39},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISQED.2015.7085394},
doi = {10.1109/ISQED.2015.7085394},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/SeoHK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LeeK14,
author = {Byunghyun Lee and
Taewhan Kim},
title = {Algorithms for {TSV} resource sharing and optimization in designing
3D stacked ICs},
journal = {Integr.},
volume = {47},
number = {2},
pages = {184--194},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.11.001},
doi = {10.1016/J.VLSI.2013.11.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LeeK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ParkK14,
author = {Sangdo Park and
Taewhan Kim},
title = {Edge layer embedding algorithm for mitigating on-package variation
in 3D clock tree synthesis},
journal = {Integr.},
volume = {47},
number = {4},
pages = {476--486},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.12.005},
doi = {10.1016/J.VLSI.2013.12.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ParkK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JooK14,
author = {Deokjin Joo and
Taewhan Kim},
title = {A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and
Low-Power Digital Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {3},
pages = {423--436},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2288698},
doi = {10.1109/TCAD.2013.2288698},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JooK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/KangK14,
author = {Minseok Kang and
Taewhan Kim},
title = {Integrated Resource Allocation and Binding in Clock Mesh Synthesis},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {19},
number = {3},
pages = {30:1--30:28},
year = {2014},
url = {https://doi.org/10.1145/2611762},
doi = {10.1145/2611762},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/KangK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ParkKK14,
author = {Kitae Park and
Geunho Kim and
Taewhan Kim},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Mixed allocation of adjustable delay buffers combined with buffer
sizing in clock tree synthesis of multiple power mode designs},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--4},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.276},
doi = {10.7873/DATE.2014.276},
timestamp = {Fri, 09 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ParkKK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdip/LeeK14,
author = {Myung Woo Lee and
Taewhan Kim},
editor = {Charles M. Falco and
Chin{-}Chen Chang and
Xudong Jiang},
title = {Fast algorithm of low power image reformation for {OLED} display},
booktitle = {Sixth International Conference on Digital Image Processing, {ICDIP}
2014, Athens, Greece, April 5-6, 2014},
series = {{SPIE} Proceedings},
volume = {9159},
pages = {91591H},
publisher = {{SPIE}},
year = {2014},
url = {https://doi.org/10.1117/12.2064407},
doi = {10.1117/12.2064407},
timestamp = {Fri, 22 Sep 2023 15:13:40 +0200},
biburl = {https://dblp.org/rec/conf/icdip/LeeK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/SeoK14,
author = {Hyungjung Seo and
Taewhan Kim},
title = {Post-silicon tunable clock buffer allocation based on fast chip yield
computation},
booktitle = {Fifteenth International Symposium on Quality Electronic Design, {ISQED}
2014, Santa Clara, CA, USA, March 3-5, 2014},
pages = {490--495},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISQED.2014.6783366},
doi = {10.1109/ISQED.2014.6783366},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/SeoK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/ParkK14,
author = {Sangdo Park and
Taewhan Kim},
title = {Post-silicon tuning aware wafer matching algorithm for 3d integration
of ICs},
booktitle = {{IEEE} 57th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2014, College Station, TX, USA, August 3-6, 2014},
pages = {511--514},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/MWSCAS.2014.6908464},
doi = {10.1109/MWSCAS.2014.6908464},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/ParkK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JungK13,
author = {Jongyoon Jung and
Taewhan Kim},
title = {Statistical Viability Analysis for Detecting False Paths Under Delay
Variation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {32},
number = {1},
pages = {111--123},
year = {2013},
url = {https://doi.org/10.1109/TCAD.2012.2211102},
doi = {10.1109/TCAD.2012.2211102},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JungK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimK13,
author = {Tak{-}Yung Kim and
Taewhan Kim},
title = {Resource Allocation and Design Techniques of Prebond Testable 3-D
Clock Tree},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {32},
number = {1},
pages = {138--151},
year = {2013},
url = {https://doi.org/10.1109/TCAD.2012.2212193},
doi = {10.1109/TCAD.2012.2212193},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LimJK13,
author = {Kyoung{-}Hwan Lim and
Deokjin Joo and
Taewhan Kim},
title = {An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical
Extensions for Clock Skew Optimization in Multiple Power Mode Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {32},
number = {3},
pages = {392--405},
year = {2013},
url = {https://doi.org/10.1109/TCAD.2012.2220769},
doi = {10.1109/TCAD.2012.2220769},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LimJK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KimJK13,
author = {Juyeon Kim and
Deokjin Joo and
Taewhan Kim},
title = {An optimal algorithm of adjustable delay buffer insertion for solving
clock skew variation problem},
booktitle = {The 50th Annual Design Automation Conference 2013, {DAC} '13, Austin,
TX, USA, May 29 - June 07, 2013},
pages = {90:1--90:6},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2463209.2488845},
doi = {10.1145/2463209.2488845},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KimJK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ParkK13,
author = {Heechun Park and
Taewhan Kim},
editor = {J{\"{o}}rg Henkel},
title = {Comprehensive technique for designing and synthesizing {TSV} fault-tolerant
3D clock trees},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
ICCAD'13, San Jose, CA, USA, November 18-21, 2013},
pages = {691--696},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ICCAD.2013.6691190},
doi = {10.1109/ICCAD.2013.6691190},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ParkK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/Kim13,
author = {Taewhan Kim},
editor = {Norbert Schuhmann and
Kaijian Shi and
Nagi Naganathan},
title = {Tutorial: Methodology for designing reliable clock networks},
booktitle = {2013 {IEEE} International {SOC} Conference, Erlangen, Germany, September
4-6, 2013},
pages = {141},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/SOCC.2013.6749676},
doi = {10.1109/SOCC.2013.6749676},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/Kim13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/LeeK13,
author = {Byunghyun Lee and
Taewhan Kim},
editor = {Norbert Schuhmann and
Kaijian Shi and
Nagi Naganathan},
title = {High-level {TSV} resource sharing and optimization for {TSV} based
3D {IC} designs},
booktitle = {2013 {IEEE} International {SOC} Conference, Erlangen, Germany, September
4-6, 2013},
pages = {153--158},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/SOCC.2013.6749680},
doi = {10.1109/SOCC.2013.6749680},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/LeeK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cj/SeoSK12,
author = {Hyungjung Seo and
Jaewon Seo and
Taewhan Kim},
title = {Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling},
journal = {Comput. J.},
volume = {55},
number = {11},
pages = {1367--1382},
year = {2012},
url = {https://doi.org/10.1093/comjnl/bxs011},
doi = {10.1093/COMJNL/BXS011},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cj/SeoSK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcse/JooKK12,
author = {Deokjin Joo and
Minseok Kang and
Taewhan Kim},
title = {Design Methodologies for Reliable Clock Networks},
journal = {J. Comput. Sci. Eng.},
volume = {6},
number = {4},
pages = {257--266},
year = {2012},
url = {https://doi.org/10.5626/JCSE.2012.6.4.257},
doi = {10.5626/JCSE.2012.6.4.257},
timestamp = {Thu, 27 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcse/JooKK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JungK12,
author = {Jongyoon Jung and
Taewhan Kim},
title = {Variation-Aware False Path Analysis Based on Statistical Dynamic Timing
Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1684--1697},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2202392},
doi = {10.1109/TCAD.2012.2202392},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JungK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/KimKK12,
author = {YongHwan Kim and
Sanghoon Kwak and
Taewhan Kim},
title = {Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing
Constraint},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {17},
number = {4},
pages = {43:1--43:29},
year = {2012},
url = {https://doi.org/10.1145/2348839.2348847},
doi = {10.1145/2348839.2348847},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/KimKK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KimK12,
author = {Kiyoung Kim and
Taewhan Kim},
title = {Algorithm for synthesizing design context-aware fast carry-skip adders},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {795--800},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6165063},
doi = {10.1109/ASPDAC.2012.6165063},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KimK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/ParkK12,
author = {Sangdo Park and
Taewhan Kim},
title = {Die matching algorithm for enhancing parametric yield of 3D ICs},
booktitle = {International SoC Design Conference, {ISOCC} 2012, Jeju Island, South
Korea, November 4-7, 2012},
pages = {143--146},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISOCC.2012.6407060},
doi = {10.1109/ISOCC.2012.6407060},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isocc/ParkK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/crc/Kim12,
author = {Taewhan Kim},
editor = {Ishfaq Ahmad and
Sanjay Ranka},
title = {Power Saving by Task-Level Dynamic Voltage Scaling},
booktitle = {Handbook of Energy-Aware and Green Computing - Two Volume Set},
pages = {361--383},
publisher = {Chapman and Hall/CRC},
year = {2012},
url = {http://www.crcnetbase.com/doi/abs/10.1201/b16631-21},
doi = {10.1201/B16631-21},
timestamp = {Wed, 12 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/reference/crc/Kim12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JangJK11,
author = {Hochang Jang and
Deokjin Joo and
Taewhan Kim},
title = {Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for
Power/Ground Noise Minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {1},
pages = {96--109},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2066650},
doi = {10.1109/TCAD.2010.2066650},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JangJK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/KimK11,
author = {Tak{-}Yung Kim and
Taewhan Kim},
title = {Clock Tree synthesis for TSV-based 3D {IC} designs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {48:1--48:21},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003708},
doi = {10.1145/2003695.2003708},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/KimK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JungK11,
author = {Jongyoon Jung and
Taewhan Kim},
title = {Scheduling and Resource Binding Algorithm Considering Timing Variation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {2},
pages = {205--216},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2009.2031676},
doi = {10.1109/TVLSI.2009.2031676},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JungK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeJK11,
author = {Yongho Lee and
Deog{-}Kyoon Jeong and
Taewhan Kim},
title = {Comprehensive Analysis and Control of Design Parameters for Power
Gated Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {3},
pages = {494--498},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2009.2033700},
doi = {10.1109/TVLSI.2009.2033700},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeJK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LimK11,
author = {Kyoung{-}Hwan Lim and
Taewhan Kim},
title = {An optimal algorithm for allocation, placement, and delay assignment
of adjustable delay buffers for clock skew minimization in multi-voltage
mode designs},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {503--508},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722242},
doi = {10.1109/ASPDAC.2011.5722242},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LimK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LeeK11,
author = {Yongho Lee and
Taewhan Kim},
title = {A fine-grained technique of NBTI-aware voltage scaling and body biasing
for standard cell based designs},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {603--608},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722260},
doi = {10.1109/ASPDAC.2011.5722260},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LeeK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/JooK11,
author = {Deokjin Joo and
Taewhan Kim},
editor = {Leon Stok and
Nikil D. Dutt and
Soha Hassoun},
title = {WaveMin: a fine-grained clock buffer polarity assignment combined
with buffer sizing},
booktitle = {Proceedings of the 48th Design Automation Conference, {DAC} 2011,
San Diego, California, USA, June 5-10, 2011},
pages = {522--527},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2024724.2024846},
doi = {10.1145/2024724.2024846},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/JooK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/KimK11,
author = {Joohan Kim and
Taewhan Kim},
title = {A fine-grained timing driven synthesis of arithmetic circuits},
booktitle = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea,
November 17-18, 2011},
pages = {80--83},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISOCC.2011.6138651},
doi = {10.1109/ISOCC.2011.6138651},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isocc/KimK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/KimKLPJK11,
author = {YongHwan Kim and
Minseok Kang and
Kyoung{-}Hwan Lim and
Sangdo Park and
Deokjin Joo and
Taewhan Kim},
title = {Clock design techniques considering circuit reliability},
booktitle = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea,
November 17-18, 2011},
pages = {142--145},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISOCC.2011.6138667},
doi = {10.1109/ISOCC.2011.6138667},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isocc/KimKLPJK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/ParkK11,
author = {Sangdo Park and
Taewhan Kim},
title = {An energy-optimal algorithm for temperature-aware idle time distribution
considering mode transition overhead},
booktitle = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea,
November 17-18, 2011},
pages = {381--384},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISOCC.2011.6138790},
doi = {10.1109/ISOCC.2011.6138790},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isocc/ParkK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cj/ChonK10,
author = {HaNeul Chon and
Taewhan Kim},
title = {Resource Sharing Problem of Timing Variation-Aware Task Scheduling
and Binding in MPSoC},
journal = {Comput. J.},
volume = {53},
number = {7},
pages = {883--894},
year = {2010},
url = {https://doi.org/10.1093/comjnl/bxp098},
doi = {10.1093/COMJNL/BXP098},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cj/ChonK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcse/Kim10,
author = {Taewhan Kim},
title = {Task-Level Dynamic Voltage Scaling for Embedded System Design: Recent
Theoretical Results},
journal = {J. Comput. Sci. Eng.},
volume = {4},
number = {3},
pages = {189--206},
year = {2010},
url = {https://doi.org/10.5626/jcse.2010.4.3.189},
doi = {10.5626/JCSE.2010.4.3.189},
timestamp = {Fri, 10 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcse/Kim10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PaikSKS10,
author = {Seungwhun Paik and
Insup Shin and
Taewhan Kim and
Youngsoo Shin},
title = {HLS-l: {A} High-Level Synthesis Framework for Latch-Based Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {5},
pages = {657--670},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2043588},
doi = {10.1109/TCAD.2010.2043588},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PaikSKS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LeeK10,
author = {Yongho Lee and
Taewhan Kim},
title = {Technique for controlling power-mode transition noise in distributed
sleep transistor network},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {131--136},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419908},
doi = {10.1109/ASPDAC.2010.5419908},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LeeK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KimK10,
author = {Tak{-}Yung Kim and
Taewhan Kim},
title = {Clock tree embedding for 3D ICs},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {486--491},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419833},
doi = {10.1109/ASPDAC.2010.5419833},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KimK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KimK10,
author = {Tak{-}Yung Kim and
Taewhan Kim},
editor = {Sachin S. Sapatnekar},
title = {Clock tree synthesis with pre-bond testability for 3D stacked {IC}
designs},
booktitle = {Proceedings of the 47th Design Automation Conference, {DAC} 2010,
Anaheim, California, USA, July 13-18, 2010},
pages = {723--728},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1837274.1837456},
doi = {10.1145/1837274.1837456},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KimK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/green/KimK10,
author = {Tak{-}Yung Kim and
Taewhan Kim},
title = {Bounded skew clock routing for 3D stacked {IC} designs: Enabling trade-offs
between power and clock skew},
booktitle = {International Green Computing Conference 2010, Chicago, IL, USA, 15-18
August 2010},
pages = {525--532},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/GREENCOMP.2010.5598269},
doi = {10.1109/GREENCOMP.2010.5598269},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/green/KimK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ParkLKK10,
author = {Danbee Park and
Jungseob Lee and
Nam Sung Kim and
Taewhan Kim},
editor = {Louis Scheffer and
Joel R. Phillips and
Alan J. Hu},
title = {Optimal algorithm for profile-based power gating: {A} compiler technique
for reducing leakage on execution units in microprocessors},
booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010,
San Jose, CA, USA, November 7-11, 2010},
pages = {361--364},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICCAD.2010.5653652},
doi = {10.1109/ICCAD.2010.5653652},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ParkLKK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/KangK10,
author = {Minseok Kang and
Taewhan Kim},
title = {Clock buffer polarity assignment considering the effect of delay variations},
booktitle = {11th International Symposium on Quality of Electronic Design {(ISQED}
2010), 22-24 March 2010, San Jose, CA, {USA}},
pages = {69--74},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISQED.2010.5450398},
doi = {10.1109/ISQED.2010.5450398},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/KangK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/SchaferK09,
author = {Benjamin Carri{\'{o}}n Sch{\"{a}}fer and
Taewhan Kim},
title = {Autonomous temperature control technique in {VLSI} circuits through
logic replication},
journal = {{IET} Comput. Digit. Tech.},
volume = {3},
number = {1},
pages = {62--71},
year = {2009},
url = {https://doi.org/10.1049/iet-cdt:20070159},
doi = {10.1049/IET-CDT:20070159},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cdt/SchaferK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/LimKK09,
author = {Kyoung{-}Hwan Lim and
YongHwan Kim and
Taewhan Kim},
title = {Interconnect and communication synthesis for distributed register-file
microarchitecture},
journal = {{IET} Comput. Digit. Tech.},
volume = {3},
number = {2},
pages = {162--174},
year = {2009},
url = {https://doi.org/10.1049/iet-cdt:20080019},
doi = {10.1049/IET-CDT:20080019},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/LimKK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/LimCK09,
author = {Pilok Lim and
Ki{-}Seok Chung and
Taewhan Kim},
title = {Thermal-Aware High-Level Synthesis Based on Network Flow Method},
journal = {J. Circuits Syst. Comput.},
volume = {18},
number = {5},
pages = {965--984},
year = {2009},
url = {https://doi.org/10.1142/S0218126609005472},
doi = {10.1142/S0218126609005472},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/LimCK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LeeCKEK09,
author = {Byunghyun Lee and
Ki{-}Seok Chung and
Bontae Koo and
Nak{-}Woong Eum and
Taewhan Kim},
title = {Thermal sensor allocation and placement for reconfigurable systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {14},
number = {4},
pages = {50:1--50:23},
year = {2009},
url = {https://doi.org/10.1145/1562514.1562518},
doi = {10.1145/1562514.1562518},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LeeCKEK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChonK09,
author = {HaNeul Chon and
Taewhan Kim},
editor = {Kazutoshi Wakabayashi},
title = {Timing variation-aware task scheduling and binding for MPSoC},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {137--142},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796470},
doi = {10.1109/ASPDAC.2009.4796470},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChonK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/JangK09,
author = {Hochang Jang and
Taewhan Kim},
title = {Simultaneous clock buffer sizing and polarity assignment for power/ground
noise minimization},
booktitle = {Proceedings of the 46th Design Automation Conference, {DAC} 2009,
San Francisco, CA, USA, July 26-31, 2009},
pages = {794--799},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629911.1630115},
doi = {10.1145/1629911.1630115},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/JangK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/JungK09,
author = {Jongyoon Jung and
Taewhan Kim},
title = {Timing variation-aware high-level synthesis considering accurate yield
computation},
booktitle = {27th International Conference on Computer Design, {ICCD} 2009, Lake
Tahoe, CA, USA, October 4-7, 2009},
pages = {207--212},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ICCD.2009.5413152},
doi = {10.1109/ICCD.2009.5413152},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/JungK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/HaCKFMY08,
author = {Soonhoi Ha and
Kiyoung Choi and
Taewhan Kim and
Kriszti{\'{a}}n Flautner and
Sang Lyul Min and
Wang Yi},
title = {Introduction to embedded systems week 2006 special issue},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {7},
number = {2},
pages = {8:1--8:3},
year = {2008},
url = {https://doi.org/10.1145/1331331.1331332},
doi = {10.1145/1331331.1331332},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/HaCKFMY08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SchaferK08,
author = {Benjamin Carri{\'{o}}n Sch{\"{a}}fer and
Taewhan Kim},
title = {Hotspots Elimination and Temperature Flattening in {VLSI} Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {11},
pages = {1475--1487},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.2001140},
doi = {10.1109/TVLSI.2008.2001140},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SchaferK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/JungK08,
author = {Jongyoon Jung and
Taewhan Kim},
title = {Timing variation-aware high level synthesis: Current results and research
challenges},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2008,
Macao, China, November 30 2008 - December 3, 2008},
pages = {1004--1007},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/APCCAS.2008.4746194},
doi = {10.1109/APCCAS.2008.4746194},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/JungK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LeeK08,
author = {Byunghyun Lee and
Taewhan Kim},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Optimal allocation and placement of thermal sensors for reconfigurable
systems and its practical extension},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {703--707},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4484042},
doi = {10.1109/ASPDAC.2008.4484042},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LeeK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LeeJK08,
author = {Yongho Lee and
Deog{-}Kyoon Jeong and
Taewhan Kim},
editor = {Sani R. Nassif and
Jaijeet S. Roychowdhury},
title = {Simultaneous control of power/ground current, wakeup time and transistor
overhead in power gated circuits},
booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008,
San Jose, CA, USA, November 10-13, 2008},
pages = {169--172},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCAD.2008.4681569},
doi = {10.1109/ICCAD.2008.4681569},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LeeJK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/RyuK08,
author = {Yesin Ryu and
Taewhan Kim},
editor = {Sani R. Nassif and
Jaijeet S. Roychowdhury},
title = {Clock buffer polarity assignment combined with clock tree generation
for power/ground noise minimization},
booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008,
San Jose, CA, USA, November 10-13, 2008},
pages = {416--419},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCAD.2008.4681608},
doi = {10.1109/ICCAD.2008.4681608},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/RyuK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ChoiSKS08,
author = {Eunjoo Choi and
Changsik Shin and
Taewhan Kim and
Youngsoo Shin},
editor = {Vijaykrishnan Narayanan and
C. P. Ravikumar and
J{\"{o}}rg Henkel and
Ali Keshavarzi and
Vojin G. Oklobdzija and
Barry M. Pangrle},
title = {Power-gating-aware high-level synthesis},
booktitle = {Proceedings of the 2008 International Symposium on Low Power Electronics
and Design, 2008, Bangalore, India, August 11-13, 2008},
pages = {39--44},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1393921.1393936},
doi = {10.1145/1393921.1393936},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/ChoiSKS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimK07,
author = {Taewhan Kim and
Jungeun Kim},
title = {Integration of Code Scheduling, Memory Allocation, and Array Binding
for Memory-Access Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {1},
pages = {142--151},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.882639},
doi = {10.1109/TCAD.2006.882639},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoiCK07,
author = {Yongseok Choi and
Naehyuck Chang and
Taewhan Kim},
title = {{DC-DC} Converter-Aware Power Management for Low-Power Embedded Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {8},
pages = {1367--1381},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.890837},
doi = {10.1109/TCAD.2007.890837},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoiCK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LimKK07,
author = {Kyoung{-}Hwan Lim and
YongHwan Kim and
Taewhan Kim},
title = {Interconnect and Communication Synthesis for Distributed Register-File
Microarchitecture},
booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007,
San Diego, CA, USA, June 4-8, 2007},
pages = {765--770},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1145/1278480.1278672},
doi = {10.1145/1278480.1278672},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LimKK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/JungK07,
author = {Jongyoon Jung and
Taewhan Kim},
editor = {Georges G. E. Gielen},
title = {Timing variation-aware high-level synthesis},
booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
San Jose, CA, USA, November 5-8, 2007},
pages = {424--428},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICCAD.2007.4397302},
doi = {10.1109/ICCAD.2007.4397302},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/JungK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiK07,
author = {Zhenmin Li and
Taewhan Kim},
title = {Address Code Optimization Exploiting Code Scheduling in {DSP} Applications},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {1573--1576},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378713},
doi = {10.1109/ISCAS.2007.378713},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LiK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtcsa/SchaferLK07,
author = {Benjamin Carri{\'{o}}n Sch{\"{a}}fer and
Yongho Lee and
Taewhan Kim},
title = {Temperature-Aware Compilation for VLIWProcessors},
booktitle = {13th {IEEE} International Conference on Embedded and Real-Time Computing
Systems and Applications {(RTCSA} 2007), 21-24 August 2007, Daegu,
Korea},
pages = {426--431},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/RTCSA.2007.69},
doi = {10.1109/RTCSA.2007.69},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rtcsa/SchaferLK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/cases/2007,
editor = {Taewhan Kim and
Pascal Sainrat and
Steven S. Lumetta and
Nacho Navarro},
title = {Proceedings of the 2007 International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems, {CASES} 2007, Salzburg, Austria,
September 30 - October 3, 2007},
publisher = {{ACM}},
year = {2007},
timestamp = {Fri, 23 Nov 2007 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/2007.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/ChoiK06,
author = {Yoonseo Choi and
Taewhan Kim},
title = {Memory Access Driven Storage Assignment for Variables in Embedded
System Design},
journal = {J. Circuits Syst. Comput.},
volume = {15},
number = {2},
pages = {145--168},
year = {2006},
url = {https://doi.org/10.1142/S0218126606003003},
doi = {10.1142/S0218126606003003},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/ChoiK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeoKL06,
author = {Jaewon Seo and
Taewhan Kim and
Joonwon Lee},
title = {Optimal intratask dynamic voltage-scaling technique and its practical
extensions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {47--57},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.853703},
doi = {10.1109/TCAD.2005.853703},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SeoKL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ShinK06,
author = {Jong{-}U. Shin and
Taewhan Kim},
title = {Technique for Transition Energy-Aware Dynamic Voltage Assignment},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {53-II},
number = {9},
pages = {956--960},
year = {2006},
url = {https://doi.org/10.1109/TCSII.2006.881808},
doi = {10.1109/TCSII.2006.881808},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ShinK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/UmK06,
author = {Junhyung Um and
Taewhan Kim},
title = {Resource Sharing Combined with Layout Effects in High-Level Synthesis},
journal = {J. {VLSI} Signal Process.},
volume = {44},
number = {3},
pages = {231--243},
year = {2006},
url = {https://doi.org/10.1007/s11265-006-8537-7},
doi = {10.1007/S11265-006-8537-7},
timestamp = {Wed, 20 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/UmK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/KimK06,
author = {Young{-}Jun Kim and
Taewhan Kim},
title = {A {HW/SW} Partitioner for Multi-Mode Multi-Task Embedded Applications},
journal = {J. {VLSI} Signal Process.},
volume = {44},
number = {3},
pages = {269--283},
year = {2006},
url = {https://doi.org/10.1007/s11265-006-8539-5},
doi = {10.1007/S11265-006-8539-5},
timestamp = {Wed, 20 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/KimK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/LimK06,
author = {Pilok Lim and
Taewhan Kim},
editor = {Reinaldo A. Bergamaschi and
Kiyoung Choi},
title = {Thermal-aware high-level synthesis based on network flow method},
booktitle = {Proceedings of the 4th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2006, Seoul, Korea, October
22-25, 2006},
pages = {124--129},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1176254.1176285},
doi = {10.1145/1176254.1176285},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/LimK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/UmKHKCKEK06,
author = {Junhyung Um and
Woo{-}Cheol Kwon and
Sungpack Hong and
Young{-}Taek Kim and
Kyu{-}Myung Choi and
Jeong{-}Taek Kong and
Soo{-}Kwan Eo and
Taewhan Kim},
editor = {Georges G. E. Gielen},
title = {A systematic {IP} and bus subsystem modeling for platform-based system
design},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {560--564},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.243954},
doi = {10.1109/DATE.2006.243954},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/UmKHKCKEK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/KimK06,
author = {Young{-}Jun Kim and
Taewhan Kim},
editor = {Gang Qu and
Yehea I. Ismail and
Narayanan Vijaykrishnan and
Hai Zhou},
title = {{HW/SW} partitioning techniques for multi-mode multi-task embedded
applications},
booktitle = {Proceedings of the 16th {ACM} Great Lakes Symposium on {VLSI} 2006,
Philadelphia, PA, USA, April 30 - May 1, 2006},
pages = {25--30},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1127908.1127917},
doi = {10.1145/1127908.1127917},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/KimK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtcsa/Kim06,
author = {Taewhan Kim},
title = {Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling},
booktitle = {12th {IEEE} Conference on Embedded and Real-Time Computing Systems
and Applications {(RTCSA} 2006), 16-18 August 2006, Sydney, Australia},
pages = {199--206},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/RTCSA.2006.16},
doi = {10.1109/RTCSA.2006.16},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rtcsa/Kim06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/cases/2006,
editor = {Seongsoo Hong and
Wayne H. Wolf and
Kriszti{\'{a}}n Flautner and
Taewhan Kim},
title = {Proceedings of the 2006 International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems, {CASES} 2006, Seoul, Korea, October
22-25, 2006},
publisher = {{ACM}},
year = {2006},
isbn = {1-59593-543-6},
timestamp = {Tue, 02 Aug 2016 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cases/2006.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoiKH05,
author = {Yoonseo Choi and
Taewhan Kim and
Hwansoo Han},
title = {Memory layout techniques for variables utilizing efficient {DRAM}
access modes in embedded system design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {2},
pages = {278--287},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2004.837721},
doi = {10.1109/TCAD.2004.837721},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoiKH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/KwonK05,
author = {Woo{-}Cheol Kwon and
Taewhan Kim},
title = {Optimal voltage allocation techniques for dynamically variable voltage
processors},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {4},
number = {1},
pages = {211--230},
year = {2005},
url = {https://doi.org/10.1145/1053271.1053280},
doi = {10.1145/1053271.1053280},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/KwonK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KimK05,
author = {Jungeun Kim and
Taewhan Kim},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Memory access optimization through combined code scheduling, memory
allocation, and array binding in embedded system design},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {105--110},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065611},
doi = {10.1145/1065579.1065611},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KimK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChoiCK05,
author = {Yongseok Choi and
Naehyuck Chang and
Taewhan Kim},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {{DC-DC} converter-aware power management for battery-operated embedded
systems},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {895--900},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065814},
doi = {10.1145/1065579.1065814},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ChoiCK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SeoKD05,
author = {Jaewon Seo and
Taewhan Kim and
Nikil D. Dutt},
title = {Optimal integration of inter-task and intra-task dynamic voltage scaling
techniques for hard real-time applications},
booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
San Jose, CA, USA, November 6-10, 2005},
pages = {450--455},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCAD.2005.1560110},
doi = {10.1109/ICCAD.2005.1560110},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SeoKD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/EumKK04,
author = {Nak{-}Woong Eum and
Taewhan Kim and
Chong{-}Min Kyung},
title = {CeRA: {A} Router for Symmetrical FPGAs Based on Exact Routing Density
Evaluation},
journal = {{IEEE} Trans. Computers},
volume = {53},
number = {7},
pages = {829--842},
year = {2004},
url = {https://doi.org/10.1109/TC.2004.20},
doi = {10.1109/TC.2004.20},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/EumKK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LyuhKK04,
author = {Chun{-}Gi Lyuh and
Taewhan Kim and
Ki{-}Wook Kim},
title = {Coupling-aware high-level interconnect synthesis {[IC} layout]},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {23},
number = {1},
pages = {157--164},
year = {2004},
url = {https://doi.org/10.1109/TCAD.2003.819892},
doi = {10.1109/TCAD.2003.819892},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LyuhKK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShinK04,
author = {Keoncheol Shin and
Taewhan Kim},
title = {Tight integration of timing-driven synthesis and placement of parallel
multiplier circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {12},
number = {7},
pages = {766--775},
year = {2004},
url = {https://doi.org/10.1109/TVLSI.2004.830914},
doi = {10.1109/TVLSI.2004.830914},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShinK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ShinK04,
author = {Keoncheol Shin and
Taewhan Kim},
editor = {Masaharu Imai},
title = {An integrated approach to timing-driven synthesis and placement of
arithmetic circuits},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {155--158},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.47},
doi = {10.1109/ASPDAC.2004.47},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ShinK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChoiK04,
author = {Yoonseo Choi and
Taewhan Kim},
editor = {Masaharu Imai},
title = {Memory access driven storage assignment for variables in embedded
system design},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {478--481},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.132},
doi = {10.1109/ASPDAC.2004.132},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ChoiK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChaLK04,
author = {Meeyoung Cha and
Chun{-}Gi Lyuh and
Taewhan Kim},
editor = {Masaharu Imai},
title = {Resource-constrained low-power bus encoding with crosstalk delay elimination},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {834--837},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.175},
doi = {10.1109/ASPDAC.2004.175},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ChaLK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LyuhK04,
author = {Chun{-}Gi Lyuh and
Taewhan Kim},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {Memory access scheduling and binding considering energy minimization
in multi-bank memory systems},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {81--86},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996596},
doi = {10.1145/996566.996596},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LyuhK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SeoKC04,
author = {Jaewon Seo and
Taewhan Kim and
Ki{-}Seok Chung},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {Profile-based optimal intra-task voltage scheduling for hard real-time
applications},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {87--92},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996597},
doi = {10.1145/996566.996597},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SeoKC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ShinK04,
author = {Keoncheol Shin and
Taewhan Kim},
editor = {David Garrett and
John C. Lach and
Charles A. Zukowski},
title = {Leakage power minimization for the synthesis of parallel multiplier
circuits},
booktitle = {Proceedings of the 14th {ACM} Great Lakes Symposium on {VLSI} 2004,
Boston, MA, USA, April 26-28, 2004},
pages = {166--169},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/988952.988993},
doi = {10.1145/988952.988993},
timestamp = {Fri, 20 Aug 2021 16:30:37 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ShinK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/HongK03,
author = {Sungpack Hong and
Taewhan Kim},
title = {Bus Optimization for Low Power in High-Level Synthesis},
journal = {J. Circuits Syst. Comput.},
volume = {12},
number = {1},
pages = {1--18},
year = {2003},
url = {https://doi.org/10.1142/S0218126603000829},
doi = {10.1142/S0218126603000829},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/HongK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoiK03,
author = {Yoonseo Choi and
Taewhan Kim},
title = {Address assignment in {DSP} code generation - an integrated approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {8},
pages = {976--984},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.814955},
doi = {10.1109/TCAD.2003.814955},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoiK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/UmK03,
author = {Junhyung Um and
Taewhan Kim},
title = {Synthesis of arithmetic circuits considering layout effects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {11},
pages = {1487--1503},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.818301},
doi = {10.1109/TCAD.2003.818301},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/UmK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/KimJKK03,
author = {Ki{-}Wook Kim and
Seong{-}Ook Jung and
Taewhan Kim and
Sung{-}Mo Kang},
title = {Minimum delay optimization for domino circuits - a coupling-aware
approach},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {8},
number = {2},
pages = {202--213},
year = {2003},
url = {https://doi.org/10.1145/762488.762491},
doi = {10.1145/762488.762491},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/KimJKK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LyuhK03,
author = {Chun{-}Gi Lyuh and
Taewhan Kim},
title = {High-level synthesis for low power based on network flow method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {364--375},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.810796},
doi = {10.1109/TVLSI.2003.810796},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LyuhK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimJKSLK03,
author = {Ki{-}Wook Kim and
Seong{-}Ook Jung and
Taewhan Kim and
Prashant Saxena and
C. L. Liu and
S.{-}M. S. Kang},
title = {Coupling delay optimization by temporal decorrelation using dual threshold
voltage technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {879--887},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817111},
doi = {10.1109/TVLSI.2003.817111},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimJKSLK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeoKP03,
author = {Jaewon Seo and
Taewhan Kim and
Preeti Ranjan Panda},
title = {Memory allocation and mapping in high-level synthesis - an integrated
approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {928--938},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.817116},
doi = {10.1109/TVLSI.2003.817116},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeoKP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KwonK03,
author = {Woo{-}Cheol Kwon and
Taewhan Kim},
title = {Optimal voltage allocation techniques for dynamically variable voltage
processors},
booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003,
Anaheim, CA, USA, June 2-6, 2003},
pages = {125--130},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/775832.775867},
doi = {10.1145/775832.775867},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KwonK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChoiK03,
author = {Yoonseo Choi and
Taewhan Kim},
title = {Memory layout techniques for variables utilizing efficient {DRAM}
access modes in embedded system design},
booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003,
Anaheim, CA, USA, June 2-6, 2003},
pages = {881--886},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/775832.776053},
doi = {10.1145/775832.776053},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ChoiK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/UmK03,
author = {Junhyung Um and
Taewhan Kim},
title = {Code Placement with Selective Cache Activity Minimization for Embedded
Real-time Software Design},
booktitle = {2003 International Conference on Computer-Aided Design, {ICCAD} 2003,
San Jose, CA, USA, November 9-13, 2003},
pages = {197--200},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257634},
doi = {10.1109/ICCAD.2003.1257634},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/UmK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/UmLPJK03,
author = {Junhyung Um and
Sangwoo Lee and
Youngsoo Park and
Sungik Jun and
Taewhan Kim},
title = {An efficient inverse multiplier/divider architecture for cryptography
systems},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {149--152},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1206213},
doi = {10.1109/ISCAS.2003.1206213},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/UmLPJK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/ChungKL02,
author = {Ki{-}Seok Chung and
Taewhan Kim and
C. L. Liu},
title = {A Complete Model for Glitch Analysis in Logic Circuits},
journal = {J. Circuits Syst. Comput.},
volume = {11},
number = {2},
pages = {137--154},
year = {2002},
url = {https://doi.org/10.1142/S0218126602000367},
doi = {10.1142/S0218126602000367},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/ChungKL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/ChoiK02,
author = {Yoonseo Choi and
Taewhan Kim},
title = {Binding Algorithm for Power Optimization Based on Network Flow Method},
journal = {J. Circuits Syst. Comput.},
volume = {11},
number = {3},
pages = {259--272},
year = {2002},
url = {https://doi.org/10.1142/S0218126602000422},
doi = {10.1142/S0218126602000422},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/ChoiK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimKLK02,
author = {Ki{-}Wook Kim and
Taewhan Kim and
C. L. Liu and
Sung{-}Mo Kang},
title = {Domino logic synthesis based on implication graph},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {2},
pages = {232--240},
year = {2002},
url = {https://doi.org/10.1109/43.980261},
doi = {10.1109/43.980261},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimKLK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/KimKHKL02,
author = {Ki{-}Wook Kim and
Taewhan Kim and
TingTing Hwang and
Sung{-}Mo Kang and
C. L. Liu},
title = {Logic transformation for low-power synthesis},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {7},
number = {2},
pages = {265--283},
year = {2002},
url = {https://doi.org/10.1145/544536.544539},
doi = {10.1145/544536.544539},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/KimKHKL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/ChungGKL02,
author = {Ki{-}Seok Chung and
Rajesh K. Gupta and
Taewhan Kim and
C. L. Liu},
title = {Synthesis and Optimization of Combinational Interface Circuits},
journal = {J. {VLSI} Signal Process.},
volume = {31},
number = {3},
pages = {243--261},
year = {2002},
url = {https://doi.org/10.1023/A:1015413306258},
doi = {10.1023/A:1015413306258},
timestamp = {Wed, 20 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/ChungGKL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/UmK02,
author = {Junhyung Um and
Taewhan Kim},
title = {Layout-aware synthesis of arithmetic circuits},
booktitle = {Proceedings of the 39th Design Automation Conference, {DAC} 2002,
New Orleans, LA, USA, June 10-14, 2002},
pages = {207--212},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/513918.513971},
doi = {10.1145/513918.513971},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/UmK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChoiK02,
author = {Yoonseo Choi and
Taewhan Kim},
title = {Address assignment combined with scheduling in {DSP} code generation},
booktitle = {Proceedings of the 39th Design Automation Conference, {DAC} 2002,
New Orleans, LA, USA, June 10-14, 2002},
pages = {225--230},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/513918.513975},
doi = {10.1145/513918.513975},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ChoiK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SeoKP02,
author = {Jaewon Seo and
Taewhan Kim and
Preeti Ranjan Panda},
title = {An integrated algorithm for memory allocation and assignment in high-level
synthesis},
booktitle = {Proceedings of the 39th Design Automation Conference, {DAC} 2002,
New Orleans, LA, USA, June 10-14, 2002},
pages = {608--611},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/513918.514072},
doi = {10.1145/513918.514072},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SeoKP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LyuhKK02,
author = {Chun{-}Gi Lyuh and
Taewhan Kim and
Ki{-}Wook Kim},
editor = {Lawrence T. Pileggi and
Andreas Kuehlmann},
title = {Coupling-aware high-level interconnect synthesis for low power},
booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided
Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002},
pages = {609--613},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1145/774572.774662},
doi = {10.1145/774572.774662},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LyuhKK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/UmKK02,
author = {Junhyung Um and
Jae{-}Hoon Kim and
Taewhan Kim},
editor = {Lawrence T. Pileggi and
Andreas Kuehlmann},
title = {Layout-driven resource sharing in high-level synthesis},
booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided
Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002},
pages = {614--618},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1145/774572.774663},
doi = {10.1145/774572.774663},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/UmKK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/NarayananCK02,
author = {Unni Narayanan and
Ki{-}Seok Chung and
Taewhan Kim},
title = {Enhanced bus invert encodings for low-power},
booktitle = {Proceedings of the 2002 International Symposium on Circuits and Systems,
{ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
pages = {25--28},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ISCAS.2002.1010631},
doi = {10.1109/ISCAS.2002.1010631},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/NarayananCK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SeoK02,
author = {Jaewon Seo and
Taewhan Kim},
title = {Memory exploration utilizing scheduling effects in high-level synthesis},
booktitle = {Proceedings of the 2002 International Symposium on Circuits and Systems,
{ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
pages = {73--76},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ISCAS.2002.1010391},
doi = {10.1109/ISCAS.2002.1010391},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SeoK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChoiK02,
author = {Yoonseo Choi and
Taewhan Kim},
title = {An efficient low-power binding algorithm in high-level synthesis},
booktitle = {Proceedings of the 2002 International Symposium on Circuits and Systems,
{ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
pages = {321--324},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ISCAS.2002.1010455},
doi = {10.1109/ISCAS.2002.1010455},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChoiK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChoiK02a,
author = {Yoonseo Choi and
Taewhan Kim},
title = {Address code optimization using code scheduling for digital signal
processors},
booktitle = {Proceedings of the 2002 International Symposium on Circuits and Systems,
{ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
pages = {481--484},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ISCAS.2002.1010745},
doi = {10.1109/ISCAS.2002.1010745},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChoiK02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/UmK01,
author = {Junhyung Um and
Taewhan Kim},
title = {An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits},
journal = {{IEEE} Trans. Computers},
volume = {50},
number = {3},
pages = {215--233},
year = {2001},
url = {https://doi.org/10.1109/12.910813},
doi = {10.1109/12.910813},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/UmK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/ChungKL01,
author = {Ki{-}Seok Chung and
Taewhan Kim and
C. L. Liu},
title = {G-vector: {A} New Model for Glitch Analysis in Logic Circuits},
journal = {J. {VLSI} Signal Process.},
volume = {27},
number = {3},
pages = {235--251},
year = {2001},
url = {https://doi.org/10.1023/A:1008139232134},
doi = {10.1023/A:1008139232134},
timestamp = {Wed, 20 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/ChungKL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KimK01,
author = {Youngtae Kim and
Taewhan Kim},
editor = {Satoshi Goto},
title = {Accurate exploration of timing and area trade-offs in arithmetic optimization
using carry-save-adders},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {622--628},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370565},
doi = {10.1145/370155.370565},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KimK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KimCL01,
author = {Taewhan Kim and
Ki{-}Seok Chung and
Chien{-}Liang Liu},
title = {A Static Estimation Technique of Power Sensitivity in Logic Circuits},
booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001,
Las Vegas, NV, USA, June 18-22, 2001},
pages = {215--219},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/378239.378466},
doi = {10.1145/378239.378466},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KimCL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/EumKK01,
author = {Nak{-}Woong Eum and
Taewhan Kim and
Chong{-}Min Kyung},
editor = {Kaushik Roy and
Sung{-}Mo Kang and
Cheng{-}Kok Koh},
title = {An accurate evaluation of routing density for symmetrical FPGAs},
booktitle = {Proceedings of the 11th {ACM} Great Lakes Symposium on {VLSI} 2001,
West Lafayette, Indiana, USA, 2001},
pages = {51--55},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368122.368794},
doi = {10.1145/368122.368794},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/EumKK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/EumKK01,
author = {Nak{-}Woong Eum and
Taewhan Kim and
Chong{-}Min Kyung},
editor = {Rolf Ernst},
title = {A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation},
booktitle = {Proceedings of the 2001 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2001, San Jose, CA, USA, November 4-8, 2001},
pages = {137--143},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICCAD.2001.968610},
doi = {10.1109/ICCAD.2001.968610},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/EumKK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LyuhKL01,
author = {Chun{-}Gi Lyuh and
Taewhan Kim and
Chien{-}Liang Liu},
editor = {Rolf Ernst},
title = {An Integrated Data Path Optimization for Low Power Based on Network
Flow Method},
booktitle = {Proceedings of the 2001 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2001, San Jose, CA, USA, November 4-8, 2001},
pages = {553--559},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICCAD.2001.968704},
doi = {10.1109/ICCAD.2001.968704},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LyuhKL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/HongKNC00,
author = {Sungpack Hong and
Taewhan Kim and
Unni Narayanan and
Ki{-}Seok Chung},
title = {Decomposition of Bus-Invert Coding for Low-Power {I/O}},
journal = {J. Circuits Syst. Comput.},
volume = {10},
number = {1-2},
pages = {101--112},
year = {2000},
url = {https://doi.org/10.1142/S0218126600000093},
doi = {10.1142/S0218126600000093},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/HongKNC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/KimK00,
author = {Youngtae Kim and
Taewhan Kim},
title = {An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic
Optimization Using Carry-Save-Adders},
journal = {J. Circuits Syst. Comput.},
volume = {10},
number = {5-6},
pages = {279--292},
year = {2000},
url = {https://doi.org/10.1142/S0218126600000196},
doi = {10.1142/S0218126600000196},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/KimK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimU00,
author = {Taewhan Kim and
Junhyung Um},
title = {A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {19},
number = {5},
pages = {615--624},
year = {2000},
url = {https://doi.org/10.1109/43.845087},
doi = {10.1109/43.845087},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimU00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ParkKL00,
author = {Chaeryung Park and
Taewhan Kim and
C. L. Liu},
title = {An Integrated Approach to Data Path Synthesis for Behavioral-level
Power Optimization},
journal = {{VLSI} Design},
volume = {11},
number = {4},
pages = {381--396},
year = {2000},
url = {https://doi.org/10.1155/2000/76384},
doi = {10.1155/2000/76384},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ParkKL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KimU00,
author = {Taewhan Kim and
Junhyung Um},
title = {A timing-driven synthesis of arithmetic circuits using carry-save-adders
(short paper)},
booktitle = {Proceedings of {ASP-DAC} 2000, Asia and South Pacific Design Automation
Conference 2000, Yokohama, Japan},
pages = {313--316},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/368434.368656},
doi = {10.1145/368434.368656},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/KimU00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/UmKL00,
author = {Junhyung Um and
Taewhan Kim and
C. L. Liu},
editor = {Giovanni De Micheli},
title = {A fine-grained arithmetic optimization technique for high-performance/low-power
data path synthesis},
booktitle = {Proceedings of the 37th Conference on Design Automation, Los Angeles,
CA, USA, June 5-9, 2000},
pages = {98--103},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/337292.337325},
doi = {10.1145/337292.337325},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/UmKL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChungKL00,
author = {Ki{-}Seok Chung and
Taewhan Kim and
Chien{-}Liang Liu},
editor = {Majid Sarrafzadeh and
Prithviraj Banerjee and
Kaushik Roy},
title = {Behavioral-level partitioning for low power design in control-dominated
application},
booktitle = {Proceedings of the 10th {ACM} Great Lakes Symposium on {VLSI} 2000,
Chicago, Illinois, USA, March 2-4, 2000},
pages = {156--161},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/330855.331028},
doi = {10.1145/330855.331028},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ChungKL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KochKG00,
author = {Gernot Koch and
Taewhan Kim and
Reiner Genevriere},
editor = {Ellen Sentovich},
title = {A Methodology for Verifying Memory Access Protocols in Behavioral
Synthesis},
booktitle = {Proceedings of the 2000 {IEEE/ACM} International Conference on Computer-Aided
Design, 2000, San Jose, California, USA, November 5-9, 2000},
pages = {33--38},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCAD.2000.896447},
doi = {10.1109/ICCAD.2000.896447},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/KochKG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HongK00,
author = {Sungpack Hong and
Taewhan Kim},
editor = {Ellen Sentovich},
title = {Bus Optimization for Low-Power Data Path Synthesis Based on Network
Flow Method},
booktitle = {Proceedings of the 2000 {IEEE/ACM} International Conference on Computer-Aided
Design, 2000, San Jose, California, USA, November 5-9, 2000},
pages = {312--317},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCAD.2000.896491},
doi = {10.1109/ICCAD.2000.896491},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HongK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/UmKL99,
author = {Junhyung Um and
Taewhan Kim and
C. L. Liu},
editor = {Jacob K. White and
Ellen Sentovich},
title = {Optimal allocation of carry-save-adders in arithmetic optimization},
booktitle = {Proceedings of the 1999 {IEEE/ACM} International Conference on Computer-Aided
Design, 1999, San Jose, California, USA, November 7-11, 1999},
pages = {410--413},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCAD.1999.810685},
doi = {10.1109/ICCAD.1999.810685},
timestamp = {Mon, 08 May 2023 21:43:38 +0200},
biburl = {https://dblp.org/rec/conf/iccad/UmKL99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimJT98,
author = {Taewhan Kim and
William Jao and
Steven W. K. Tjiang},
title = {Circuit optimization using carry-save-adder cells},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {974--984},
year = {1998},
url = {https://doi.org/10.1109/43.728918},
doi = {10.1109/43.728918},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimJT98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/ParkKL98,
author = {Chaeryung Park and
Taewhan Kim and
C. L. Liu},
title = {Register Allocation - {A} Hierarchical Reduction Approach},
journal = {J. {VLSI} Signal Process.},
volume = {19},
number = {3},
pages = {269--285},
year = {1998},
url = {https://doi.org/10.1023/A:1008073925779},
doi = {10.1023/A:1008073925779},
timestamp = {Wed, 20 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/ParkKL98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KimJT98,
author = {Taewhan Kim and
William Jao and
Steven W. K. Tjiang},
editor = {Basant R. Chawla and
Randal E. Bryant and
Jan M. Rabaey},
title = {Arithmetic Optimization Using Carry-Save-Adders},
booktitle = {Proceedings of the 35th Conference on Design Automation, Moscone center,
San Francico, California, USA, June 15-19, 1998},
pages = {433--438},
publisher = {{ACM} Press},
year = {1998},
url = {https://doi.org/10.1145/277044.277166},
doi = {10.1145/277044.277166},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KimJT98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/KimL96,
author = {Taewhan Kim and
C. L. Liu},
title = {An integrated algorithm for incremental data path synthesis},
journal = {J. {VLSI} Signal Process.},
volume = {12},
number = {3},
pages = {265--285},
year = {1996},
url = {https://doi.org/10.1007/BF00924989},
doi = {10.1007/BF00924989},
timestamp = {Wed, 20 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/KimL96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KimL95,
author = {Taewhan Kim and
C. L. Liu},
title = {A new approach to the multiport memory allocation problem in data
path synthesis},
journal = {Integr.},
volume = {19},
number = {3},
pages = {133--160},
year = {1995},
url = {https://doi.org/10.1016/0167-9260(95)00009-5},
doi = {10.1016/0167-9260(95)00009-5},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KimL95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimYLL94,
author = {Taewhan Kim and
Noritake Yonezawa and
Jane W.{-}S. Liu and
C. L. Liu},
title = {A scheduling algorithm for conditional resource sharing-a hierarchical
reduction approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {13},
number = {4},
pages = {425--438},
year = {1994},
url = {https://doi.org/10.1109/43.275353},
doi = {10.1109/43.275353},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimYLL94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/KimCL94,
author = {Taewhan Kim and
Ki{-}Seok Chung and
Chien{-}Liang Liu},
editor = {Robert Werner},
title = {A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability},
booktitle = {{EDAC} - The European Conference on Design Automation, {ETC} - European
Test Conference, {EUROASIC} - The European Event in {ASIC} Design,
Proceedings, February 28 - March 3, 1994, Paris, France},
pages = {586--590},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/EDTC.1994.326814},
doi = {10.1109/EDTC.1994.326814},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/KimCL94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KimL93,
author = {Taewhan Kim and
C. L. Liu},
editor = {Alfred E. Dunlop},
title = {Utilization of Multiport Memories in Data Path Synthesis},
booktitle = {Proceedings of the 30th Design Automation Conference. Dallas, Texas,
USA, June 14-18, 1993},
pages = {298--302},
publisher = {{ACM} Press},
year = {1993},
url = {https://doi.org/10.1145/157485.164900},
doi = {10.1145/157485.164900},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KimL93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/ParkKL93,
author = {Chaeryung Park and
Taewhan Kim and
C. L. Liu},
title = {Register allocation for data flow graphs with conditional branches
and loops},
booktitle = {Proceedings of the European Design Automation Conference 1993, {EURO-DAC}
'93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993},
pages = {232--237},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/EURDAC.1993.410643},
doi = {10.1109/EURDAC.1993.410643},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/ParkKL93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KimLL91,
author = {Taewhan Kim and
Jane W.{-}S. Liu and
C. L. Liu},
title = {A Scheduling Algorithm for Conditional Resource Sharing},
booktitle = {1991 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of
Technical Papers},
pages = {84--87},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/ICCAD.1991.185198},
doi = {10.1109/ICCAD.1991.185198},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/KimLL91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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