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ORCIDBibTeX records: Win-San Khwa
@article{DBLP:journals/jssc/LeleCSCKWBKCCR24,
author = {Ashwin Sanjay Lele and
Muya Chang and
Samuel D. Spetalnick and
Brian Crafton and
Shota Konno and
Zishen Wan and
Ashwin Bhat and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A Heterogeneous {RRAM} In-Memory and {SRAM} Near-Memory SoC for Fused
Frame and Event-Based Target Identification and Tracking},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {1},
pages = {52--64},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2023.3297411},
doi = {10.1109/JSSC.2023.3297411},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/LeleCSCKWBKCCR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HsuWHKLJCCLLTHCCC24,
author = {Hung{-}Hsi Hsu and
Tai{-}Hao Wen and
Wei{-}Hsing Huang and
Win{-}San Khwa and
Yun{-}Chen Lo and
Chuan{-}Jia Jhang and
Yu{-}Hsiang Chin and
Yu{-}Chiao Chen and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Kea{-}Tiong Tang and
Chih{-}Cheng Hsieh and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {A Nonvolatile AI-Edge Processor With {SLC-MLC} Hybrid ReRAM Compute-in-Memory
Macro Using Current-Voltage-Hybrid Readout Scheme},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {1},
pages = {116--127},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2023.3314433},
doi = {10.1109/JSSC.2023.3314433},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/HsuWHKLJCCLLTHCCC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YouCKLHCLLHTCCC24,
author = {De{-}Qi You and
Yen{-}Cheng Chiu and
Win{-}San Khwa and
Chung{-}Yuan Li and
Fang{-}Ling Hsieh and
Yu{-}An Chien and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {An 8b-Precision 8-Mb {STT-MRAM} Near-Memory-Compute Macro Using Weight-Feature
and Input-Sparsity Aware Schemes for Energy-Efficient Edge {AI} Devices},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {1},
pages = {219--230},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2023.3324335},
doi = {10.1109/JSSC.2023.3324335},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/YouCKLHCLLHTCCC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SpetalnickLCCRYHAKCCR24,
author = {Samuel D. Spetalnick and
Ashwin Sanjay Lele and
Brian Crafton and
Muya Chang and
Sigang Ryu and
Jong{-}Hyeok Yoon and
Zhijian Hao and
Azadeh Ansari and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {30.1 {A} 40nm {VLIW} Edge Accelerator with 5MB of 0.256pJ/b {RRAM}
and a Localization Solver for Bristle Robot Surveillance},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {482--484},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454500},
doi = {10.1109/ISSCC49657.2024.10454500},
timestamp = {Tue, 19 Mar 2024 09:04:31 +0100},
biburl = {https://dblp.org/rec/conf/isscc/SpetalnickLCCRYHAKCCR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KhwaWWSCKCHCCLLHTC24,
author = {Win{-}San Khwa and
Ping{-}Chun Wu and
Jui{-}Jen Wu and
Jian{-}Wei Su and
Ho{-}Yu Chen and
Zhao{-}En Ke and
Ting{-}Chien Chiu and
Jun{-}Ming Hsu and
Chiao{-}Yen Cheng and
Yu{-}Chen Chen and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {34.2 {A} 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory
Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge
Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {568--570},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454447},
doi = {10.1109/ISSCC49657.2024.10454447},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KhwaWWSCKCHCCLLHTC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WenHKHKCWCHLLHTTCCCC24,
author = {Tai{-}Hao Wen and
Hung{-}Hsi Hsu and
Win{-}San Khwa and
Wei{-}Hsing Huang and
Zhao{-}En Ke and
Yu{-}Hsiang Chin and
Hua{-}Jin Wen and
Yu{-}Chen Chang and
Wei{-}Ting Hsu and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Shih{-}Hsih Teng and
Chung{-}Cheng Chou and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {34.8 {A} 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with
31.2TFLOPS/W for {AI} Edge Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {580--582},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454468},
doi = {10.1109/ISSCC49657.2024.10454468},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/WenHKHKCWCHLLHTTCCCC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HungWHHCSKLLHTC23,
author = {Je{-}Min Hung and
Tai{-}Hao Wen and
Yen{-}Hsiang Huang and
Sheng{-}Po Huang and
Fu{-}Chun Chang and
Chin{-}I Su and
Win{-}San Khwa and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free
Time-Domain Readout Scheme for {AI} Edge Devices},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {1},
pages = {303--315},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3200515},
doi = {10.1109/JSSC.2022.3200515},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/HungWHHCSKLLHTC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/UptonLSRKCCMRM23,
author = {Luke R. Upton and
Akash Levy and
Michael D. Scott and
Dennis Rich and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Subhasish Mitra and
Priyanka Raina and
Boris Murmann},
title = {{EMBER:} {A} 100 MHz, 0.86 mm\({}^{\mbox{2}}\), Multiple-Bits-per-Cell
{RRAM} Macro in 40 nm {CMOS} with Compact Peripherals and 1.0 pJ/bit
Read Circuitry},
booktitle = {49th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2023,
Lisbon, Portugal, September 11-14, 2023},
pages = {469--472},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ESSCIRC59616.2023.10268807},
doi = {10.1109/ESSCIRC59616.2023.10268807},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/UptonLSRKCCMRM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/JiWWKCHC23,
author = {Zexi Ji and
Hanrui Wang and
Miaorong Wang and
Win{-}San Khwa and
Meng{-}Fan Chang and
Song Han and
Anantha P. Chandrakasan},
title = {A Fully-Integrated Energy-Scalable Transformer Accelerator Supporting
Adaptive Model Configuration and Word Elimination for Language Understanding
on Edge Devices},
booktitle = {{IEEE/ACM} International Symposium on Low Power Electronics and Design,
{ISLPED} 2023, Vienna, Austria, August 7-8, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISLPED58423.2023.10244459},
doi = {10.1109/ISLPED58423.2023.10244459},
timestamp = {Fri, 09 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/JiWWKCHC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HuangWHKLJHCCLLTHCCC23,
author = {Wei{-}Hsing Huang and
Tai{-}Hao Wen and
Je{-}Min Hung and
Win{-}San Khwa and
Yun{-}Chen Lo and
Chuan{-}Jia Jhang and
Hung{-}Hsi Hsu and
Yu{-}Hsiang Chin and
Yu{-}Chiao Chen and
Chuna{-}Chuan Lo and
Ren{-}Shuo Liu and
Kea{-}Tiong Tang and
Chih{-}Cheng Hsieh and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {A Nonvolatile Al-Edge Processor with 4MB {SLC-MLC} Hybrid-Mode ReRAM
Compute-in-Memory Macro and 51.4-251TOPS/W},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {258--259},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067610},
doi = {10.1109/ISSCC42615.2023.10067610},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/HuangWHKLJHCCLLTHCCC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangLSCKWBKCCR23,
author = {Muya Chang and
Ashwin Sanjay Lele and
Samuel D. Spetalnick and
Brian Crafton and
Shota Konno and
Zishen Wan and
Ashwin Bhat and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 73.53TOPS/W 14.74TOPS Heterogeneous {RRAM} In-Memory and {SRAM}
Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {426--427},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067544},
doi = {10.1109/ISSCC42615.2023.10067544},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangLSCKWBKCCR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChiuKLHCLCPYCLLLHTCCC23,
author = {Yen{-}Cheng Chiu and
Win{-}San Khwa and
Chung{-}Yuan Li and
Fang{-}Ling Hsieh and
Yu{-}An Chien and
Guan{-}Yi Lin and
Po{-}Jung Chen and
Tsen{-}Hsiang Pan and
De{-}Qi You and
Fang{-}Yi Chen and
Andrew Lee and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {A 22nm 8Mb {STT-MRAM} Near-Memory-Computing Macro with 8b-Precision
and 46.4-160.1TOPS/W for Edge-AI Devices},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {496--497},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067563},
doi = {10.1109/ISSCC42615.2023.10067563},
timestamp = {Wed, 29 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChiuKLHCLCPYCLLLHTCCC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/SpetalnickCKCLK23,
author = {Samuel D. Spetalnick and
Muya Chang and
Shota Konno and
Brian Crafton and
Ashwin Sanjay Lele and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 2.38 MCells/mm\({}^{\mbox{2}}\) 9.81 -350 {TOPS/W} {RRAM} Compute-in-Memory
Macro in 40nm {CMOS} with Hybrid Offset/IOFF Cancellation and {ICELL}
{RBLSL} Drop Mitigation},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185424},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185424},
timestamp = {Fri, 28 Jul 2023 10:40:41 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/SpetalnickCKCLK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/WenHHWCLCSKWLLH23,
author = {Tai{-}Hao Wen and
Je{-}Min Hung and
Hung{-}Hsi Hsu and
Yuan Wu and
Fu{-}Chun Chang and
Chung{-}Yuan Li and
Chih{-}Han Chien and
Chin{-}I Su and
Win{-}San Khwa and
Jui{-}Jen Wu and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Mon{-}Shu Ho and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {A 28nm Nonvolatile {AI} Edge Processor using 4Mb Analog-Based Near-Memory-Compute
ReRAM with 27.2 {TOPS/W} for Tiny {AI} Edge Devices},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185326},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185326},
timestamp = {Tue, 20 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsit/WenHHWCLCSKWLLH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YoonCKCCR22,
author = {Jong{-}Hyeok Yoon and
Muya Chang and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 40-nm, 64-Kb, 56.67 {TOPS/W} Voltage-Sensing Computing-In-Memory/Digital
{RRAM} Macro Supporting Iterative Write With Verification and Online
Read-Disturb Detection},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {1},
pages = {68--79},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2021.3101209},
doi = {10.1109/JSSC.2021.3101209},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/YoonCKCCR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YoonCKCCR22a,
author = {Jong{-}Hyeok Yoon and
Muya Chang and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory {RRAM} Macro
With Write Verification and Multi-Bit Encoding},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {3},
pages = {845--857},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2022.3141370},
doi = {10.1109/JSSC.2022.3141370},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/YoonCKCCR22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/PrabhuGKRGKDKLL22,
author = {Kartik Prabhu and
Albert Gural and
Zainab F. Khan and
Robert M. Radway and
Massimo Giordano and
Kalhan Koul and
Rohan Doshi and
John W. Kustin and
Timothy Liu and
Gregorio B. Lopes and
Victor Turbiner and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Gu{\'{e}}nol{\'{e}} Lallement and
Boris Murmann and
Subhasish Mitra and
Priyanka Raina},
title = {{CHIMERA:} {A} 0.92-TOPS, 2.2-TOPS/W Edge {AI} Accelerator With 2-MByte
On-Chip Foundry Resistive {RAM} for Efficient Training and Inference},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {4},
pages = {1013--1026},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2022.3140753},
doi = {10.1109/JSSC.2022.3140753},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/PrabhuGKRGKDKLL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/neuromorphic/ZhengZLKROW22,
author = {Xin Zheng and
Ryan Zarcone and
Akash Levy and
Win{-}San Khwa and
Priyanka Raina and
Bruno A. Olshausen and
H.{-}S. Philip Wong},
title = {High-density analog image storage in an analog-valued non-volatile
memory array},
journal = {Neuromorph. Comput. Eng.},
volume = {2},
number = {4},
pages = {44018},
year = {2022},
url = {https://doi.org/10.1088/2634-4386/aca92c},
doi = {10.1088/2634-4386/ACA92C},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/neuromorphic/ZhengZLKROW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangSCKCCR22,
author = {Muya Chang and
Samuel D. Spetalnick and
Brian Crafton and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB
{RRAM/SRAM} System with Embedded Cortex {M3} Microprocessor for Edge
Recommendation Systems},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731679},
doi = {10.1109/ISSCC42614.2022.9731679},
timestamp = {Mon, 21 Mar 2022 13:32:47 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ChangSCKCCR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HungHHCWSKLLHTC22,
author = {Je{-}Min Hung and
Yen{-}Hsiang Huang and
Sheng{-}Po Huang and
Fu{-}Chun Chang and
Tai{-}Hao Wen and
Chin{-}I Su and
Win{-}San Khwa and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory
Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI
Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731715},
doi = {10.1109/ISSCC42614.2022.9731715},
timestamp = {Mon, 21 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/HungHHCWSKLLHTC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KhwaCJHLWCYLC22,
author = {Win{-}San Khwa and
Yen{-}Cheng Chiu and
Chuan{-}Jia Jhang and
Sheng{-}Po Huang and
Chun{-}Ying Lee and
Tai{-}Hao Wen and
Fu{-}Chun Chang and
Shao{-}Ming Yu and
Tung{-}Yin Lee and
Meng{-}Fan Chang},
title = {A 40-nm, 2M-Cell, 8b-Precision, Hybrid {SLC-MLC} {PCM} Computing-in-Memory
Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731670},
doi = {10.1109/ISSCC42614.2022.9731670},
timestamp = {Mon, 21 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KhwaCJHLWCYLC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SpetalnickCCKCC22,
author = {Samuel D. Spetalnick and
Muya Chang and
Brian Crafton and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 40nm 64kb 26.56TOPS/W 2.37Mb/mm\({}^{\mbox{2}}\)RRAM Binary/Compute-in-Memory
Macro with 4.23x Improvement in Density and {\textgreater}75{\%} Use
of Sensing Dynamic Range},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731725},
doi = {10.1109/ISSCC42614.2022.9731725},
timestamp = {Mon, 21 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/SpetalnickCCKCC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChiuYTHCWCHLLCP22,
author = {Yen{-}Cheng Chiu and
Chia{-}Sheng Yang and
Shih{-}Hsih Teng and
Hsiao{-}Yu Huang and
Fu{-}Chun Chang and
Yuan Wu and
Yu{-}An Chien and
Fang{-}Ling Hsieh and
Chung{-}Yuan Li and
Guan{-}Yi Lin and
Po{-}Jung Chen and
Tsen{-}Hsiang Pan and
Chung{-}Chuan Lo and
Win{-}San Khwa and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Chieh{-}Pu Lo and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {A 22nm 4Mb {STT-MRAM} Data-Encrypted Near-Memory Computation Macro
with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b
{MAC} for {AI} Operations},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {178--180},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731621},
doi = {10.1109/ISSCC42614.2022.9731621},
timestamp = {Tue, 20 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ChiuYTHCWCHLLCP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SinangilENASKLW21,
author = {Mahmut E. Sinangil and
Burak Erbagci and
Rawan Naous and
Kerem Akarvardar and
Dar Sun and
Win{-}San Khwa and
Hung{-}Jen Liao and
Yih Wang and
Jonathan Chang},
title = {A 7-nm Compute-in-Memory {SRAM} Macro Supporting Multi-Bit Input,
Weight and Output and Achieving 351 {TOPS/W} and 372.4 {GOPS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {1},
pages = {188--198},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2020.3031290},
doi = {10.1109/JSSC.2020.3031290},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SinangilENASKLW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/YoonCKCCR21,
author = {Jong{-}Hyeok Yoon and
Muya Chang and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory {RRAM} Macro
with Voltage-sensing Read and Write Verification for reliable multi-bit
{RRAM} operation},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2021, Austin,
TX, USA, April 25-30, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/CICC51472.2021.9431412},
doi = {10.1109/CICC51472.2021.9431412},
timestamp = {Thu, 20 May 2021 14:06:55 +0200},
biburl = {https://dblp.org/rec/conf/cicc/YoonCKCCR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/XueHKHHCCLJSKLL21,
author = {Cheng{-}Xin Xue and
Je{-}Min Hung and
Hui{-}Yao Kao and
Yen{-}Hsiang Huang and
Sheng{-}Po Huang and
Fu{-}Chun Chang and
Peng Chen and
Ta{-}Wei Liu and
Chuan{-}Jia Jhang and
Chin{-}I Su and
Win{-}San Khwa and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
Meng{-}Fan Chang},
title = {A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91
to 195.7TOPS/W for Tiny {AI} Edge Devices},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {245--247},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365769},
doi = {10.1109/ISSCC42613.2021.9365769},
timestamp = {Wed, 10 Mar 2021 15:02:58 +0100},
biburl = {https://dblp.org/rec/conf/isscc/XueHKHHCCLJSKLL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/YoonCKCCR21,
author = {Jong{-}Hyeok Yoon and
Muya Chang and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Arijit Raychowdhury},
title = {29.1 {A} 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital
{RRAM} Macro with Active-Feedback-Based Read and In-Situ Write Verification},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {404--406},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365926},
doi = {10.1109/ISSCC42613.2021.9365926},
timestamp = {Wed, 10 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/YoonCKCCR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GiordanoPKRGDKK21,
author = {Massimo Giordano and
Kartik Prabhu and
Kalhan Koul and
Robert M. Radway and
Albert Gural and
Rohan Doshi and
Zainab F. Khan and
John W. Kustin and
Timothy Liu and
Gregorio B. Lopes and
Victor Turbiner and
Win{-}San Khwa and
Yu{-}Der Chih and
Meng{-}Fan Chang and
Gu{\'{e}}nol{\'{e}} Lallement and
Boris Murmann and
Subhasish Mitra and
Priyanka Raina},
title = {{CHIMERA:} {A} 0.92 TOPS, 2.2 {TOPS/W} Edge {AI} Accelerator with
2 MByte On-Chip Foundry Resistive {RAM} for Efficient Training and
Inference},
booktitle = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492347},
doi = {10.23919/VLSICIRCUITS52068.2021.9492347},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GiordanoPKRGDKK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/0001SESKLWC20,
author = {Qing Dong and
Mahmut E. Sinangil and
Burak Erbagci and
Dar Sun and
Win{-}San Khwa and
Hung{-}Jen Liao and
Yih Wang and
Jonathan Chang},
title = {15.3 {A} 351TOPS/W and 372.4GOPS Compute-in-Memory {SRAM} Macro in
7nm FinFET {CMOS} for Machine-Learning Applications},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {242--244},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062985},
doi = {10.1109/ISSCC19947.2020.9062985},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/0001SESKLWC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/SiKCLSLYYLC19,
author = {Xin Si and
Win{-}San Khwa and
Jia{-}Jing Chen and
Jia{-}Fang Li and
Xiaoyu Sun and
Rui Liu and
Shimeng Yu and
Hiroyuki Yamauchi and
Qiang Li and
Meng{-}Fan Chang},
title = {A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully
Parallel Product-Sum Operation for Binarized {DNN} Edge Processors},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {66-I},
number = {11},
pages = {4172--4185},
year = {2019},
url = {https://doi.org/10.1109/TCSI.2019.2928043},
doi = {10.1109/TCSI.2019.2928043},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/SiKCLSLYYLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GuoLZWOKCCLLCWY19,
author = {Ruiqi Guo and
Yonggang Liu and
Shixuan Zheng and
Ssu{-}Yen Wu and
Peng Ouyang and
Win{-}San Khwa and
Xi Chen and
Jia{-}Jing Chen and
Xiudong Li and
Leibo Liu and
Meng{-}Fan Chang and
Shaojun Wei and
Shouyi Yin},
title = {A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor
using 16 Computing-in-Memory {SRAM} Macros in 65nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {120},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778028},
doi = {10.23919/VLSIC.2019.8778028},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GuoLZWOKCCLLCWY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuPSKSCLCY18,
author = {Rui Liu and
Xiaochen Peng and
Xiaoyu Sun and
Win{-}San Khwa and
Xin Si and
Jia{-}Jing Chen and
Jia{-}Fang Li and
Meng{-}Fan Chang and
Shimeng Yu},
title = {Parallelizing {SRAM} arrays with customized bit-cell for binary neural
networks},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {21:1--21:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3196089},
doi = {10.1145/3195970.3196089},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/LiuPSKSCLCY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KhwaCLSYSLCLYC18,
author = {Win{-}San Khwa and
Jia{-}Jing Chen and
Jia{-}Fang Li and
Xin Si and
En{-}Yu Yang and
Xiaoyu Sun and
Rui Liu and
Pai{-}Yu Chen and
Qiang Li and
Shimeng Yu and
Meng{-}Fan Chang},
title = {A 65nm 4Kb algorithm-dependent computing-in-memory {SRAM} unit-macro
with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for
binary {DNN} edge processors},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {496--498},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310401},
doi = {10.1109/ISSCC.2018.8310401},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KhwaCLSYSLCLYC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KhwaCWLSYCWLBKL17,
author = {Win{-}San Khwa and
Meng{-}Fan Chang and
Jau{-}Yi Wu and
Ming{-}Hsiu Lee and
Tzu{-}Hsiang Su and
Keng{-}Hao Yang and
Tien{-}Fu Chen and
Tien{-}Yen Wang and
Hsiang{-}Pang Li and
Matthew J. BrightSky and
SangBum Kim and
Hsiang{-}Lam Lung and
Chung Lam},
title = {A Resistance Drift Compensation Scheme to Reduce {MLC} {PCM} Raw {BER}
by Over 100{\texttimes} for Storage Class Memory Applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {1},
pages = {218--228},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2016.2597822},
doi = {10.1109/JSSC.2016.2597822},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KhwaCWLSYCWLBKL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChenKLLLL0WYC17,
author = {Wei{-}Hao Chen and
Win{-}San Khwa and
Jun{-}Yi Li and
Wei{-}Yu Lin and
Huan{-}Ting Lin and
Yongpan Liu and
Yu Wang and
Huaqiang Wu and
Huazhong Yang and
Meng{-}Fan Chang},
title = {Circuit design for beyond von Neumann applications using emerging
memory: From nonvolatile logics to neuromorphic computing},
booktitle = {18th International Symposium on Quality Electronic Design, {ISQED}
2017, Santa Clara, CA, USA, March 14-15, 2017},
pages = {23--28},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISQED.2017.7918287},
doi = {10.1109/ISQED.2017.7918287},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/ChenKLLLL0WYC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KhwaCWLSYCWLBKL16,
author = {Win{-}San Khwa and
Meng{-}Fan Chang and
Jau{-}Yi Wu and
Ming{-}Hsiu Lee and
Tzu{-}Hsiang Su and
Keng{-}Hao Yang and
Tien{-}Fu Chen and
Tien{-}Yen Wang and
Hsiang{-}Pang Li and
Matthew BrightSky and
SangBum Kim and
Hsiang{-}Lam Lung and
Chung Lam},
title = {7.3 {A} resistance-drift compensation scheme to reduce {MLC} {PCM}
raw {BER} by over 100{\texttimes} for storage-class memory applications},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {134--135},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7417943},
doi = {10.1109/ISSCC.2016.7417943},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KhwaCWLSYCWLBKL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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