BibTeX records: Aamer Jaleel

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@article{DBLP:journals/taco/JaleelED19,
  author    = {Aamer Jaleel and
               Eiman Ebrahimi and
               Sam Duncan},
  title     = {{DUCATI:} High-performance Address Translation by Extending {TLB}
               Reach of GPU-accelerated Systems},
  journal   = {{TACO}},
  volume    = {16},
  number    = {1},
  pages     = {6:1--6:24},
  year      = {2019},
  url       = {https://dl.acm.org/citation.cfm?id=3309710},
  timestamp = {Thu, 28 Mar 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/taco/JaleelED19},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/YoungCJQ18,
  author    = {Vinson Young and
               Chia{-}Chen Chou and
               Aamer Jaleel and
               Moinuddin K. Qureshi},
  title     = {{ACCORD:} Enabling Associativity for Gigascale {DRAM} Caches by Coordinating
               Way-Install and Way-Prediction},
  booktitle = {45th {ACM/IEEE} Annual International Symposium on Computer Architecture,
               {ISCA} 2018, Los Angeles, CA, USA, June 1-6, 2018},
  pages     = {328--339},
  year      = {2018},
  crossref  = {DBLP:conf/isca/2018},
  url       = {https://doi.org/10.1109/ISCA.2018.00036},
  doi       = {10.1109/ISCA.2018.00036},
  timestamp = {Tue, 11 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isca/YoungCJQ18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/YoungJBENV18,
  author    = {Vinson Young and
               Aamer Jaleel and
               Evgeny Bolotin and
               Eiman Ebrahimi and
               David W. Nellans and
               Oreste Villa},
  title     = {Combining {HW/SW} Mechanisms to Improve {NUMA} Performance of Multi-GPU
               Systems},
  booktitle = {51st Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2018, Fukuoka, Japan, October 20-24, 2018},
  pages     = {339--351},
  year      = {2018},
  crossref  = {DBLP:conf/micro/2018},
  url       = {https://doi.org/10.1109/MICRO.2018.00035},
  doi       = {10.1109/MICRO.2018.00035},
  timestamp = {Wed, 13 Feb 2019 11:42:26 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/micro/YoungJBENV18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cal/AdilehEJE17,
  author    = {Almutaz Adileh and
               Stijn Eyerman and
               Aamer Jaleel and
               Lieven Eeckhout},
  title     = {Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous
               Multicores},
  journal   = {Computer Architecture Letters},
  volume    = {16},
  number    = {1},
  pages     = {56--59},
  year      = {2017},
  url       = {https://doi.org/10.1109/LCA.2016.2616339},
  doi       = {10.1109/LCA.2016.2616339},
  timestamp = {Thu, 29 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/cal/AdilehEJE17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/JaleelQ17,
  author    = {Aamer Jaleel and
               Moinuddin K. Qureshi},
  title     = {Top Picks from the 2016 Computer Architecture Conferences},
  journal   = {{IEEE} Micro},
  volume    = {37},
  number    = {3},
  pages     = {6--11},
  year      = {2017},
  url       = {https://doi.org/10.1109/MM.2017.66},
  doi       = {10.1109/MM.2017.66},
  timestamp = {Thu, 29 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/micro/JaleelQ17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cf/OtoomJT17,
  author    = {Mwaffaq Otoom and
               Aamer Jaleel and
               Pedro Trancoso},
  title     = {Using Personality Metrics to Improve Cache Interference Management
               in Multicore Processors},
  booktitle = {Proceedings of the Computing Frontiers Conference, CF'17, Siena, Italy,
               May 15-17, 2017},
  pages     = {251--254},
  year      = {2017},
  crossref  = {DBLP:conf/cf/2017},
  url       = {https://doi.org/10.1145/3075564.3075591},
  doi       = {10.1145/3075564.3075591},
  timestamp = {Tue, 06 Nov 2018 11:07:32 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/cf/OtoomJT17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KayaalpKEEAPJ17,
  author    = {Mehmet Kayaalp and
               Khaled N. Khasawneh and
               Hodjat Asghari Esfeden and
               Jesse Elwell and
               Nael B. Abu{-}Ghazaleh and
               Dmitry V. Ponomarev and
               Aamer Jaleel},
  title     = {{RIC:} Relaxed Inclusion Caches for Mitigating {LLC} Side-Channel
               Attacks},
  booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
               2017, Austin, TX, USA, June 18-22, 2017},
  pages     = {7:1--7:6},
  year      = {2017},
  crossref  = {DBLP:conf/dac/2017},
  url       = {https://doi.org/10.1145/3061639.3062313},
  doi       = {10.1145/3061639.3062313},
  timestamp = {Tue, 06 Nov 2018 16:58:15 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/dac/KayaalpKEEAPJ17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/ArunkumarBCMEVJ17,
  author    = {Akhil Arunkumar and
               Evgeny Bolotin and
               Benjamin Cho and
               Ugljesa Milic and
               Eiman Ebrahimi and
               Oreste Villa and
               Aamer Jaleel and
               Carole{-}Jean Wu and
               David W. Nellans},
  title     = {{MCM-GPU:} Multi-Chip-Module GPUs for Continued Performance Scalability},
  booktitle = {Proceedings of the 44th Annual International Symposium on Computer
               Architecture, {ISCA} 2017, Toronto, ON, Canada, June 24-28, 2017},
  pages     = {320--332},
  year      = {2017},
  crossref  = {DBLP:conf/isca/2017},
  url       = {https://doi.org/10.1145/3079856.3080231},
  doi       = {10.1145/3079856.3080231},
  timestamp = {Tue, 06 Nov 2018 11:07:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isca/ArunkumarBCMEVJ17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memsys/ChouJQ17,
  author    = {Chia{-}Chen Chou and
               Aamer Jaleel and
               Moinuddin K. Qureshi},
  title     = {{BATMAN:} techniques for maximizing system bandwidth of memory systems
               with stacked-DRAM},
  booktitle = {Proceedings of the International Symposium on Memory Systems, {MEMSYS}
               2017, Alexandria, VA, USA, October 02 - 05, 2017},
  pages     = {268--280},
  year      = {2017},
  crossref  = {DBLP:conf/memsys/2017},
  url       = {https://doi.org/10.1145/3132402.3132404},
  doi       = {10.1145/3132402.3132404},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/memsys/ChouJQ17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/MilicVBAEJRN17,
  author    = {Ugljesa Milic and
               Oreste Villa and
               Evgeny Bolotin and
               Akhil Arunkumar and
               Eiman Ebrahimi and
               Aamer Jaleel and
               Alex Ram{\'{\i}}rez and
               David W. Nellans},
  title     = {Beyond the socket: NUMA-aware GPUs},
  booktitle = {Proceedings of the 50th Annual {IEEE/ACM} International Symposium
               on Microarchitecture, {MICRO} 2017, Cambridge, MA, USA, October 14-18,
               2017},
  pages     = {123--135},
  year      = {2017},
  crossref  = {DBLP:conf/micro/2017},
  url       = {https://doi.org/10.1145/3123939.3124534},
  doi       = {10.1145/3123939.3124534},
  timestamp = {Tue, 06 Nov 2018 16:58:26 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/micro/MilicVBAEJRN17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/AdilehEJE16,
  author    = {Almutaz Adileh and
               Stijn Eyerman and
               Aamer Jaleel and
               Lieven Eeckhout},
  title     = {Maximizing Heterogeneous Processor Performance Under Power Constraints},
  journal   = {{TACO}},
  volume    = {13},
  number    = {3},
  pages     = {29:1--29:23},
  year      = {2016},
  url       = {https://doi.org/10.1145/2976739},
  doi       = {10.1145/2976739},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/taco/AdilehEJE16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KayaalpAPJ16,
  author    = {Mehmet Kayaalp and
               Nael B. Abu{-}Ghazaleh and
               Dmitry V. Ponomarev and
               Aamer Jaleel},
  title     = {A high-resolution side-channel attack on last-level cache},
  booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
               2016, Austin, TX, USA, June 5-9, 2016},
  pages     = {72:1--72:6},
  year      = {2016},
  crossref  = {DBLP:conf/dac/2016},
  url       = {https://doi.org/10.1145/2897937.2897962},
  doi       = {10.1145/2897937.2897962},
  timestamp = {Tue, 06 Nov 2018 16:58:19 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/dac/KayaalpAPJ16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/ChengZSIJL016,
  author    = {Hsiang{-}Yun Cheng and
               Jishen Zhao and
               Jack Sampson and
               Mary Jane Irwin and
               Aamer Jaleel and
               Yu Lu and
               Yuan Xie},
  title     = {{LAP:} Loop-Block Aware Inclusion Properties for Energy-Efficient
               Asymmetric Last Level Caches},
  booktitle = {43rd {ACM/IEEE} Annual International Symposium on Computer Architecture,
               {ISCA} 2016, Seoul, South Korea, June 18-22, 2016},
  pages     = {103--114},
  year      = {2016},
  crossref  = {DBLP:conf/isca/2016},
  url       = {https://doi.org/10.1109/ISCA.2016.19},
  doi       = {10.1109/ISCA.2016.19},
  timestamp = {Tue, 23 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isca/ChengZSIJL016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memsys/GhasempourJGL16,
  author    = {Mohsen Ghasempour and
               Aamer Jaleel and
               Jim D. Garside and
               Mikel Luj{\'{a}}n},
  title     = {{HAPPY:} Hybrid Address-based Page Policy in DRAMs},
  booktitle = {Proceedings of the Second International Symposium on Memory Systems,
               {MEMSYS} 2016, Alexandria, VA, USA, October 3-6, 2016},
  pages     = {311--321},
  year      = {2016},
  crossref  = {DBLP:conf/memsys/2016},
  url       = {https://doi.org/10.1145/2989081.2989101},
  doi       = {10.1145/2989081.2989101},
  timestamp = {Tue, 06 Nov 2018 11:07:11 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/memsys/GhasempourJGL16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memsys/GhasempourJGL16a,
  author    = {Mohsen Ghasempour and
               Aamer Jaleel and
               Jim D. Garside and
               Mikel Luj{\'{a}}n},
  title     = {DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance
               of DRAMs},
  booktitle = {Proceedings of the Second International Symposium on Memory Systems,
               {MEMSYS} 2016, Alexandria, VA, USA, October 3-6, 2016},
  pages     = {362--373},
  year      = {2016},
  crossref  = {DBLP:conf/memsys/2016},
  url       = {https://doi.org/10.1145/2989081.2989102},
  doi       = {10.1145/2989081.2989102},
  timestamp = {Tue, 06 Nov 2018 11:07:11 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/memsys/GhasempourJGL16a},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/ChouJQ16,
  author    = {Chia{-}Chen Chou and
               Aamer Jaleel and
               Moinuddin K. Qureshi},
  title     = {{CANDY:} Enabling coherent {DRAM} caches for multi-node systems},
  booktitle = {49th Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2016, Taipei, Taiwan, October 15-19, 2016},
  pages     = {35:1--35:13},
  year      = {2016},
  crossref  = {DBLP:conf/micro/2016},
  url       = {https://doi.org/10.1109/MICRO.2016.7783738},
  doi       = {10.1109/MICRO.2016.7783738},
  timestamp = {Sat, 10 Mar 2018 14:44:10 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/micro/ChouJQ16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/MiguelAJJ16,
  author    = {Joshua San Miguel and
               Jorge Albericio and
               Natalie D. Enright Jerger and
               Aamer Jaleel},
  title     = {The Bunker Cache for spatio-value approximation},
  booktitle = {49th Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2016, Taipei, Taiwan, October 15-19, 2016},
  pages     = {43:1--43:12},
  year      = {2016},
  crossref  = {DBLP:conf/micro/2016},
  url       = {https://doi.org/10.1109/MICRO.2016.7783746},
  doi       = {10.1109/MICRO.2016.7783746},
  timestamp = {Sat, 10 Mar 2018 14:44:10 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/micro/MiguelAJJ16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OzdalJNBS15,
  author    = {Muhammet Mustafa Ozdal and
               Aamer Jaleel and
               Paolo Narv{\'{a}}ez and
               Steven M. Burns and
               Ganapati Srinivasa},
  title     = {Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures},
  journal   = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
  volume    = {34},
  number    = {3},
  pages     = {381--394},
  year      = {2015},
  url       = {https://doi.org/10.1109/TCAD.2014.2387856},
  doi       = {10.1109/TCAD.2014.2387856},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tcad/OzdalJNBS15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tocs/PellauerPAAACFG15,
  author    = {Michael Pellauer and
               Angshuman Parashar and
               Michael Adler and
               Bushra Ahsan and
               Randy L. Allmon and
               Neal Clayton Crago and
               Kermin Fleming and
               Mohit Gambhir and
               Aamer Jaleel and
               Tushar Krishna and
               Daniel Lustig and
               Stephen Maresh and
               Vladimir Pavlov and
               Rachid Rayess and
               Antonia Zhai and
               Joel S. Emer},
  title     = {Efficient Control and Communication Paradigms for Coarse-Grained Spatial
               Architectures},
  journal   = {{ACM} Trans. Comput. Syst.},
  volume    = {33},
  number    = {3},
  pages     = {10:1--10:32},
  year      = {2015},
  url       = {https://doi.org/10.1145/2754930},
  doi       = {10.1145/2754930},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/tocs/PellauerPAAACFG15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/JaleelNMSE15,
  author    = {Aamer Jaleel and
               Joseph Nuzman and
               Adrian Moga and
               Simon C. Steely Jr. and
               Joel S. Emer},
  title     = {High performing cache hierarchies for server workloads: Relaxing inclusion
               to capture the latency benefits of exclusive caches},
  booktitle = {21st {IEEE} International Symposium on High Performance Computer Architecture,
               {HPCA} 2015, Burlingame, CA, USA, February 7-11, 2015},
  pages     = {343--353},
  year      = {2015},
  crossref  = {DBLP:conf/hpca/2015},
  url       = {https://doi.org/10.1109/HPCA.2015.7056045},
  doi       = {10.1109/HPCA.2015.7056045},
  timestamp = {Fri, 19 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/JaleelNMSE15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/ChouJQ15,
  author    = {Chia{-}Chen Chou and
               Aamer Jaleel and
               Moinuddin K. Qureshi},
  title     = {{BEAR:} techniques for mitigating bandwidth bloat in gigascale {DRAM}
               caches},
  booktitle = {Proceedings of the 42nd Annual International Symposium on Computer
               Architecture, Portland, OR, USA, June 13-17, 2015},
  pages     = {198--210},
  year      = {2015},
  crossref  = {DBLP:conf/isca/2015},
  url       = {https://doi.org/10.1145/2749469.2750387},
  doi       = {10.1145/2749469.2750387},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isca/ChouJQ15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/GhasempourGJL15,
  author    = {Mohsen Ghasempour and
               Jim D. Garside and
               Aamer Jaleel and
               Mikel Luj{\'{a}}n},
  title     = {DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance
               of DRAMs},
  journal   = {CoRR},
  volume    = {abs/1509.03721},
  year      = {2015},
  url       = {http://arxiv.org/abs/1509.03721},
  archivePrefix = {arXiv},
  eprint    = {1509.03721},
  timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/corr/GhasempourGJL15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/GhasempourJGL15,
  author    = {Mohsen Ghasempour and
               Aamer Jaleel and
               Jim D. Garside and
               Mikel Luj{\'{a}}n},
  title     = {{HAPPY:} Hybrid Address-based Page Policy in DRAMs},
  journal   = {CoRR},
  volume    = {abs/1509.03740},
  year      = {2015},
  url       = {http://arxiv.org/abs/1509.03740},
  archivePrefix = {arXiv},
  eprint    = {1509.03740},
  timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/corr/GhasempourJGL15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/ParasharPAACLPZGJARME14,
  author    = {Angshuman Parashar and
               Michael Pellauer and
               Michael Adler and
               Bushra Ahsan and
               Neal Clayton Crago and
               Daniel Lustig and
               Vladimir Pavlov and
               Antonia Zhai and
               Mohit Gambhir and
               Aamer Jaleel and
               Randy L. Allmon and
               Rachid Rayess and
               Stephen Maresh and
               Joel S. Emer},
  title     = {Efficient Spatial Processing Element Control via Triggered Instructions},
  journal   = {{IEEE} Micro},
  volume    = {34},
  number    = {3},
  pages     = {120--137},
  year      = {2014},
  url       = {https://doi.org/10.1109/MM.2014.14},
  doi       = {10.1109/MM.2014.14},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/micro/ParasharPAACLPZGJARME14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/PugsleyCWCSJLCB14,
  author    = {Seth H. Pugsley and
               Zeshan Chishti and
               Chris Wilkerson and
               Peng{-}fei Chuang and
               Robert L. Scott and
               Aamer Jaleel and
               Shih{-}Lien Lu and
               Kingsum Chow and
               Rajeev Balasubramonian},
  title     = {Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers},
  booktitle = {20th {IEEE} International Symposium on High Performance Computer Architecture,
               {HPCA} 2014, Orlando, FL, USA, February 15-19, 2014},
  pages     = {626--637},
  year      = {2014},
  crossref  = {DBLP:conf/hpca/2014},
  url       = {https://doi.org/10.1109/HPCA.2014.6835971},
  doi       = {10.1109/HPCA.2014.6835971},
  timestamp = {Thu, 07 Feb 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/PugsleyCWCSJLCB14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/HeirmanCCHJE14,
  author    = {Wim Heirman and
               Trevor E. Carlson and
               Kenzo Van Craeynest and
               Ibrahim Hur and
               Aamer Jaleel and
               Lieven Eeckhout},
  title     = {Undersubscribed threading on clustered cache architectures},
  booktitle = {20th {IEEE} International Symposium on High Performance Computer Architecture,
               {HPCA} 2014, Orlando, FL, USA, February 15-19, 2014},
  pages     = {678--689},
  year      = {2014},
  crossref  = {DBLP:conf/hpca/2014},
  url       = {https://doi.org/10.1109/HPCA.2014.6835975},
  doi       = {10.1109/HPCA.2014.6835975},
  timestamp = {Thu, 07 Feb 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/HeirmanCCHJE14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ics/HeirmanCCHJE14,
  author    = {Wim Heirman and
               Trevor E. Carlson and
               Kenzo Van Craeynest and
               Ibrahim Hur and
               Aamer Jaleel and
               Lieven Eeckhout},
  title     = {Automatic {SMT} threading for OpenMP applications on the Intel Xeon
               Phi co-processor},
  booktitle = {Proceedings of the 4th International Workshop on Runtime and Operating
               Systems for Supercomputers, {ROSS} 2014, Munich, Germany, June 10,
               2014},
  pages     = {7:1--7:7},
  year      = {2014},
  crossref  = {DBLP:conf/ics/2014ross},
  url       = {https://doi.org/10.1145/2612262.2612268},
  doi       = {10.1145/2612262.2612268},
  timestamp = {Tue, 06 Nov 2018 11:07:02 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/ics/HeirmanCCHJE14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/ChouJQ14,
  author    = {Chia{-}Chen Chou and
               Aamer Jaleel and
               Moinuddin K. Qureshi},
  title     = {{CAMEO:} {A} Two-Level Memory Organization with Capacity of Main Memory
               and Flexibility of Hardware-Managed Cache},
  booktitle = {47th Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2014, Cambridge, United Kingdom, December 13-17, 2014},
  pages     = {1--12},
  year      = {2014},
  crossref  = {DBLP:conf/micro/2014},
  url       = {https://doi.org/10.1109/MICRO.2014.63},
  doi       = {10.1109/MICRO.2014.63},
  timestamp = {Sun, 21 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/micro/ChouJQ14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/SubramaniamSHJBFE13,
  author    = {Samantika Subramaniam and
               Simon C. Steely Jr. and
               William Hasenplaugh and
               Aamer Jaleel and
               Carl J. Beckmann and
               Tryggve Fossum and
               Joel S. Emer},
  title     = {Using in-flight chains to build a scalable cache coherence protocol},
  journal   = {{TACO}},
  volume    = {10},
  number    = {4},
  pages     = {28:1--28:24},
  year      = {2013},
  url       = {https://doi.org/10.1145/2541228.2541235},
  doi       = {10.1145/2541228.2541235},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/taco/SubramaniamSHJBFE13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/CraeynestAHJE13,
  author    = {Kenzo Van Craeynest and
               Shoaib Akram and
               Wim Heirman and
               Aamer Jaleel and
               Lieven Eeckhout},
  title     = {Fairness-aware scheduling on single-ISA heterogeneous multi-cores},
  booktitle = {Proceedings of the 22nd International Conference on Parallel Architectures
               and Compilation Techniques, Edinburgh, United Kingdom, September 7-11,
               2013},
  pages     = {177--187},
  year      = {2013},
  crossref  = {DBLP:conf/IEEEpact/2013},
  url       = {https://doi.org/10.1109/PACT.2013.6618815},
  doi       = {10.1109/PACT.2013.6618815},
  timestamp = {Mon, 22 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/IEEEpact/CraeynestAHJE13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/OzdalJNBS13,
  author    = {Muhammet Mustafa Ozdal and
               Aamer Jaleel and
               Paolo Narv{\'{a}}ez and
               Steven M. Burns and
               Ganapati Srinivasa},
  title     = {Trace alignment algorithms for offline workload analysis of heterogeneous
               architectures},
  booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
               ICCAD'13, San Jose, CA, USA, November 18-21, 2013},
  pages     = {654--661},
  year      = {2013},
  crossref  = {DBLP:conf/iccad/2013},
  url       = {https://doi.org/10.1109/ICCAD.2013.6691185},
  doi       = {10.1109/ICCAD.2013.6691185},
  timestamp = {Wed, 24 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/OzdalJNBS13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/ParasharPAACLPZGJARME13,
  author    = {Angshuman Parashar and
               Michael Pellauer and
               Michael Adler and
               Bushra Ahsan and
               Neal Clayton Crago and
               Daniel Lustig and
               Vladimir Pavlov and
               Antonia Zhai and
               Mohit Gambhir and
               Aamer Jaleel and
               Randy L. Allmon and
               Rachid Rayess and
               Stephen Maresh and
               Joel S. Emer},
  title     = {Triggered instructions: a control paradigm for spatially-programmed
               architectures},
  booktitle = {The 40th Annual International Symposium on Computer Architecture,
               ISCA'13, Tel-Aviv, Israel, June 23-27, 2013},
  pages     = {142--153},
  year      = {2013},
  crossref  = {DBLP:conf/isca/2013},
  url       = {https://doi.org/10.1145/2485922.2485935},
  doi       = {10.1145/2485922.2485935},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isca/ParasharPAACLPZGJARME13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/DomnitserJLAP12,
  author    = {Leonid Domnitser and
               Aamer Jaleel and
               Jason Loew and
               Nael B. Abu{-}Ghazaleh and
               Dmitry Ponomarev},
  title     = {Non-monopolizable caches: Low-complexity mitigation of cache side
               channel attacks},
  journal   = {{TACO}},
  volume    = {8},
  number    = {4},
  pages     = {35:1--35:21},
  year      = {2012},
  url       = {https://doi.org/10.1145/2086696.2086714},
  doi       = {10.1145/2086696.2086714},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/taco/DomnitserJLAP12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/HasenplaughAJSE12,
  author    = {William Hasenplaugh and
               Pritpal S. Ahuja and
               Aamer Jaleel and
               Simon C. Steely Jr. and
               Joel S. Emer},
  title     = {The gradient-based cache partitioning algorithm},
  journal   = {{TACO}},
  volume    = {8},
  number    = {4},
  pages     = {44:1--44:21},
  year      = {2012},
  url       = {https://doi.org/10.1145/2086696.2086723},
  doi       = {10.1145/2086696.2086723},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/taco/HasenplaughAJSE12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asplos/JaleelNSSE12,
  author    = {Aamer Jaleel and
               Hashem Hashemi Najaf{-}abadi and
               Samantika Subramaniam and
               Simon C. Steely Jr. and
               Joel S. Emer},
  title     = {{CRUISE:} cache replacement and utility-aware scheduling},
  booktitle = {Proceedings of the 17th International Conference on Architectural
               Support for Programming Languages and Operating Systems, {ASPLOS}
               2012, London, UK, March 3-7, 2012},
  pages     = {249--260},
  year      = {2012},
  crossref  = {DBLP:conf/asplos/2012},
  url       = {https://doi.org/10.1145/2150976.2151003},
  doi       = {10.1145/2150976.2151003},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/asplos/JaleelNSSE12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/CraeynestJENE12,
  author    = {Kenzo Van Craeynest and
               Aamer Jaleel and
               Lieven Eeckhout and
               Paolo Narv{\'{a}}ez and
               Joel S. Emer},
  title     = {Scheduling heterogeneous multi-cores through performance impact estimation
               {(PIE)}},
  booktitle = {39th International Symposium on Computer Architecture {(ISCA} 2012),
               June 9-13, 2012, Portland, OR, {USA}},
  pages     = {213--224},
  year      = {2012},
  crossref  = {DBLP:conf/isca/2012},
  url       = {https://doi.org/10.1109/ISCA.2012.6237019},
  doi       = {10.1109/ISCA.2012.6237019},
  timestamp = {Tue, 12 Feb 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isca/CraeynestJENE12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/PhamVJB12,
  author    = {Binh Pham and
               Viswanathan Vaidyanathan and
               Aamer Jaleel and
               Abhishek Bhattacharjee},
  title     = {CoLT: Coalesced Large-Reach TLBs},
  booktitle = {45th Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2012, Vancouver, BC, Canada, December 1-5, 2012},
  pages     = {258--269},
  year      = {2012},
  crossref  = {DBLP:conf/micro/2012},
  url       = {https://doi.org/10.1109/MICRO.2012.32},
  doi       = {10.1109/MICRO.2012.32},
  timestamp = {Thu, 09 Aug 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/micro/PhamVJB12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/WuJHMSE11,
  author    = {Carole{-}Jean Wu and
               Aamer Jaleel and
               William Hasenplaugh and
               Margaret Martonosi and
               Simon C. Steely Jr. and
               Joel S. Emer},
  title     = {SHiP: signature-based hit predictor for high performance caching},
  booktitle = {44rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2011, Porto Alegre, Brazil, December 3-7, 2011},
  pages     = {430--441},
  year      = {2011},
  crossref  = {DBLP:conf/micro/2011},
  url       = {https://doi.org/10.1145/2155620.2155671},
  doi       = {10.1145/2155620.2155671},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/micro/WuJHMSE11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/WuJMSE11,
  author    = {Carole{-}Jean Wu and
               Aamer Jaleel and
               Margaret Martonosi and
               Simon C. Steely Jr. and
               Joel S. Emer},
  title     = {PACMan: prefetch-aware cache management for high performance caching},
  booktitle = {44rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2011, Porto Alegre, Brazil, December 3-7, 2011},
  pages     = {442--453},
  year      = {2011},
  crossref  = {DBLP:conf/micro/2011},
  url       = {https://doi.org/10.1145/2155620.2155672},
  doi       = {10.1145/2155620.2155672},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/micro/WuJMSE11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/BachCCDDHJLLPT10,
  author    = {Moshe Bach and
               Mark Charney and
               Robert Cohn and
               Elena Demikhovsky and
               Tevi Devor and
               Kim M. Hazelwood and
               Aamer Jaleel and
               Chi{-}Keung Luk and
               Gail Lyons and
               Harish Patil and
               Ady Tal},
  title     = {Analyzing Parallel Programs with Pin},
  journal   = {{IEEE} Computer},
  volume    = {43},
  number    = {3},
  pages     = {34--41},
  year      = {2010},
  url       = {https://doi.org/10.1109/MC.2010.60},
  doi       = {10.1109/MC.2010.60},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/computer/BachCCDDHJLLPT10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/BiswasRMACJPPS10,
  author    = {Arijit Biswas and
               Charles Recchia and
               Shubhendu S. Mukherjee and
               Vinod Ambrose and
               Leo Chan and
               Aamer Jaleel and
               Athanasios E. Papathanasiou and
               Mike Plaster and
               Norbert Seifert},
  title     = {Explaining cache {SER} anomaly using {DUE} {AVF} measurement},
  booktitle = {16th International Conference on High-Performance Computer Architecture
               {(HPCA-16} 2010), 9-14 January 2010, Bangalore, India},
  pages     = {1--12},
  year      = {2010},
  crossref  = {DBLP:conf/hpca/2010},
  url       = {https://doi.org/10.1109/HPCA.2010.5416629},
  doi       = {10.1109/HPCA.2010.5416629},
  timestamp = {Thu, 07 Feb 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/BiswasRMACJPPS10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/JaleelTSE10,
  author    = {Aamer Jaleel and
               Kevin B. Theobald and
               Simon C. Steely Jr. and
               Joel S. Emer},
  title     = {High performance cache replacement using re-reference interval prediction
               {(RRIP)}},
  booktitle = {37th International Symposium on Computer Architecture {(ISCA} 2010),
               June 19-23, 2010, Saint-Malo, France},
  pages     = {60--71},
  year      = {2010},
  crossref  = {DBLP:conf/isca/2010},
  url       = {https://doi.org/10.1145/1815961.1815971},
  doi       = {10.1145/1815961.1815971},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isca/JaleelTSE10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/JaleelBBSE10,
  author    = {Aamer Jaleel and
               Eric Borch and
               Malini Bhandaru and
               Simon C. Steely Jr. and
               Joel S. Emer},
  title     = {Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal
               Locality Aware {(TLA)} Cache Management Policies},
  booktitle = {43rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2010, 4-8 December 2010, Atlanta, Georgia, {USA}},
  pages     = {151--162},
  year      = {2010},
  crossref  = {DBLP:conf/micro/2010},
  url       = {https://doi.org/10.1109/MICRO.2010.52},
  doi       = {10.1109/MICRO.2010.52},
  timestamp = {Sun, 21 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/micro/JaleelBBSE10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/MosesAJIINM09,
  author    = {Jaideep Moses and
               Konstantinos Aisopos and
               Aamer Jaleel and
               Ravi R. Iyer and
               Ramesh Illikkal and
               Donald Newell and
               Srihari Makineni},
  title     = {CMPSched{\textdollar}im: Evaluating {OS/CMP} interaction on shared
               cache management},
  booktitle = {{IEEE} International Symposium on Performance Analysis of Systems
               and Software, {ISPASS} 2009, April 26-28, 2009, Boston, Massachusetts,
               USA, Proceedings},
  pages     = {113--122},
  year      = {2009},
  crossref  = {DBLP:conf/ispass/2009},
  url       = {https://doi.org/10.1109/ISPASS.2009.4919643},
  doi       = {10.1109/ISPASS.2009.4919643},
  timestamp = {Wed, 13 Feb 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/ispass/MosesAJIINM09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispdc/LinCLJT09,
  author    = {Junmin Lin and
               Yu Chen and
               Wenlong Li and
               Aamer Jaleel and
               Zhizhong Tang},
  title     = {Understanding the Memory Behavior of Emerging Multi-core Workloads},
  booktitle = {Eighth International Symposium on Parallel and Distributed Computing,
               {ISPDC} 2009, Lisbon, Portugal, June 30-July 4 2009},
  pages     = {153--160},
  year      = {2009},
  crossref  = {DBLP:conf/ispdc/2009},
  url       = {https://doi.org/10.1109/ISPDC.2009.14},
  doi       = {10.1109/ISPDC.2009.14},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ispdc/LinCLJT09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/QureshiJPSE08,
  author    = {Moinuddin K. Qureshi and
               Aamer Jaleel and
               Yale N. Patt and
               Simon C. Steely Jr. and
               Joel S. Emer},
  title     = {Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching},
  journal   = {{IEEE} Micro},
  volume    = {28},
  number    = {1},
  pages     = {91--98},
  year      = {2008},
  url       = {https://doi.org/10.1109/MM.2008.14},
  doi       = {10.1109/MM.2008.14},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/micro/QureshiJPSE08},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/JaleelHQSSE08,
  author    = {Aamer Jaleel and
               William Hasenplaugh and
               Moinuddin K. Qureshi and
               Julien Sebot and
               Simon C. Steely Jr. and
               Joel S. Emer},
  title     = {Adaptive insertion policies for managing shared caches},
  booktitle = {17th International Conference on Parallel Architectures and Compilation
               Techniques, {PACT} 2008, Toronto, Ontario, Canada, October 25-29,
               2008},
  pages     = {208--219},
  year      = {2008},
  crossref  = {DBLP:conf/IEEEpact/2008},
  url       = {https://doi.org/10.1145/1454115.1454145},
  doi       = {10.1145/1454115.1454145},
  timestamp = {Mon, 15 Apr 2019 16:16:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/IEEEpact/JaleelHQSSE08},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipc/ChenLLJT08,
  author    = {Yu Chen and
               Wenlong Li and
               Junmin Lin and
               Aamer Jaleel and
               Zhizhong Tang},
  title     = {Data Sharing Analysis of Emerging Parallel Media Mining Workloads},
  booktitle = {High Performance Computing - HiPC 2008, 15th International Conference,
               Bangalore, India, December 17-20, 2008. Proceedings},
  pages     = {87--96},
  year      = {2008},
  crossref  = {DBLP:conf/hipc/2008},
  url       = {https://doi.org/10.1007/978-3-540-89894-8\_11},
  doi       = {10.1007/978-3-540-89894-8\_11},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hipc/ChenLLJT08},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/GaneshJWJ07,
  author    = {Brinda Ganesh and
               Aamer Jaleel and
               David Wang and
               Bruce L. Jacob},
  title     = {Fully-Buffered {DIMM} Memory Architectures: Understanding Mechanisms,
               Overheads and Scaling},
  booktitle = {13st International Conference on High-Performance Computer Architecture
               {(HPCA-13} 2007), 10-14 February 2007, Phoenix, Arizona, {USA}},
  pages     = {109--120},
  year      = {2007},
  crossref  = {DBLP:conf/hpca/2007},
  url       = {https://doi.org/10.1109/HPCA.2007.346190},
  doi       = {10.1109/HPCA.2007.346190},
  timestamp = {Wed, 14 Mar 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/GaneshJWJ07},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/QureshiJPSE07,
  author    = {Moinuddin K. Qureshi and
               Aamer Jaleel and
               Yale N. Patt and
               Simon C. Steely Jr. and
               Joel S. Emer},
  title     = {Adaptive insertion policies for high performance caching},
  booktitle = {34th International Symposium on Computer Architecture {(ISCA} 2007),
               June 9-13, 2007, San Diego, California, {USA}},
  pages     = {381--391},
  year      = {2007},
  crossref  = {DBLP:conf/isca/2007},
  url       = {https://doi.org/10.1145/1250662.1250709},
  doi       = {10.1145/1250662.1250709},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isca/QureshiJPSE07},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/LiLJSCWIIZLLWD07,
  author    = {Wenlong Li and
               Eric Q. Li and
               Aamer Jaleel and
               Jiulong Shan and
               Yurong Chen and
               Qigang Wang and
               Ravi R. Iyer and
               Ramesh Illikkal and
               Yimin Zhang and
               Dong Liu and
               Michael Liao and
               Wei Wei and
               Jinhua Du},
  title     = {Understanding the Memory Performance of Data-Mining Workloads on Small,
               Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation},
  booktitle = {2007 {IEEE} International Symposium on Performance Analysis of Systems
               and Software, April 25-27, 2007, San Jose, California, USA, Proceedings},
  pages     = {35--43},
  year      = {2007},
  crossref  = {DBLP:conf/ispass/2007},
  url       = {https://doi.org/10.1109/ISPASS.2007.363734},
  doi       = {10.1109/ISPASS.2007.363734},
  timestamp = {Mon, 20 Nov 2017 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/ispass/LiLJSCWIIZLLWD07},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/PerelmanLPJHC07,
  author    = {Erez Perelman and
               Jeremy Lau and
               Harish Patil and
               Aamer Jaleel and
               Greg Hamerly and
               Brad Calder},
  title     = {Cross Binary Simulation Points},
  booktitle = {2007 {IEEE} International Symposium on Performance Analysis of Systems
               and Software, April 25-27, 2007, San Jose, California, USA, Proceedings},
  pages     = {179--189},
  year      = {2007},
  crossref  = {DBLP:conf/ispass/2007},
  url       = {https://doi.org/10.1109/ISPASS.2007.363748},
  doi       = {10.1109/ISPASS.2007.363748},
  timestamp = {Sun, 04 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ispass/PerelmanLPJHC07},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/JaleelJ06,
  author    = {Aamer Jaleel and
               Bruce L. Jacob},
  title     = {In-Line Interrupt Handling and Lock-Up Free Translation Lookaside
               Buffers (TLBs)},
  journal   = {{IEEE} Trans. Computers},
  volume    = {55},
  number    = {5},
  pages     = {559--574},
  year      = {2006},
  url       = {https://doi.org/10.1109/TC.2006.77},
  doi       = {10.1109/TC.2006.77},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tc/JaleelJ06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/JaleelMJ06,
  author    = {Aamer Jaleel and
               Matthew Mattina and
               Bruce L. Jacob},
  title     = {Last level cache {(LLC)} performance of data mining workloads on a
               {CMP} - a case study of parallel bioinformatics workloads},
  booktitle = {12th International Symposium on High-Performance Computer Architecture,
               {HPCA-12} 2006, Austin, Texas, USA, February 11-15, 2006},
  pages     = {88--98},
  year      = {2006},
  crossref  = {DBLP:conf/hpca/2006},
  url       = {https://doi.org/10.1109/HPCA.2006.1598115},
  doi       = {10.1109/HPCA.2006.1598115},
  timestamp = {Wed, 20 Jun 2018 17:44:09 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/JaleelMJ06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/WangGTBJJ05,
  author    = {David Wang and
               Brinda Ganesh and
               Nuengwong Tuaycharoen and
               Kathleen Baynes and
               Aamer Jaleel and
               Bruce L. Jacob},
  title     = {DRAMsim: a memory system simulator},
  journal   = {{SIGARCH} Computer Architecture News},
  volume    = {33},
  number    = {4},
  pages     = {100--107},
  year      = {2005},
  url       = {https://doi.org/10.1145/1105734.1105748},
  doi       = {10.1145/1105734.1105748},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/sigarch/WangGTBJJ05},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/JaleelJ05,
  author    = {Aamer Jaleel and
               Bruce L. Jacob},
  title     = {Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects
               of Reordered Memory Instructions},
  booktitle = {11th International Conference on High-Performance Computer Architecture
               {(HPCA-11} 2005), 12-16 February 2005, San Francisco, CA, {USA}},
  pages     = {191--200},
  year      = {2005},
  crossref  = {DBLP:conf/hpca/2005},
  url       = {https://doi.org/10.1109/HPCA.2005.42},
  doi       = {10.1109/HPCA.2005.42},
  timestamp = {Fri, 19 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/JaleelJ05},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispass/AlbayraktarogluJWFJTY05,
  author    = {Kursad Albayraktaroglu and
               Aamer Jaleel and
               Xue Wu and
               Manoj Franklin and
               Bruce L. Jacob and
               Chau{-}Wen Tseng and
               Donald Yeung},
  title     = {BioBench: {A} Benchmark Suite of Bioinformatics Applications},
  booktitle = {{IEEE} International Symposium on Performance Analysis of Systems
               and Software, {ISPASS} 2005, March 20-22, 2005, Austin, Texas, USA,
               Proceedings},
  pages     = {2--9},
  year      = {2005},
  crossref  = {DBLP:conf/ispass/2005},
  url       = {https://doi.org/10.1109/ISPASS.2005.1430554},
  doi       = {10.1109/ISPASS.2005.1430554},
  timestamp = {Fri, 08 Mar 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/ispass/AlbayraktarogluJWFJTY05},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipc/JaleelJ01,
  author    = {Aamer Jaleel and
               Bruce L. Jacob},
  title     = {Improving the Precise Interrupt Mechanism of Software-Managed {TLB}
               Miss Handlers},
  booktitle = {High Performance Computing - HiPC 2001, 8th International Conference,
               Hyderabad, India, December, 17-20, 2001, Proceedings},
  pages     = {282--293},
  year      = {2001},
  crossref  = {DBLP:conf/hipc/2001},
  url       = {https://doi.org/10.1007/3-540-45307-5\_25},
  doi       = {10.1007/3-540-45307-5\_25},
  timestamp = {Fri, 26 May 2017 14:09:14 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hipc/JaleelJ01},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/JaleelJ01,
  author    = {Aamer Jaleel and
               Bruce L. Jacob},
  title     = {In-Line Interrupt Handling for Software-Managed TLBs},
  booktitle = {19th International Conference on Computer Design {(ICCD} 2001), {VLSI}
               in Computers and Processors, 23-26 September 2001, Austin, TX, USA,
               Proceedings},
  pages     = {62--67},
  year      = {2001},
  crossref  = {DBLP:conf/iccd/2001},
  url       = {https://doi.org/10.1109/ICCD.2001.955004},
  doi       = {10.1109/ICCD.2001.955004},
  timestamp = {Wed, 24 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccd/JaleelJ01},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isca/2018,
  editor    = {Murali Annavaram and
               Timothy M. Pinkston and
               Babak Falsafi},
  title     = {45th {ACM/IEEE} Annual International Symposium on Computer Architecture,
               {ISCA} 2018, Los Angeles, CA, USA, June 1-6, 2018},
  publisher = {{IEEE} Computer Society},
  year      = {2018},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8401306},
  isbn      = {978-1-5386-5984-7},
  timestamp = {Sun, 09 Sep 2018 11:52:43 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isca/2018},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2018,
  title     = {51st Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2018, Fukuoka, Japan, October 20-24, 2018},
  publisher = {{IEEE} Computer Society},
  year      = {2018},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8573939},
  isbn      = {978-1-5386-6240-3},
  timestamp = {Wed, 13 Feb 2019 11:42:26 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/micro/2018},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/cf/2017,
  title     = {Proceedings of the Computing Frontiers Conference, CF'17, Siena, Italy,
               May 15-17, 2017},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3075564},
  doi       = {10.1145/3075564},
  isbn      = {978-1-4503-4487-6},
  timestamp = {Tue, 06 Nov 2018 11:07:32 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/cf/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dac/2017,
  title     = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
               2017, Austin, TX, USA, June 18-22, 2017},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3061639},
  doi       = {10.1145/3061639},
  isbn      = {978-1-4503-4927-7},
  timestamp = {Tue, 06 Nov 2018 16:58:15 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/dac/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isca/2017,
  title     = {Proceedings of the 44th Annual International Symposium on Computer
               Architecture, {ISCA} 2017, Toronto, ON, Canada, June 24-28, 2017},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3079856},
  doi       = {10.1145/3079856},
  isbn      = {978-1-4503-4892-8},
  timestamp = {Tue, 06 Nov 2018 11:07:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/isca/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/memsys/2017,
  title     = {Proceedings of the International Symposium on Memory Systems, {MEMSYS}
               2017, Alexandria, VA, USA, October 02 - 05, 2017},
  publisher = {{ACM}},
  year      = {2017},
  url       = {http://dl.acm.org/citation.cfm?id=3132402},
  isbn      = {978-1-4503-5335-9},
  timestamp = {Wed, 25 Oct 2017 21:23:59 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/memsys/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2017,
  editor    = {Hillery C. Hunter and
               Jaime Moreno and
               Joel S. Emer and
               Daniel S{\'{a}}nchez},
  title     = {Proceedings of the 50th Annual {IEEE/ACM} International Symposium
               on Microarchitecture, {MICRO} 2017, Cambridge, MA, USA, October 14-18,
               2017},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3123939},
  doi       = {10.1145/3123939},
  isbn      = {978-1-4503-4952-9},
  timestamp = {Tue, 06 Nov 2018 16:58:26 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/micro/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dac/2016,
  title     = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
               2016, Austin, TX, USA, June 5-9, 2016},
  publisher = {{ACM}},
  year      = {2016},
  url       = {https://doi.org/10.1145/2897937},
  doi       = {10.1145/2897937},
  isbn      = {978-1-4503-4236-0},
  timestamp = {Tue, 06 Nov 2018 16:58:19 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/dac/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isca/2016,
  title     = {43rd {ACM/IEEE} Annual International Symposium on Computer Architecture,
               {ISCA} 2016, Seoul, South Korea, June 18-22, 2016},
  publisher = {{IEEE} Computer Society},
  year      = {2016},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7551325},
  isbn      = {978-1-4673-8947-1},
  timestamp = {Tue, 20 Sep 2016 12:04:25 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isca/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/memsys/2016,
  editor    = {Bruce Jacob},
  title     = {Proceedings of the Second International Symposium on Memory Systems,
               {MEMSYS} 2016, Alexandria, VA, USA, October 3-6, 2016},
  publisher = {{ACM}},
  year      = {2016},
  url       = {https://doi.org/10.1145/2989081},
  doi       = {10.1145/2989081},
  isbn      = {978-1-4503-4305-3},
  timestamp = {Tue, 06 Nov 2018 11:07:11 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/memsys/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2016,
  title     = {49th Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2016, Taipei, Taiwan, October 15-19, 2016},
  publisher = {{IEEE} Computer Society},
  year      = {2016},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7777315},
  isbn      = {978-1-5090-3508-3},
  timestamp = {Sat, 10 Mar 2018 14:44:10 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/micro/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hpca/2015,
  title     = {21st {IEEE} International Symposium on High Performance Computer Architecture,
               {HPCA} 2015, Burlingame, CA, USA, February 7-11, 2015},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7048058},
  isbn      = {978-1-4799-8930-0},
  timestamp = {Wed, 29 Mar 2017 16:45:26 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/2015},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isca/2015,
  editor    = {Deborah T. Marr and
               David H. Albonesi},
  title     = {Proceedings of the 42nd Annual International Symposium on Computer
               Architecture, Portland, OR, USA, June 13-17, 2015},
  publisher = {{ACM}},
  year      = {2015},
  url       = {http://dl.acm.org/citation.cfm?id=2749469},
  isbn      = {978-1-4503-3402-0},
  timestamp = {Wed, 27 May 2015 08:30:30 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isca/2015},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hpca/2014,
  title     = {20th {IEEE} International Symposium on High Performance Computer Architecture,
               {HPCA} 2014, Orlando, FL, USA, February 15-19, 2014},
  publisher = {{IEEE} Computer Society},
  year      = {2014},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6823235},
  isbn      = {978-1-4799-3097-5},
  timestamp = {Tue, 07 Oct 2014 17:26:19 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/2014},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ics/2014ross,
  editor    = {Kamil Iskra and
               Torsten Hoefler},
  title     = {Proceedings of the 4th International Workshop on Runtime and Operating
               Systems for Supercomputers, {ROSS} 2014, Munich, Germany, June 10,
               2014},
  publisher = {{ACM}},
  year      = {2014},
  url       = {https://doi.org/10.1145/2612262},
  doi       = {10.1145/2612262},
  isbn      = {978-1-4503-2950-7},
  timestamp = {Tue, 06 Nov 2018 11:07:02 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/ics/2014ross},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2014,
  title     = {47th Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2014, Cambridge, United Kingdom, December 13-17, 2014},
  publisher = {{IEEE} Computer Society},
  year      = {2014},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7008946},
  isbn      = {978-1-4799-6998-2},
  timestamp = {Fri, 23 Dec 2016 12:56:23 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/micro/2014},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/IEEEpact/2013,
  editor    = {Christian Fensch and
               Michael F. P. O'Boyle and
               Andr{\'{e}} Seznec and
               Fran{\c{c}}ois Bodin},
  title     = {Proceedings of the 22nd International Conference on Parallel Architectures
               and Compilation Techniques, Edinburgh, United Kingdom, September 7-11,
               2013},
  publisher = {{IEEE} Computer Society},
  year      = {2013},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6603429},
  isbn      = {978-1-4799-1018-2},
  timestamp = {Tue, 02 Jun 2015 18:34:40 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/IEEEpact/2013},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iccad/2013,
  editor    = {J{\"{o}}rg Henkel},
  title     = {The {IEEE/ACM} International Conference on Computer-Aided Design,
               ICCAD'13, San Jose, CA, USA, November 18-21, 2013},
  publisher = {{IEEE}},
  year      = {2013},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6679730},
  isbn      = {978-1-4799-1069-4},
  timestamp = {Thu, 30 Apr 2015 18:34:35 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/2013},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isca/2013,
  editor    = {Avi Mendelson},
  title     = {The 40th Annual International Symposium on Computer Architecture,
               ISCA'13, Tel-Aviv, Israel, June 23-27, 2013},
  publisher = {{ACM}},
  year      = {2013},
  url       = {http://dl.acm.org/citation.cfm?id=2485922},
  isbn      = {978-1-4503-2079-5},
  timestamp = {Fri, 28 Jun 2013 09:25:07 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isca/2013},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/asplos/2012,
  editor    = {Tim Harris and
               Michael L. Scott},
  title     = {Proceedings of the 17th International Conference on Architectural
               Support for Programming Languages and Operating Systems, {ASPLOS}
               2012, London, UK, March 3-7, 2012},
  publisher = {{ACM}},
  year      = {2012},
  isbn      = {978-1-4503-0759-8},
  timestamp = {Tue, 07 Apr 2015 18:52:40 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/asplos/2012},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isca/2012,
  title     = {39th International Symposium on Computer Architecture {(ISCA} 2012),
               June 9-13, 2012, Portland, OR, {USA}},
  publisher = {{IEEE} Computer Society},
  year      = {2012},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6230820},
  isbn      = {978-1-4673-0475-7},
  timestamp = {Thu, 16 Oct 2014 17:35:15 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isca/2012},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2012,
  title     = {45th Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2012, Vancouver, BC, Canada, December 1-5, 2012},
  publisher = {{IEEE} Computer Society},
  year      = {2012},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6490492},
  isbn      = {978-1-4673-4819-5},
  timestamp = {Thu, 18 Sep 2014 16:58:21 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/micro/2012},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2011,
  editor    = {Carlo Galuzzi and
               Luigi Carro and
               Andreas Moshovos and
               Milos Prvulovic},
  title     = {44rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2011, Porto Alegre, Brazil, December 3-7, 2011},
  publisher = {{ACM}},
  year      = {2011},
  url       = {http://dl.acm.org/citation.cfm?id=2155620},
  isbn      = {978-1-4503-1053-6},
  timestamp = {Fri, 17 Feb 2017 11:09:56 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/micro/2011},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hpca/2010,
  editor    = {Matthew T. Jacob and
               Chita R. Das and
               Pradip Bose},
  title     = {16th International Conference on High-Performance Computer Architecture
               {(HPCA-16} 2010), 9-14 January 2010, Bangalore, India},
  publisher = {{IEEE} Computer Society},
  year      = {2010},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5410726},
  isbn      = {978-1-4244-5659-8},
  timestamp = {Tue, 07 Oct 2014 17:26:20 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/2010},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isca/2010,
  editor    = {Andr{\'{e}} Seznec and
               Uri C. Weiser and
               Ronny Ronen},
  title     = {37th International Symposium on Computer Architecture {(ISCA} 2010),
               June 19-23, 2010, Saint-Malo, France},
  publisher = {{ACM}},
  year      = {2010},
  url       = {http://dl.acm.org/citation.cfm?id=1815961},
  isbn      = {978-1-4503-0053-7},
  timestamp = {Thu, 16 Oct 2014 17:35:16 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isca/2010},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/micro/2010,
  title     = {43rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
               {MICRO} 2010, 4-8 December 2010, Atlanta, Georgia, {USA}},
  publisher = {{IEEE} Computer Society},
  year      = {2010},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5692847},
  isbn      = {978-0-7695-4299-7},
  timestamp = {Thu, 18 Sep 2014 16:58:22 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/micro/2010},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ispass/2009,
  title     = {{IEEE} International Symposium on Performance Analysis of Systems
               and Software, {ISPASS} 2009, April 26-28, 2009, Boston, Massachusetts,
               USA, Proceedings},
  publisher = {{IEEE} Computer Society},
  year      = {2009},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4907867},
  isbn      = {978-1-4244-4184-6},
  timestamp = {Mon, 04 May 2015 17:00:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ispass/2009},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ispdc/2009,
  editor    = {Leonel Sousa and
               Yves Robert},
  title     = {Eighth International Symposium on Parallel and Distributed Computing,
               {ISPDC} 2009, Lisbon, Portugal, June 30-July 4 2009},
  publisher = {{IEEE} Computer Society},
  year      = {2009},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5284332},
  isbn      = {978-0-7695-3680-4},
  timestamp = {Fri, 10 Oct 2014 14:35:25 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ispdc/2009},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/IEEEpact/2008,
  editor    = {Andreas Moshovos and
               David Tarditi and
               Kunle Olukotun},
  title     = {17th International Conference on Parallel Architectures and Compilation
               Techniques, {PACT} 2008, Toronto, Ontario, Canada, October 25-29,
               2008},
  publisher = {{ACM}},
  year      = {2008},
  url       = {https://doi.org/10.1145/1454115},
  doi       = {10.1145/1454115},
  isbn      = {978-1-60558-282-5},
  timestamp = {Mon, 15 Apr 2019 16:16:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/IEEEpact/2008},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipc/2008,
  editor    = {P. Sadayappan and
               Manish Parashar and
               Ramamurthy Badrinath and
               Viktor K. Prasanna},
  title     = {High Performance Computing - HiPC 2008, 15th International Conference,
               Bangalore, India, December 17-20, 2008. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {5374},
  publisher = {Springer},
  year      = {2008},
  url       = {https://doi.org/10.1007/978-3-540-89894-8},
  doi       = {10.1007/978-3-540-89894-8},
  isbn      = {978-3-540-89893-1},
  timestamp = {Fri, 26 May 2017 00:49:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hipc/2008},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hpca/2007,
  title     = {13st International Conference on High-Performance Computer Architecture
               {(HPCA-13} 2007), 10-14 February 2007, Phoenix, Arizona, {USA}},
  publisher = {{IEEE} Computer Society},
  year      = {2007},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4147635},
  isbn      = {1-4244-0804-0},
  timestamp = {Tue, 07 Oct 2014 17:26:19 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/2007},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isca/2007,
  editor    = {Dean M. Tullsen and
               Brad Calder},
  title     = {34th International Symposium on Computer Architecture {(ISCA} 2007),
               June 9-13, 2007, San Diego, California, {USA}},
  publisher = {{ACM}},
  year      = {2007},
  url       = {http://dl.acm.org/citation.cfm?id=1250662},
  isbn      = {978-1-59593-706-3},
  timestamp = {Thu, 16 Oct 2014 17:35:15 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isca/2007},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ispass/2007,
  title     = {2007 {IEEE} International Symposium on Performance Analysis of Systems
               and Software, April 25-27, 2007, San Jose, California, USA, Proceedings},
  publisher = {{IEEE} Computer Society},
  year      = {2007},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4211006},
  isbn      = {1-4244-1081-9},
  timestamp = {Mon, 04 May 2015 17:00:48 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ispass/2007},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hpca/2006,
  title     = {12th International Symposium on High-Performance Computer Architecture,
               {HPCA-12} 2006, Austin, Texas, USA, February 11-15, 2006},
  publisher = {{IEEE} Computer Society},
  year      = {2006},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=10647},
  isbn      = {0-7803-9368-6},
  timestamp = {Wed, 20 Jun 2018 17:44:09 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/2006},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hpca/2005,
  title     = {11th International Conference on High-Performance Computer Architecture
               {(HPCA-11} 2005), 12-16 February 2005, San Francisco, CA, {USA}},
  publisher = {{IEEE} Computer Society},
  year      = {2005},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9519},
  isbn      = {0-7695-2275-0},
  timestamp = {Tue, 07 Oct 2014 17:26:20 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hpca/2005},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ispass/2005,
  title     = {{IEEE} International Symposium on Performance Analysis of Systems
               and Software, {ISPASS} 2005, March 20-22, 2005, Austin, Texas, USA,
               Proceedings},
  publisher = {{IEEE} Computer Society},
  year      = {2005},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9783},
  isbn      = {0-7803-8965-4},
  timestamp = {Mon, 04 May 2015 17:00:50 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ispass/2005},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipc/2001,
  editor    = {Burkhard Monien and
               Viktor K. Prasanna and
               Sriram Vajapeyam},
  title     = {High Performance Computing - HiPC 2001, 8th International Conference,
               Hyderabad, India, December, 17-20, 2001, Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {2228},
  publisher = {Springer},
  year      = {2001},
  url       = {https://doi.org/10.1007/3-540-45307-5},
  doi       = {10.1007/3-540-45307-5},
  isbn      = {3-540-43009-1},
  timestamp = {Fri, 26 May 2017 14:09:14 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hipc/2001},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iccd/2001,
  title     = {19th International Conference on Computer Design {(ICCD} 2001), {VLSI}
               in Computers and Processors, 23-26 September 2001, Austin, TX, USA,
               Proceedings},
  publisher = {{IEEE} Computer Society},
  year      = {2001},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7577},
  isbn      = {0-7695-1200-3},
  timestamp = {Mon, 22 Sep 2014 16:50:07 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccd/2001},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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