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ORCIDBibTeX records: Vikram Iyengar
@article{DBLP:journals/tcad/LinPBNLI12,
author = {Yen{-}Tzu Lin and
Osei Poku and
R. D. (Shawn) Blanton and
Phil Nigh and
Peter Lloyd and
Vikram Iyengar},
title = {Physically-Aware N-Detect Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {308--321},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2168526},
doi = {10.1109/TCAD.2011.2168526},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinPBNLI12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/KellerCFCMSILG10,
author = {Brion L. Keller and
Krishna Chakravadhanula and
Brian Foutz and
Vivek Chickermane and
R. Malneedi and
Thomas J. Snethen and
Vikram Iyengar and
David E. Lackey and
Gary Grise},
editor = {Ron Press and
Erik H. Volkerink},
title = {Low cost at-speed testing using On-Product Clock Generation compatible
with test compression},
booktitle = {2011 {IEEE} International Test Conference, {ITC} 2010, Austin, TX,
USA, November 2-4, 2010},
pages = {724--733},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/TEST.2010.5699276},
doi = {10.1109/TEST.2010.5699276},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/KellerCFCMSILG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BahukudumbiOCI09,
author = {Sudarshan Bahukudumbi and
Sule Ozev and
Krishnendu Chakrabarty and
Vikram Iyengar},
title = {Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal
SoCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {17},
number = {4},
pages = {587--592},
year = {2009},
url = {https://doi.org/10.1109/TVLSI.2008.2006075},
doi = {10.1109/TVLSI.2008.2006075},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BahukudumbiOCI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/LinPBNLI08,
author = {Yen{-}Tzu Lin and
Osei Poku and
Ronald D. Blanton and
Phil Nigh and
Peter Lloyd and
Vikram Iyengar},
editor = {Douglas Young and
Nur A. Touba},
title = {Evaluating the Effectiveness of Physically-Aware N-Detect Test using
Real Silicon},
booktitle = {2008 {IEEE} International Test Conference, {ITC} 2008, Santa Clara,
California, USA, October 26-31, 2008},
pages = {1--9},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/TEST.2008.4700606},
doi = {10.1109/TEST.2008.4700606},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/LinPBNLI08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/BahukudumbiOCI07,
author = {Sudarshan Bahukudumbi and
Sule Ozev and
Krishnendu Chakrabarty and
Vikram Iyengar},
title = {AWafer-Level Defect Screening Technique to Reduce Test and Packaging
Costs for "Big-D/Small-A" Mixed-Signal SoCs},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {823--828},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.358091},
doi = {10.1109/ASPDAC.2007.358091},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/BahukudumbiOCI07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/IyengarXVZLHV07,
author = {Vikram Iyengar and
Jinjun Xiong and
Subbayyan Venkatesan and
Vladimir Zolotov and
David E. Lackey and
Peter A. Habitz and
Chandu Visweswariah},
editor = {Georges G. E. Gielen},
title = {Variation-aware performance verification using at-speed structural
test and statistical timing},
booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
San Jose, CA, USA, November 5-8, 2007},
pages = {405--412},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICCAD.2007.4397299},
doi = {10.1109/ICCAD.2007.4397299},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/IyengarXVZLHV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/IyengarPFWLGTDO07,
author = {Vikram Iyengar and
Kenneth Pichamuthu and
Andrew Ferko and
Frank Woytowich and
David E. Lackey and
Gary Grise and
Mark Taylor and
Mike Degregorio and
Steven F. Oakland},
title = {An Integrated Framework for At-Speed and ATE-Driven Delay Test of
Contract-Manufactured ASICs},
booktitle = {25th {IEEE} {VLSI} Test Symposium {(VTS} 2007), 6-10 May 2007, Berkeley,
California, {USA}},
pages = {173--178},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VTS.2007.15},
doi = {10.1109/VTS.2007.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/IyengarPFWLGTDO07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/IyengarJAGTFWB06,
author = {Vikram Iyengar and
Mark Johnson and
Theo Anemikos and
Gary Grise and
Mark Taylor and
Raymond Farmer and
Frank Woytowich and
Bob Bassett},
title = {Design For At-Speed Structural Test And Performance Verification Of
High-Performance ASICs},
booktitle = {Proceedings of the {IEEE} 2006 Custom Integrated Circuits Conference,
{CICC} 2006, DoubleTree Hotel, San Jose, California, USA, September
10-13, 2006},
pages = {567--570},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/CICC.2006.320991},
doi = {10.1109/CICC.2006.320991},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/IyengarJAGTFWB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/IyengarGT06,
author = {Vikram Iyengar and
Gary Grise and
Mark Taylor},
editor = {Ellen Sentovich},
title = {A flexible and scalable methodology for GHz-speed structural test},
booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006,
San Francisco, CA, USA, July 24-28, 2006},
pages = {314--319},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1146909.1146992},
doi = {10.1145/1146909.1146992},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/IyengarGT06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LiuI06,
author = {Chunsheng Liu and
Vikram Iyengar},
editor = {Georges G. E. Gielen},
title = {Test scheduling with thermal optimization for network-on-chip systems
using variable-rate on-chip clocking},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {652--657},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.244013},
doi = {10.1109/DATE.2006.244013},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/LiuI06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/IyengarJABDFGSTW06,
author = {Vikram Iyengar and
Mark Johnson and
Theo Anemikos and
Bob Bassett and
Mike Degregorio and
Rudy Farmer and
Gary Grise and
Phil Stevens and
Mark Taylor and
Frank Woytowich},
editor = {Gang Qu and
Yehea I. Ismail and
Narayanan Vijaykrishnan and
Hai Zhou},
title = {Performance verification of high-performance ASICs using at-speed
structural test},
booktitle = {Proceedings of the 16th {ACM} Great Lakes Symposium on {VLSI} 2006,
Philadelphia, PA, USA, April 30 - May 1, 2006},
pages = {247--252},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1127908.1127966},
doi = {10.1145/1127908.1127966},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/IyengarJABDFGSTW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/IyengarYYABDFGJMTW06,
author = {Vikram Iyengar and
Toshihiko Yokota and
Kazuhiro Yamada and
Theo Anemikos and
Bob Bassett and
Mike Degregorio and
Rudy Farmer and
Gary Grise and
Mark Johnson and
Dave Milton and
Mark Taylor and
Frank Woytowich},
editor = {Scott Davidson and
Anne Gattiker},
title = {At-Speed Structural Test For High-Performance ASICs},
booktitle = {2006 {IEEE} International Test Conference, {ITC} 2006, Santa Clara,
CA, USA, October 22-27, 2006},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/TEST.2006.297686},
doi = {10.1109/TEST.2006.297686},
timestamp = {Tue, 12 Dec 2023 09:46:27 +0100},
biburl = {https://dblp.org/rec/conf/itc/IyengarYYABDFGJMTW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/LiuIP06,
author = {Chunsheng Liu and
Vikram Iyengar and
Dhiraj K. Pradhan},
title = {Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency
Clocking},
booktitle = {24th {IEEE} {VLSI} Test Symposium {(VTS} 2006), 30 April - 4 May 2006,
Berkeley, California, {USA}},
pages = {46--51},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VTS.2006.88},
doi = {10.1109/VTS.2006.88},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/LiuIP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChakrabartyIK05,
author = {Krishnendu Chakrabarty and
Vikram Iyengar and
Mark D. Krasniewski},
title = {Test planning for modular testing of hierarchical SOCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {3},
pages = {435--448},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2004.842816},
doi = {10.1109/TCAD.2004.842816},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChakrabartyIK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/IyengarN05,
author = {Vikram Iyengar and
Phil Nigh},
title = {Defect-Oriented Test for Ultra-Low {DPM}},
booktitle = {14th Asian Test Symposium {(ATS} 2005), 18-21 December 2005, Calcutta,
India},
pages = {455},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ATS.2005.44},
doi = {10.1109/ATS.2005.44},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/IyengarN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/LiuVI05,
author = {Chunsheng Liu and
Kugesh Veeraraghavant and
Vikram Iyengar},
title = {Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization
for Core-Based Systems},
booktitle = {20th {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2005), 3-5 October 2005, Monterey, CA, {USA}},
pages = {552--562},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DFTVS.2005.66},
doi = {10.1109/DFTVS.2005.66},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/LiuVI05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iros/CsencsitsJMIW05,
author = {Matthew A. Csencsits and
Bryan A. Jones and
William McMahan and
Vikram Iyengar and
Ian D. Walker},
title = {User interfaces for continuum robot arms},
booktitle = {2005 {IEEE/RSJ} International Conference on Intelligent Robots and
Systems, Edmonton, Alberta, Canada, August 2-6, 2005},
pages = {3123--3130},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/IROS.2005.1545434},
doi = {10.1109/IROS.2005.1545434},
timestamp = {Wed, 16 Oct 2019 14:14:51 +0200},
biburl = {https://dblp.org/rec/conf/iros/CsencsitsJMIW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/LiuISC05,
author = {Chunsheng Liu and
Vikram Iyengar and
Jiangfan Shi and
{\'{E}}rika F. Cota},
title = {Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate
On-Chip Clocking},
booktitle = {23rd {IEEE} {VLSI} Test Symposium {(VTS} 2005), 1-5 May 2005, Palm
Springs, CA, {USA}},
pages = {349--354},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/VTS.2005.66},
doi = {10.1109/VTS.2005.66},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/LiuISC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SehgalIC04,
author = {Anuja Sehgal and
Vikram Iyengar and
Krishnendu Chakrabarty},
title = {{SOC} test planning using virtual test access architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {12},
number = {12},
pages = {1263--1276},
year = {2004},
url = {https://doi.org/10.1109/TVLSI.2004.834228},
doi = {10.1109/TVLSI.2004.834228},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SehgalIC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/IyengarCM03,
author = {Vikram Iyengar and
Krishnendu Chakrabarty and
Erik Jan Marinissen},
title = {Test Access Mechanism Optimization, Test Scheduling, and Tester Data
Volume Reduction for System-on-Chip},
journal = {{IEEE} Trans. Computers},
volume = {52},
number = {12},
pages = {1619--1632},
year = {2003},
url = {https://doi.org/10.1109/TC.2003.1252857},
doi = {10.1109/TC.2003.1252857},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/IyengarCM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IyengarCM03,
author = {Vikram Iyengar and
Krishnendu Chakrabarty and
Erik Jan Marinissen},
title = {Efficient test access mechanism optimization for system-on-chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {5},
pages = {635--643},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.810737},
doi = {10.1109/TCAD.2003.810737},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/IyengarCM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SehgalIKC03,
author = {Anuja Sehgal and
Vikram Iyengar and
Mark D. Krasniewski and
Krishnendu Chakrabarty},
title = {Test cost reduction for SOCs using virtual TAMs and lagrange multipliers},
booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003,
Anaheim, CA, USA, June 2-6, 2003},
pages = {738--743},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/775832.776021},
doi = {10.1145/775832.776021},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SehgalIKC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/IyengarCSC03,
author = {Vikram Iyengar and
Anshuman Chandra and
Sharon Schweizer and
Krishnendu Chakrabarty},
title = {A Unified Approach for {SOC} Testing Using Test Data Compression and
{TAM} Optimization},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {11188--11190},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10043},
doi = {10.1109/DATE.2003.10043},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/IyengarCSC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/IyengarC03,
author = {Vikram Iyengar and
Anshuman Chandra},
title = {A Uni.ed {SOC} Test Approach Based on Test Data Compression and {TAM}
Design},
booktitle = {18th {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2003), 3-5 November 2003, Boston, MA, USA,
Proceedings},
pages = {511--518},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/DFTVS.2003.1250150},
doi = {10.1109/DFTVS.2003.1250150},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/IyengarC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/IyengarCKK03,
author = {Vikram Iyengar and
Krishnendu Chakrabarty and
Mark D. Krasniewski and
Gopind N. Kumar},
title = {Design and Optimization of Multi-level {TAM} Architectures for Hierarchical
SOCs},
booktitle = {21st {IEEE} {VLSI} Test Symposium {(VTS} 2003), 27 April - 1 May 2003,
Napa Valley, CA, {USA}},
pages = {299--312},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/VTEST.2003.1197667},
doi = {10.1109/VTEST.2003.1197667},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/IyengarCKK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0029046,
author = {Krishnendu Chakrabarty and
Vikram Iyengar and
Anshuman Chandra},
title = {Test Resource Partitioning for System-on-a-Chip},
series = {Frontiers in electronic testing},
volume = {20},
publisher = {Kluwer / Springer},
year = {2002},
url = {http://www.springer.com/engineering/circuits+\%26+systems/book/978-1-4020-7119-5},
isbn = {978-1-4020-7119-5},
timestamp = {Tue, 04 Sep 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0029046.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/IyengarCM02,
author = {Vikram Iyengar and
Krishnendu Chakrabarty and
Erik Jan Marinissen},
title = {Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip},
journal = {J. Electron. Test.},
volume = {18},
number = {2},
pages = {213--230},
year = {2002},
url = {https://doi.org/10.1023/A:1014916913577},
doi = {10.1023/A:1014916913577},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/et/IyengarCM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/IyengarC02,
author = {Vikram Iyengar and
Krishnendu Chakrabarty},
title = {Test Bus Sizing for System-on-a-Chip},
journal = {{IEEE} Trans. Computers},
volume = {51},
number = {5},
pages = {449--459},
year = {2002},
url = {https://doi.org/10.1109/TC.2002.1004585},
doi = {10.1109/TC.2002.1004585},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/IyengarC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IyengarC02,
author = {Vikram Iyengar and
Krishnendu Chakrabarty},
title = {System-on-a-chip test scheduling with precedence relationships, preemption,
and power constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1088--1094},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801102},
doi = {10.1109/TCAD.2002.801102},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/IyengarC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/IyengarCM02,
author = {Vikram Iyengar and
Krishnendu Chakrabarty and
Erik Jan Marinissen},
title = {Recent Advances in Test Planning for Modular Testing of Core-Based
SOCs},
booktitle = {11th Asian Test Symposium {(ATS} 2002), 18-20 November 2002, Guam,
{USA}},
pages = {320},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ATS.2002.1181731},
doi = {10.1109/ATS.2002.1181731},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/IyengarCM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/IyengarCM02,
author = {Vikram Iyengar and
Krishnendu Chakrabarty and
Erik Jan Marinissen},
title = {Wrapper/TAM co-optimization, constraint-driven test scheduling, and
tester data volume reduction for SOCs},
booktitle = {Proceedings of the 39th Design Automation Conference, {DAC} 2002,
New Orleans, LA, USA, June 10-14, 2002},
pages = {685--690},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/513918.514092},
doi = {10.1145/513918.514092},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/IyengarCM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/IyengarCM02,
author = {Vikram Iyengar and
Krishnendu Chakrabarty and
Erik Jan Marinissen},
title = {Efficient Wrapper/TAM Co-Optimization for Large SOCs},
booktitle = {2002 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2002), 4-8 March 2002, Paris, France},
pages = {491--498},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DATE.2002.998318},
doi = {10.1109/DATE.2002.998318},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/IyengarCM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/MarinissenIC02,
author = {Erik Jan Marinissen and
Vikram Iyengar and
Krishnendu Chakrabarty},
title = {A Set of Benchmarks fo Modular Testing of SOCs},
booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore,
MD, USA, October 7-10, 2002},
pages = {519--528},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/TEST.2002.1041802},
doi = {10.1109/TEST.2002.1041802},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/MarinissenIC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/KoranneI02,
author = {Sandeep Koranne and
Vikram Iyengar},
title = {On the Use of k-tuples for SoC Test Schedule Representation},
booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore,
MD, USA, October 7-10, 2002},
pages = {539--548},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/TEST.2002.1041804},
doi = {10.1109/TEST.2002.1041804},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/KoranneI02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/IyengarGMC02,
author = {Vikram Iyengar and
Sandeep Kumar Goel and
Erik Jan Marinissen and
Krishnendu Chakrabarty},
title = {Test Resource Optimization for Multi-Site Testing of SOCs Under {ATE}
Memory Depth Constraints},
booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore,
MD, USA, October 7-10, 2002},
pages = {1159--1168},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/TEST.2002.1041874},
doi = {10.1109/TEST.2002.1041874},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/IyengarGMC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/IyengarCM02,
author = {Vikram Iyengar and
Krishnendu Chakrabarty and
Erik Jan Marinissen},
title = {On Using Rectangle Packing for {SOC} Wrapper/TAM Co-Optimization},
booktitle = {20th {IEEE} {VLSI} Test Symposium {(VTS} 2002), Without Testing It's
a Gamble, 28 April - 2 May 2002, Monterey, CA, {USA}},
pages = {253--258},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/VTS.2002.1011146},
doi = {10.1109/VTS.2002.1011146},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/IyengarCM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/IyengarCM01,
author = {Vikram Iyengar and
Krishnendu Chakrabarty and
Erik Jan Marinissen},
title = {Test wrapper and test access mechanism co-optimization for system-on-chip},
booktitle = {Proceedings {IEEE} International Test Conference 2001, Baltimore,
MD, USA, 30 October - 1 November 2001},
pages = {1023--1032},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/TEST.2001.966728},
doi = {10.1109/TEST.2001.966728},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/IyengarCM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/IyengarC01,
author = {Vikram Iyengar and
Krishnendu Chakrabarty},
title = {Precedence-Based, Preemptive, and Power-Constrained Test Scheduling
for System-on-a-Chip},
booktitle = {19th {IEEE} {VLSI} Test Symposium {(VTS} 2001), Test and Diagnosis
in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA,
{USA}},
pages = {368--374},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/VTS.2001.923464},
doi = {10.1109/VTS.2001.923464},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/IyengarC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/ChangIR00,
author = {Ta{-}Chung Chang and
Vikram Iyengar and
Elizabeth M. Rudnick},
title = {A Biased Random Instruction Generation Environment for Architectural
Verification of Pipelined Processors},
journal = {J. Electron. Test.},
volume = {16},
number = {1-2},
pages = {13--27},
year = {2000},
url = {https://doi.org/10.1023/A:1008311916502},
doi = {10.1023/A:1008311916502},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/ChangIR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChakrabartyMI00,
author = {Krishnendu Chakrabarty and
Brian T. Murray and
Vikram Iyengar},
title = {Deterministic built-in test pattern generation for high-performance
circuits using twisted-ring counters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {8},
number = {5},
pages = {633--636},
year = {2000},
url = {https://doi.org/10.1109/92.894170},
doi = {10.1109/92.894170},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabartyMI00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdpta/DateICS00,
author = {Hiroshi Date and
Vikram Iyengar and
Krishnendu Chakrabarty and
Makoto Sugihara},
editor = {Hamid R. Arabnia},
title = {Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable
Cores},
booktitle = {Proceedings of the International Conference on Parallel and Distributed
Processing Techniques and Applications, {PDPTA} 2000, June 24-29,
2000, Las Vegas, Nevada, {USA}},
publisher = {{CSREA} Press},
year = {2000},
timestamp = {Mon, 08 Dec 2003 16:35:08 +0100},
biburl = {https://dblp.org/rec/conf/pdpta/DateICS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/IyengarCM99,
author = {Vikram Iyengar and
Krishnendu Chakrabarty and
Brian T. Murray},
title = {Deterministic Built-in Pattern Generation for Sequential Circuits},
journal = {J. Electron. Test.},
volume = {15},
number = {1-2},
pages = {97--114},
year = {1999},
url = {https://doi.org/10.1023/A:1008384201996},
doi = {10.1023/A:1008384201996},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/et/IyengarCM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/ChakrabartyMI99,
author = {Krishnendu Chakrabarty and
Brian T. Murray and
Vikram Iyengar},
title = {Built-in Test Pattern Generation For High-Performance Cir cuits Using
Twisted-Ring Counters},
booktitle = {17th {IEEE} {VLSI} Test Symposium {(VTS} '99), 25-30 April 1999, San
Diego, CA, {USA}},
pages = {22--27},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/VTEST.1999.766642},
doi = {10.1109/VTEST.1999.766642},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/ChakrabartyMI99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/vlsi/IyengarR99,
author = {Vikram Iyengar and
Elizabeth M. Rudnick},
editor = {Wai{-}Kai Chen},
title = {Microprocessor Design Verification},
booktitle = {The {VLSI} Handbook},
publisher = {{CRC} Press},
year = {1999},
url = {https://doi.org/10.1201/9781420049671.ch61},
doi = {10.1201/9781420049671.CH61},
timestamp = {Wed, 12 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/reference/vlsi/IyengarR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tim/IyengarCM98,
author = {Vikram Iyengar and
Krishnendu Chakrabarty and
Brian T. Murray},
title = {Huffman encoding of test sets for sequential circuits},
journal = {{IEEE} Trans. Instrum. Meas.},
volume = {47},
number = {1},
pages = {21--25},
year = {1998},
url = {https://doi.org/10.1109/19.728782},
doi = {10.1109/19.728782},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tim/IyengarCM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/IyengarCM98,
author = {Vikram Iyengar and
Krishnendu Chakrabarty and
Brian T. Murray},
title = {Built-In Self Testing of Sequential Circuits Using Precomputed Test
Sets},
booktitle = {16th {IEEE} {VLSI} Test Symposium {(VTS} '98), 28 April - 1 May 1998,
Princeton, NJ, {USA}},
pages = {418--423},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/VTEST.1998.670900},
doi = {10.1109/VTEST.1998.670900},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/IyengarCM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipl/IyengarC97,
author = {Vikram Iyengar and
Krishnendu Chakrabarty},
title = {An Efficient Finite-State Machine Implementation of Huffman Decoders},
journal = {Inf. Process. Lett.},
volume = {64},
number = {6},
pages = {271--275},
year = {1997},
url = {https://doi.org/10.1016/S0020-0190(97)00176-2},
doi = {10.1016/S0020-0190(97)00176-2},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipl/IyengarC97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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