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ORCIDBibTeX records: Andreas Gerstlauer
@article{DBLP:journals/tecs/IyerTOGY24,
author = {Vishnuvardhan V. Iyer and
Aditya Thimmaiah and
Michael Orshansky and
Andreas Gerstlauer and
Ali E. Yilmaz},
title = {A Hierarchical Classification Method for High-accuracy Instruction
Disassembly with Near-field {EM} Measurements},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {23},
number = {1},
pages = {10:1--10:21},
year = {2024},
url = {https://doi.org/10.1145/3629167},
doi = {10.1145/3629167},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tecs/IyerTOGY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/KumarAAG23,
author = {Ajay Krishna Ananda Kumar and
Sami Alsalamin and
Hussam Amrouch and
Andreas Gerstlauer},
title = {Machine Learning-Based Microarchitecture- Level Power Modeling of
CPUs},
journal = {{IEEE} Trans. Computers},
volume = {72},
number = {4},
pages = {941--956},
year = {2023},
url = {https://doi.org/10.1109/TC.2022.3185572},
doi = {10.1109/TC.2022.3185572},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/KumarAAG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LozanoG23,
author = {Erika Susana Alcorta Lozano and
Andreas Gerstlauer},
title = {Learning-based Phase-aware Multi-core {CPU} Workload Forecasting},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {28},
number = {2},
pages = {23:1--23:27},
year = {2023},
url = {https://doi.org/10.1145/3564929},
doi = {10.1145/3564929},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/LozanoG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/GourounasHFTJG23,
author = {Dimitrios Gourounas and
Bagus Hanindhito and
Arash Fathi and
Dimitar Trenev and
Lizy K. John and
Andreas Gerstlauer},
title = {{FAWS:} {FPGA} Acceleration of Large-Scale Wave Simulations},
booktitle = {34th {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2023, Porto, Portugal, July 19-21,
2023},
pages = {76--84},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ASAP57973.2023.00025},
doi = {10.1109/ASAP57973.2023.00025},
timestamp = {Thu, 19 Oct 2023 20:45:03 +0200},
biburl = {https://dblp.org/rec/conf/asap/GourounasHFTJG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codesisss/AlcortaGDSZXWLEGH23,
author = {Erika S. Alcorta and
Andreas Gerstlauer and
Chenhui Deng and
Qi Sun and
Zhiru Zhang and
Ceyu Xu and
Lisa Wu Wills and
Daniela Sanchez Lopera and
Wolfgang Ecker and
Siddharth Garg and
Jiang Hu},
title = {Special Session: Machine Learning for Embedded System Design},
booktitle = {International Conference on Hardware/Software Codesign and System
Synthesis, {CODES+ISSS} 2023, Hamburg, Germany, September 17-22, 2023},
pages = {28--37},
publisher = {{IEEE}},
year = {2023},
url = {https://ieeexplore.ieee.org/document/10317830},
timestamp = {Tue, 05 Dec 2023 20:47:36 +0100},
biburl = {https://dblp.org/rec/conf/codesisss/AlcortaGDSZXWLEGH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ecrts/SaeedHDZMSG023,
author = {Ahsan Saeed and
Denis Hoornaert and
Dakshina Dasari and
Dirk Ziegenbein and
Daniel Mueller{-}Gritschneder and
Ulf Schlichtmann and
Andreas Gerstlauer and
Renato Mancuso},
editor = {Alessandro V. Papadopoulos},
title = {Memory Latency Distribution-Driven Regulation for Temporal Isolation
in MPSoCs},
booktitle = {35th Euromicro Conference on Real-Time Systems, {ECRTS} 2023, July
11-14, 2023, Vienna, Austria},
series = {LIPIcs},
volume = {262},
pages = {4:1--4:23},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik},
year = {2023},
url = {https://doi.org/10.4230/LIPIcs.ECRTS.2023.4},
doi = {10.4230/LIPICS.ECRTS.2023.4},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ecrts/SaeedHDZMSG023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GourounasHFTJG23,
author = {Dimitrios Gourounas and
Bagus Hanindhito and
Arash Fathi and
Dimitar Trenev and
Lizy Kurian John and
Andreas Gerstlauer},
editor = {Paolo Ienne and
Zhiru Zhang},
title = {{LAWS:} Large-Scale Accelerated Wave Simulations on FPGAs},
booktitle = {Proceedings of the 2023 {ACM/SIGDA} International Symposium on Field
Programmable Gate Arrays, {FPGA} 2023, Monterey, CA, USA, February
12-14, 2023},
pages = {230},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3543622.3573160},
doi = {10.1145/3543622.3573160},
timestamp = {Sat, 25 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/GourounasHFTJG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icons2/BoylePCCG23,
author = {James A. Boyle and
Mark Plagge and
Suma George Cardwell and
Frances S. Chance and
Andreas Gerstlauer},
editor = {Catherine D. Schuman and
Melika Payvand and
Maryam Parsa},
title = {Performance and Energy Simulation of Spiking Neuromorphic Architectures
for Fast Exploration},
booktitle = {Proceedings of the 2023 International Conference on Neuromorphic Systems,
{ICONS} 2023, Santa Fe, NM, USA, August 1-3, 2023},
pages = {19:1--19:4},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3589737.3605970},
doi = {10.1145/3589737.3605970},
timestamp = {Mon, 04 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icons2/BoylePCCG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2307-08635,
author = {Erika S. Alcorta and
Mahesh Madhav and
Scott Tetrick and
Neeraja J. Yadwadkar and
Andreas Gerstlauer},
title = {Lightweight ML-based Runtime Prefetcher Selection on Many-core Platforms},
journal = {CoRR},
volume = {abs/2307.08635},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2307.08635},
doi = {10.48550/ARXIV.2307.08635},
eprinttype = {arXiv},
eprint = {2307.08635},
timestamp = {Tue, 25 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2307-08635.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/GerstlauerS22,
author = {Andreas Gerstlauer and
Aviral Shrivastava},
title = {Report on the 2021 Embedded Systems Week {(ESWEEK)}},
journal = {{IEEE} Des. Test},
volume = {39},
number = {1},
pages = {94--96},
year = {2022},
url = {https://doi.org/10.1109/MDAT.2021.3124759},
doi = {10.1109/MDAT.2021.3124759},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/GerstlauerS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AsriG22,
author = {Mochamad Asri and
Andreas Gerstlauer},
title = {CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous
System Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {11},
pages = {4325--4336},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2022.3197535},
doi = {10.1109/TCAD.2022.3197535},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/AsriG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/SantiagoJAGLH22,
author = {Francisco Javier Hernandez Santiago and
Honglan Jiang and
Hussam Amrouch and
Andreas Gerstlauer and
Leibo Liu and
Jie Han},
title = {Characterizing Approximate Adders and Multipliers for Mitigating Aging
and Temperature Degradations},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {69},
number = {11},
pages = {4558--4571},
year = {2022},
url = {https://doi.org/10.1109/TCSI.2022.3193928},
doi = {10.1109/TCSI.2022.3193928},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcasI/SantiagoJAGLH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/AlaghiDGS22,
author = {Armin Alaghi and
Eva Darulova and
Andreas Gerstlauer and
Phillip Stanley{-}Marbell},
title = {Introduction to the Special Issue on Approximate Systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {27},
number = {2},
pages = {10:1--10:2},
year = {2022},
url = {https://doi.org/10.1145/3488726},
doi = {10.1145/3488726},
timestamp = {Sat, 26 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/AlaghiDGS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ics/HanindhitoGFTGJ22,
author = {Bagus Hanindhito and
Dimitrios Gourounas and
Arash Fathi and
Dimitar Trenev and
Andreas Gerstlauer and
Lizy K. John},
editor = {Lawrence Rauchwerger and
Kirk W. Cameron and
Dimitrios S. Nikolopoulos and
Dionisios N. Pnevmatikatos},
title = {{GAPS:} GPU-acceleration of {PDE} solvers for wave simulation},
booktitle = {{ICS} '22: 2022 International Conference on Supercomputing, Virtual
Event, June 28 - 30, 2022},
pages = {30:1--30:13},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3524059.3532373},
doi = {10.1145/3524059.3532373},
timestamp = {Wed, 22 Jun 2022 13:49:53 +0200},
biburl = {https://dblp.org/rec/conf/ics/HanindhitoGFTGJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iess/FarleyG22,
author = {Jackson Farley and
Andreas Gerstlauer},
editor = {Stefan Henkler and
M{\'{a}}rcio Eduardo Kreutz and
Marco A. Wehrmeister and
Marcelo G{\"{o}}tz and
Achim Rettberg},
title = {{MAFAT:} Memory-Aware Fusing and Tiling of Neural Networks for Accelerated
Edge Inference},
booktitle = {Designing Modern Embedded Systems: Software, Hardware, and Applications
- 7th {IFIP} {TC} 10 International Embedded Systems Symposium, {IESS}
2022, Lippstadt, Germany, November 3-4, 2022, Proceedings},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {669},
pages = {78--88},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-34214-1\_7},
doi = {10.1007/978-3-031-34214-1\_7},
timestamp = {Tue, 13 Jun 2023 16:03:31 +0200},
biburl = {https://dblp.org/rec/conf/iess/FarleyG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtas/SaeedDZRRPHMGS22,
author = {Ahsan Saeed and
Dakshina Dasari and
Dirk Ziegenbein and
Varun Rajasekaran and
Falk Rehm and
Michael Pressler and
Arne Hamann and
Daniel Mueller{-}Gritschneder and
Andreas Gerstlauer and
Ulf Schlichtmann},
title = {Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal
Isolation in Multi-Cores},
booktitle = {28th {IEEE} Real-Time and Embedded Technology and Applications Symposium,
{RTAS} 2022, Milano, Italy, May 4-6, 2022},
pages = {133--145},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/RTAS54340.2022.00019},
doi = {10.1109/RTAS54340.2022.00019},
timestamp = {Mon, 04 Jul 2022 17:06:22 +0200},
biburl = {https://dblp.org/rec/conf/rtas/SaeedDZRRPHMGS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/ThimmaiahIGO22,
author = {Aditya Thimmaiah and
Vishnuvardhan V. Iyer and
Andreas Gerstlauer and
Michael Orshansky},
editor = {Alex Orailoglu and
Marc Reichenbach and
Matthias Jung},
title = {High-Level Simulation of Embedded Software Vulnerabilities to {EM}
Side-Channel Attacks},
booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation
- 22nd International Conference, {SAMOS} 2022, Samos, Greece, July
3-7, 2022, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {13511},
pages = {155--170},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-15074-6\_10},
doi = {10.1007/978-3-031-15074-6\_10},
timestamp = {Fri, 19 Aug 2022 08:42:32 +0200},
biburl = {https://dblp.org/rec/conf/samos/ThimmaiahIGO22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/csur/Stanley-Marbell20,
author = {Phillip Stanley{-}Marbell and
Armin Alaghi and
Michael Carbin and
Eva Darulova and
Lara Dolecek and
Andreas Gerstlauer and
Ghayoor Gillani and
Djordje Jevdjic and
Thierry Moreau and
Mattia Cacciotti and
Alexandros Daglis and
Natalie D. Enright Jerger and
Babak Falsafi and
Sasa Misailovic and
Adrian Sampson and
Damien Zufferey},
title = {Exploiting Errors for Efficiency: {A} Survey from Circuits to Applications},
journal = {{ACM} Comput. Surv.},
volume = {53},
number = {3},
pages = {51:1--51:39},
year = {2021},
url = {https://doi.org/10.1145/3394898},
doi = {10.1145/3394898},
timestamp = {Wed, 23 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/csur/Stanley-Marbell20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/MitraG21,
author = {Tulika Mitra and
Andreas Gerstlauer},
title = {Report on the 2020 Embedded Systems Week {(ESWEEK):} {A} Virtual Event
during a Pandemic, September 20-25},
journal = {{IEEE} Des. Test},
volume = {38},
number = {1},
pages = {79--80},
year = {2021},
url = {https://doi.org/10.1109/MDAT.2020.3036595},
doi = {10.1109/MDAT.2020.3036595},
timestamp = {Tue, 23 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/MitraG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/StahlHMGS21,
author = {Rafael Stahl and
Alexander Hoffman and
Daniel Mueller{-}Gritschneder and
Andreas Gerstlauer and
Ulf Schlichtmann},
title = {DeeperThings: Fully Distributed {CNN} Inference on Resource-Constrained
Edge Devices},
journal = {Int. J. Parallel Program.},
volume = {49},
number = {4},
pages = {600--624},
year = {2021},
url = {https://doi.org/10.1007/s10766-021-00712-3},
doi = {10.1007/S10766-021-00712-3},
timestamp = {Thu, 29 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijpp/StahlHMGS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/AydinATGO21,
author = {Furkan Aydin and
Aydin Aysu and
Mohit Tiwari and
Andreas Gerstlauer and
Michael Orshansky},
title = {Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange
and Encapsulation Protocols},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {20},
number = {6},
pages = {110:1--110:22},
year = {2021},
url = {https://doi.org/10.1145/3476799},
doi = {10.1145/3476799},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/AydinATGO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/AsriMWBJG21,
author = {Mochamad Asri and
Dhairya Malhotra and
Jiajun Wang and
George Biros and
Lizy K. John and
Andreas Gerstlauer},
title = {Hardware Accelerator Integration Tradeoffs for High-Performance Computing:
{A} Case Study of {GEMM} Acceleration in N-Body Methods},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {32},
number = {8},
pages = {2035--2048},
year = {2021},
url = {https://doi.org/10.1109/TPDS.2021.3056045},
doi = {10.1109/TPDS.2021.3056045},
timestamp = {Tue, 23 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tpds/AsriMWBJG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlanGH21,
author = {Tanfer Alan and
Andreas Gerstlauer and
J{\"{o}}rg Henkel},
title = {Cross-Layer Approximate Hardware Synthesis for Runtime Configurable
Accuracy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1231--1243},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3068312},
doi = {10.1109/TVLSI.2021.3068312},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AlanGH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZervakisSAGPH21,
author = {Georgios Zervakis and
Hassaan Saadat and
Hussam Amrouch and
Andreas Gerstlauer and
Sri Parameswaran and
J{\"{o}}rg Henkel},
title = {Approximate Computing for {ML:} State-of-the-art, Challenges and Visions},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {189--196},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431632},
doi = {10.1145/3394885.3431632},
timestamp = {Wed, 06 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ZervakisSAGPH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/HanindhitoLGFGT21,
author = {Bagus Hanindhito and
Ruihao Li and
Dimitrios Gourounas and
Arash Fathi and
Karan Govil and
Dimitar Trenev and
Andreas Gerstlauer and
Lizy Kurian John},
editor = {Xian{-}He Sun and
Sameer Shende and
Laxmikant V. Kal{\'{e}} and
Yong Chen},
title = {Wave-PIM: Accelerating Wave Simulation Using Processing-in-Memory},
booktitle = {{ICPP} 2021: 50th International Conference on Parallel Processing,
Lemont, IL, USA, August 9 - 12, 2021},
pages = {8:1--8:11},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3472456.3472512},
doi = {10.1145/3472456.3472512},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icpp/HanindhitoLGFGT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/WuBEGJ21,
author = {Qinzhe Wu and
Jonathan Beard and
Ashen Ekanayake and
Andreas Gerstlauer and
Lizy K. John},
title = {Virtual-Link: {A} Scalable Multi-Producer Multi-Consumer Message Queue
Architecture for Cross-Core Communication},
booktitle = {35th {IEEE} International Parallel and Distributed Processing Symposium,
{IPDPS} 2021, Portland, OR, USA, May 17-21, 2021},
pages = {182--191},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/IPDPS49936.2021.00027},
doi = {10.1109/IPDPS49936.2021.00027},
timestamp = {Fri, 02 Jul 2021 14:10:24 +0200},
biburl = {https://dblp.org/rec/conf/ipps/WuBEGJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mlcad/AlcortaG21,
author = {Erika S. Alcorta and
Andreas Gerstlauer},
title = {Learning-Based Workload Phase Classification and Prediction Using
Performance Monitoring Counters},
booktitle = {3rd {ACM/IEEE} Workshop on Machine Learning for CAD, {MLCAD} 2021,
Raleigh, NC, USA, August 30 - Sept. 3, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MLCAD52597.2021.9531161},
doi = {10.1109/MLCAD52597.2021.9531161},
timestamp = {Fri, 17 Sep 2021 14:46:40 +0200},
biburl = {https://dblp.org/rec/conf/mlcad/AlcortaG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mlcad/SaeedMRHZSG21,
author = {Ahsan Saeed and
Daniel Mueller{-}Gritschneder and
Falk Rehm and
Arne Hamann and
Dirk Ziegenbein and
Ulf Schlichtmann and
Andreas Gerstlauer},
title = {Learning based Memory Interference Prediction for Co-running Applications
on Multi-Cores},
booktitle = {3rd {ACM/IEEE} Workshop on Machine Learning for CAD, {MLCAD} 2021,
Raleigh, NC, USA, August 30 - Sept. 3, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MLCAD52597.2021.9531245},
doi = {10.1109/MLCAD52597.2021.9531245},
timestamp = {Fri, 17 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mlcad/SaeedMRHZSG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/AlcortaRRG21,
author = {Erika S. Alcorta and
Pranav Rama and
Aswin Ramachandran and
Andreas Gerstlauer},
editor = {Alex Orailoglu and
Matthias Jung and
Marc Reichenbach},
title = {Phase-Aware {CPU} Workload Forecasting},
booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation
- 21st International Conference, {SAMOS} 2021, Virtual Event, July
4-8, 2021, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {13227},
pages = {195--209},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-031-04580-6\_13},
doi = {10.1007/978-3-031-04580-6\_13},
timestamp = {Fri, 29 Apr 2022 14:50:40 +0200},
biburl = {https://dblp.org/rec/conf/samos/AlcortaRRG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2107-06960,
author = {Jackson Farley and
Andreas Gerstlauer},
title = {Memory-Aware Fusing and Tiling of Neural Networks for Accelerated
Edge Inference},
journal = {CoRR},
volume = {abs/2107.06960},
year = {2021},
url = {https://arxiv.org/abs/2107.06960},
eprinttype = {arXiv},
eprint = {2107.06960},
timestamp = {Wed, 21 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2107-06960.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dagstuhl-reports/DarulovaFGS21,
author = {Eva Darulova and
Babak Falsafi and
Andreas Gerstlauer and
Phillip Stanley{-}Marbell},
title = {Approximate Systems (Dagstuhl Seminar 21302)},
journal = {Dagstuhl Reports},
volume = {11},
number = {6},
pages = {147--163},
year = {2021},
url = {https://doi.org/10.4230/DagRep.11.6.147},
doi = {10.4230/DAGREP.11.6.147},
timestamp = {Mon, 06 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dagstuhl-reports/DarulovaFGS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SalaminRHGA20,
author = {Sami Salamin and
Martin Rapp and
J{\"{o}}rg Henkel and
Andreas Gerstlauer and
Hussam Amrouch},
title = {Dynamic Power and Energy Management for NCFET-Based Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {11},
pages = {3361--3372},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2020.3012644},
doi = {10.1109/TCAD.2020.3012644},
timestamp = {Thu, 17 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SalaminRHGA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KimKAHGCP20,
author = {Heesu Kim and
Jongho Kim and
Hussam Amrouch and
J{\"{o}}rg Henkel and
Andreas Gerstlauer and
Kiyoung Choi and
Hanmin Park},
title = {Aging Compensation With Dynamic Computation Approximation},
journal = {{IEEE} Trans. Circuits Syst. {I} Fundam. Theory Appl.},
volume = {67-I},
number = {4},
pages = {1319--1332},
year = {2020},
url = {https://doi.org/10.1109/TCSI.2020.2969462},
doi = {10.1109/TCSI.2020.2969462},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/KimKAHGCP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/ZhaoBG20,
author = {Zhuoran Zhao and
Kamyar Mirzazad Barijough and
Andreas Gerstlauer},
title = {Network-level Design Space Exploration of Resource-constrained Networks-of-Systems},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {19},
number = {4},
pages = {22:1--22:26},
year = {2020},
url = {https://doi.org/10.1145/3387918},
doi = {10.1145/3387918},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/ZhaoBG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEpact/PunniyamurthyG20,
author = {Kishore Punniyamurthy and
Andreas Gerstlauer},
editor = {Vivek Sarkar and
Hyesoon Kim},
title = {{TAFE:} Thread Address Footprint Estimation for Capturing Data/Thread
Locality in {GPU} Systems},
booktitle = {{PACT} '20: International Conference on Parallel Architectures and
Compilation Techniques, Virtual Event, GA, USA, October 3-7, 2020},
pages = {17--29},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3410463.3414641},
doi = {10.1145/3410463.3414641},
timestamp = {Fri, 23 Oct 2020 10:46:26 +0200},
biburl = {https://dblp.org/rec/conf/IEEEpact/PunniyamurthyG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SalaminRAGH20,
author = {Sami Salamin and
Martin Rapp and
Hussam Amrouch and
Andreas Gerstlauer and
J{\"{o}}rg Henkel},
title = {Energy Optimization in NCFET-based Processors},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2020, Grenoble, France, March 9-13, 2020},
pages = {630--633},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.23919/DATE48585.2020.9116301},
doi = {10.23919/DATE48585.2020.9116301},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/SalaminRAGH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/AlanGH20,
author = {Tanfer Alan and
Andreas Gerstlauer and
J{\"{o}}rg Henkel},
title = {Runtime Accuracy-Configurable Approximate Hardware Synthesis Using
Logic Gating and Relaxation},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2020, Grenoble, France, March 9-13, 2020},
pages = {1578--1581},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.23919/DATE48585.2020.9116272},
doi = {10.23919/DATE48585.2020.9116272},
timestamp = {Thu, 25 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/AlanGH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdp/AsriDRGB20,
author = {Mochamad Asri and
Curtis Dunham and
Roxana Rusitoru and
Andreas Gerstlauer and
Jonathan Beard},
title = {The Non-Uniform Compute Device {(NUCD)} Architecture for Lightweight
Accelerator Offload},
booktitle = {28th Euromicro International Conference on Parallel, Distributed and
Network-Based Processing, {PDP} 2020, V{\"{a}}ster{\aa}s, Sweden,
March 11-13, 2020},
pages = {38--45},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/PDP50117.2020.00013},
doi = {10.1109/PDP50117.2020.00013},
timestamp = {Tue, 19 May 2020 14:16:27 +0200},
biburl = {https://dblp.org/rec/conf/pdp/AsriDRGB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdp/PunniyamurthyG20,
author = {Kishore Punniyamurthy and
Andreas Gerstlauer},
title = {Off-Chip Congestion Management for GPU-based Non-Uniform Processing-in-Memory
Networks},
booktitle = {28th Euromicro International Conference on Parallel, Distributed and
Network-Based Processing, {PDP} 2020, V{\"{a}}ster{\aa}s, Sweden,
March 11-13, 2020},
pages = {282--289},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/PDP50117.2020.00050},
doi = {10.1109/PDP50117.2020.00050},
timestamp = {Tue, 19 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/pdp/PunniyamurthyG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PunniyamurthyDG20,
author = {Kishore Punniyamurthy and
Shomit Das and
Andreas Gerstlauer},
title = {Cacheline Utilization-Aware Link Traffic Compression for Modular GPUs},
booktitle = {33rd International Conference on {VLSI} Design and 19th International
Conference on Embedded Systems, {VLSID} 2020, Bangalore, India, January
4-8, 2020},
pages = {137--142},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSID49098.2020.00041},
doi = {10.1109/VLSID49098.2020.00041},
timestamp = {Mon, 14 Nov 2022 15:28:08 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PunniyamurthyDG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/cases/2020,
editor = {Tulika Mitra and
Andreas Gerstlauer},
title = {International Conference on Compilers, Architecture, and Synthesis
for Embedded Systems, {CASES} 2020, Singapore, September 20-25, 2020},
publisher = {{IEEE}},
year = {2020},
url = {https://ieeexplore.ieee.org/xpl/conhome/9243670/proceeding},
isbn = {978-1-7281-9192-8},
timestamp = {Tue, 10 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/2020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/emsoft/2020,
editor = {Tulika Mitra and
Andreas Gerstlauer},
title = {20th International Conference on Embedded Software, {EMSOFT} 2020,
Singapore, September 20-25, 2020},
publisher = {{IEEE}},
year = {2020},
url = {https://ieeexplore.ieee.org/xpl/conhome/9243930/proceeding},
isbn = {978-1-7281-9195-9},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/emsoft/2020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2012-05181,
author = {Qinzhe Wu and
Jonathan Beard and
Ashen Ekanayake and
Andreas Gerstlauer and
Lizy K. John},
title = {Virtual-Link: {A} Scalable Multi-Producer, Multi-Consumer Message
Queue Architecture for Cross-Core Communication},
journal = {CoRR},
volume = {abs/2012.05181},
year = {2020},
url = {https://arxiv.org/abs/2012.05181},
eprinttype = {arXiv},
eprint = {2012.05181},
timestamp = {Sat, 02 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2012-05181.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/AmrouchEGH19,
author = {Hussam Amrouch and
Seyed Borna Ehsani and
Andreas Gerstlauer and
J{\"{o}}rg Henkel},
title = {On the Efficiency of Voltage Overscaling under Temperature and Aging
Effects},
journal = {{IEEE} Trans. Computers},
volume = {68},
number = {11},
pages = {1647--1662},
year = {2019},
url = {https://doi.org/10.1109/TC.2019.2916869},
doi = {10.1109/TC.2019.2916869},
timestamp = {Thu, 07 Nov 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/AmrouchEGH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/BarijoughZG19,
author = {Kamyar Mirzazad Barijough and
Zhuoran Zhao and
Andreas Gerstlauer},
title = {Quality/Latency-Aware Real-time Scheduling of Distributed Streaming
IoT Applications},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {18},
number = {5s},
pages = {83:1--83:23},
year = {2019},
url = {https://doi.org/10.1145/3358209},
doi = {10.1145/3358209},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/BarijoughZG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/host/WeiAOGT19,
author = {Shijia Wei and
Aydin Aysu and
Michael Orshansky and
Andreas Gerstlauer and
Mohit Tiwari},
title = {Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks
in Embedded Systems},
booktitle = {{IEEE} International Symposium on Hardware Oriented Security and Trust,
{HOST} 2019, McLean, VA, USA, May 5-10, 2019},
pages = {111--120},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/HST.2019.8740838},
doi = {10.1109/HST.2019.8740838},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/host/WeiAOGT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KimKAHGC19,
author = {Jongho Kim and
Heesu Kim and
Hussam Amrouch and
J{\"{o}}rg Henkel and
Andreas Gerstlauer and
Kiyoung Choi},
title = {Aging Gracefully with Approximation},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702120},
doi = {10.1109/ISCAS.2019.8702120},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KimKAHGC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/StahlZMGS19,
author = {Rafael Stahl and
Zhuoran Zhao and
Daniel Mueller{-}Gritschneder and
Andreas Gerstlauer and
Ulf Schlichtmann},
editor = {Dionisios N. Pnevmatikatos and
Maxime Pelcat and
Matthias Jung},
title = {Fully Distributed Deep Learning Inference on Resource-Constrained
Edge Devices},
booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation
- 19th International Conference, {SAMOS} 2019, Samos, Greece, July
7-11, 2019, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {11733},
pages = {77--90},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-27562-4\_6},
doi = {10.1007/978-3-030-27562-4\_6},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/samos/StahlZMGS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/syscon/AbdelhadiGV19,
author = {Ahmed Abdelhadi and
Andreas Gerstlauer and
Sriram Vishwanath},
title = {Real-Time Rate Distortion Optimized and Adaptive Low Complexity Algorithms
for Video Streaming},
booktitle = {2019 {IEEE} International Systems Conference, SysCon 2019, Orlando,
FL, USA, April 8-11, 2019},
pages = {1--8},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SYSCON.2019.8836788},
doi = {10.1109/SYSCON.2019.8836788},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/syscon/AbdelhadiGV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/syscon/AbdelhadiGV19a,
author = {Ahmed Abdelhadi and
Andreas Gerstlauer and
Sriram Vishwanath},
title = {Horus Testbed: Implementation of Real-Time Video Streaming Protocols},
booktitle = {2019 {IEEE} International Systems Conference, SysCon 2019, Orlando,
FL, USA, April 8-11, 2019},
pages = {1--8},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SYSCON.2019.8836840},
doi = {10.1109/SYSCON.2019.8836840},
timestamp = {Mon, 23 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/syscon/AbdelhadiGV19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wosp/WhitehouseWSJGJ19,
author = {Joseph Whitehouse and
Qinzhe Wu and
Shuang Song and
Eugene John and
Andreas Gerstlauer and
Lizy K. John},
editor = {Varsha Apte and
Antinisca Di Marco and
Marin Litoiu and
Jos{\'{e}} Merseguer},
title = {A Study of Core Utilization and Residency in Heterogeneous Smart Phone
Architectures},
booktitle = {Proceedings of the 2019 {ACM/SPEC} International Conference on Performance
Engineering, {ICPE} 2019, Mumbai, India, April 7-11, 2019},
pages = {67--78},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3297663.3310304},
doi = {10.1145/3297663.3310304},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/wosp/WhitehouseWSJGJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/19/LeeG19,
author = {Seogoo Lee and
Andreas Gerstlauer},
editor = {Sherief Reda and
Muhammad Shafique},
title = {Approximate High-Level Synthesis of Custom Hardware},
booktitle = {Approximate Circuits, Methodologies and {CAD}},
pages = {205--223},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-319-99322-5\_10},
doi = {10.1007/978-3-319-99322-5\_10},
timestamp = {Sun, 02 Feb 2020 18:57:32 +0100},
biburl = {https://dblp.org/rec/books/sp/19/LeeG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/LeeG18,
author = {Seogoo Lee and
Andreas Gerstlauer},
title = {Data-Dependent Loop Approximations for Performance-Quality Driven
High-Level Synthesis},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {10},
number = {1},
pages = {18--21},
year = {2018},
url = {https://doi.org/10.1109/LES.2017.2764542},
doi = {10.1109/LES.2017.2764542},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/LeeG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pvldb/SongLWGLJ18,
author = {Shuang Song and
Xu Liu and
Qinzhe Wu and
Andreas Gerstlauer and
Tao Li and
Lizy K. John},
title = {Start Late or Finish Early: {A} Distributed Graph Processing System
with Redundancy Reduction},
journal = {Proc. {VLDB} Endow.},
volume = {12},
number = {2},
pages = {154--168},
year = {2018},
url = {http://www.vldb.org/pvldb/vol12/p154-song.pdf},
doi = {10.14778/3282495.3282501},
timestamp = {Mon, 03 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/pvldb/SongLWGLJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoBG18,
author = {Zhuoran Zhao and
Kamyar Mirzazad Barijough and
Andreas Gerstlauer},
title = {DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained
IoT Edge Clusters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2348--2359},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858384},
doi = {10.1109/TCAD.2018.2858384},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoBG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LeeG18,
author = {Dongwook Lee and
Andreas Gerstlauer},
title = {Learning-Based, Fine-Grain Power Modeling of System-Level Hardware
IPs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {23},
number = {3},
pages = {30:1--30:25},
year = {2018},
url = {https://doi.org/10.1145/3177865},
doi = {10.1145/3177865},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LeeG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LeePSJGJ18,
author = {Wooseok Lee and
Reena Panda and
Dam Sunwoo and
Jos{\'{e}} A. Joao and
Andreas Gerstlauer and
Lizy K. John},
editor = {Youngsoo Shin},
title = {{BUQS:} Battery- and user-aware QoS scaling for interactive mobile
devices},
booktitle = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2018, Jeju, Korea (South), January 22-25, 2018},
pages = {64--69},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASPDAC.2018.8297284},
doi = {10.1109/ASPDAC.2018.8297284},
timestamp = {Fri, 24 Jan 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/LeePSJGJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PandaZGJ18,
author = {Reena Panda and
Xinnian Zheng and
Andreas Gerstlauer and
Lizy Kurian John},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {{CAMP:} Accurate modeling of core and memory locality for proxy generation
of big-data applications},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {337--342},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342032},
doi = {10.23919/DATE.2018.8342032},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/PandaZGJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/host/AysuTTGO18,
author = {Aydin Aysu and
Youssef Tobah and
Mohit Tiwari and
Andreas Gerstlauer and
Michael Orshansky},
title = {Horizontal side-channel vulnerabilities of post-quantum key exchange
protocols},
booktitle = {2018 {IEEE} International Symposium on Hardware Oriented Security
and Trust, {HOST} 2018, Washington, DC, USA, April 30 - May 4, 2018},
pages = {81--88},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/HST.2018.8383894},
doi = {10.1109/HST.2018.8383894},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/host/AysuTTGO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/BoroujerdianAHG18,
author = {Behzad Boroujerdian and
Hussam Amrouch and
J{\"{o}}rg Henkel and
Andreas Gerstlauer},
title = {Trading Off Temperature Guardbands via Adaptive Approximations},
booktitle = {36th {IEEE} International Conference on Computer Design, {ICCD} 2018,
Orlando, FL, USA, October 7-10, 2018},
pages = {202--209},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ICCD.2018.00039},
doi = {10.1109/ICCD.2018.00039},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/BoroujerdianAHG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/scopes/YuKG18,
author = {Wenxiao Yu and
Jacob Kornerup and
Andreas Gerstlauer},
editor = {Sander Stuijk},
title = {{MASES:} Mobility And Slack Enhanced Scheduling For Latency-Optimized
Pipelined Dataflow Graphs},
booktitle = {Proceedings of the 21st International Workshop on Software and Compilers
for Embedded Systems, {SCOPES} 2018, Sankt Goar, Germany, May 28-30,
2018},
pages = {104--109},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3207719.3207733},
doi = {10.1145/3207719.3207733},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/scopes/YuKG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1805-12305,
author = {Shuang Song and
Xu Liu and
Qinzhe Wu and
Andreas Gerstlauer and
Tao Li and
Lizy K. John},
title = {Start Late or Finish Early: {A} Distributed Graph Processing System
with Redundancy Reduction},
journal = {CoRR},
volume = {abs/1805.12305},
year = {2018},
url = {http://arxiv.org/abs/1805.12305},
eprinttype = {arXiv},
eprint = {1805.12305},
timestamp = {Mon, 03 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1805-12305.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1809-05859,
author = {Phillip Stanley{-}Marbell and
Armin Alaghi and
Michael Carbin and
Eva Darulova and
Lara Dolecek and
Andreas Gerstlauer and
Ghayoor Gillani and
Djordje Jevdjic and
Thierry Moreau and
Mattia Cacciotti and
Alexandros Daglis and
Natalie D. Enright Jerger and
Babak Falsafi and
Sasa Misailovic and
Adrian Sampson and
Damien Zufferey},
title = {Exploiting Errors for Efficiency: {A} Survey from Circuits to Algorithms},
journal = {CoRR},
volume = {abs/1809.05859},
year = {2018},
url = {http://arxiv.org/abs/1809.05859},
eprinttype = {arXiv},
eprint = {1809.05859},
timestamp = {Fri, 05 Oct 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1809-05859.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/FrancisG17,
author = {Sabine Francis and
Andreas Gerstlauer},
title = {A Reactive and Adaptive Data Flow Model for Network-of-System Specification},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {9},
number = {4},
pages = {121--124},
year = {2017},
url = {https://doi.org/10.1109/LES.2017.2725826},
doi = {10.1109/LES.2017.2725826},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/FrancisG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/VayaG17,
author = {Guillermo Pay{\'{a}} Vay{\'{a}} and
Andreas Gerstlauer},
title = {Guest Editorial: Special Issue on the 2015 International Conference
on Embedded Computer Systems - Architectures, Modeling and Simulation
{(SAMOS} {XV)}},
journal = {Int. J. Parallel Program.},
volume = {45},
number = {6},
pages = {1417--1419},
year = {2017},
url = {https://doi.org/10.1007/s10766-017-0500-7},
doi = {10.1007/S10766-017-0500-7},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijpp/VayaG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijpp/ZhengJG17,
author = {Xinnian Zheng and
Lizy K. John and
Andreas Gerstlauer},
title = {LACross: Learning-Based Analytical Cross-Platform Performance and
Power Prediction},
journal = {Int. J. Parallel Program.},
volume = {45},
number = {6},
pages = {1488--1514},
year = {2017},
url = {https://doi.org/10.1007/s10766-017-0487-0},
doi = {10.1007/S10766-017-0487-0},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijpp/ZhengJG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoGJ17,
author = {Zhuoran Zhao and
Andreas Gerstlauer and
Lizy K. John},
title = {Source-Level Performance, Energy, Reliability, Power and Thermal {(PERPT)}
Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {2},
pages = {299--312},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2016.2578882},
doi = {10.1109/TCAD.2016.2578882},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoGJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/AmrouchKGH17,
author = {Hussam Amrouch and
Behnam Khaleghi and
Andreas Gerstlauer and
J{\"{o}}rg Henkel},
title = {Towards Aging-Induced Approximations},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {41:1--41:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062331},
doi = {10.1145/3061639.3062331},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/AmrouchKGH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PandaZWGJ17,
author = {Reena Panda and
Xinnian Zheng and
Jiajun Wang and
Andreas Gerstlauer and
Lizy K. John},
title = {Statistical Pattern Based Modeling of {GPU} Memory Access Streams},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {81:1--81:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062320},
doi = {10.1145/3061639.3062320},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PandaZWGJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PunniyamurthyBG17,
author = {Kishore Punniyamurthy and
Behzad Boroujerdian and
Andreas Gerstlauer},
editor = {David Atienza and
Giorgio Di Natale},
title = {GATSim: Abstract timing simulation of GPUs},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {43--48},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7926956},
doi = {10.23919/DATE.2017.7926956},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/PunniyamurthyBG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LeeJG17,
author = {Seogoo Lee and
Lizy K. John and
Andreas Gerstlauer},
editor = {David Atienza and
Giorgio Di Natale},
title = {High-level synthesis of approximate hardware under joint precision
and voltage scaling},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {187--192},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7926980},
doi = {10.23919/DATE.2017.7926980},
timestamp = {Mon, 14 Aug 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/LeeJG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ZhengVSJG17,
author = {Xinnian Zheng and
Haris Vikalo and
Shuang Song and
Lizy K. John and
Andreas Gerstlauer},
editor = {David Atienza and
Giorgio Di Natale},
title = {Sampling-based binary-level cross-platform performance estimation},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {1709--1714},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927269},
doi = {10.23919/DATE.2017.7927269},
timestamp = {Mon, 03 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/ZhengVSJG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SongDBSGJ17,
author = {Shuang Song and
Raj Desikan and
Mohamad Barakat and
Sridhar Sundaram and
Andreas Gerstlauer and
Lizy K. John},
editor = {Laleh Behjat and
Jie Han and
Miroslav N. Velev and
Deming Chen},
title = {Fine-Grain Program Snippets Generator for Mobile Core Design},
booktitle = {Proceedings of the on Great Lakes Symposium on {VLSI} 2017, Banff,
AB, Canada, May 10-12, 2017},
pages = {245--250},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3060403.3060439},
doi = {10.1145/3060403.3060439},
timestamp = {Mon, 03 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/SongDBSGJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LeeSEGJ17,
author = {Wooseok Lee and
Dam Sunwoo and
Christopher D. Emmons and
Andreas Gerstlauer and
Lizy K. John},
editor = {Laleh Behjat and
Jie Han and
Miroslav N. Velev and
Deming Chen},
title = {Exploring Heterogeneous-ISA Core Architectures for High-Performance
and Energy-Efficient Mobile SoCs},
booktitle = {Proceedings of the on Great Lakes Symposium on {VLSI} 2017, Banff,
AB, Canada, May 10-12, 2017},
pages = {419--422},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3060403.3060408},
doi = {10.1145/3060403.3060408},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LeeSEGJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/green/GandheJG17,
author = {Maithili P. Gandhe and
Lizy K. John and
Andreas Gerstlauer},
title = {{POWSER:} {A} novel user-experience based power management metric},
booktitle = {Eighth International Green and Sustainable Computing Conference, {IGSC}
2017, Orlando, FL, USA, October 23-25, 2017},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/IGCC.2017.8323606},
doi = {10.1109/IGCC.2017.8323606},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/green/GandheJG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icse/LeeSGJ17,
author = {Wooseok Lee and
Dam Sunwoo and
Andreas Gerstlauer and
Lizy K. John},
title = {Cloud-Guided QoS and Energy Management for Mobile Interactive Web
Applications},
booktitle = {4th {IEEE/ACM} International Conference on Mobile Software Engineering
and Systems, MOBILESoft@ICSE 2017, Buenos Aires, Argentina, May 22-23,
2017},
pages = {25--29},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/MOBILESoft.2017.4},
doi = {10.1109/MOBILESOFT.2017.4},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icse/LeeSGJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/ZhaoTSG17,
author = {Zhuoran Zhao and
Vasileios Tsoutsouras and
Dimitrios Soudris and
Andreas Gerstlauer},
editor = {Yale N. Patt and
S. K. Nandy},
title = {Network/system co-simulation for design space exploration of IoT applications},
booktitle = {2017 International Conference on Embedded Computer Systems: Architectures,
Modeling, and Simulation, {SAMOS} 2017, Pythagorion, Greece, July
17-20, 2017},
pages = {46--53},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/SAMOS.2017.8344610},
doi = {10.1109/SAMOS.2017.8344610},
timestamp = {Tue, 27 Apr 2021 15:13:55 +0200},
biburl = {https://dblp.org/rec/conf/samos/ZhaoTSG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/hwswco/HaTHGMDESGB17,
author = {Soonhoi Ha and
J{\"{u}}rgen Teich and
Christian Haubelt and
Michael Gla{\ss} and
Tulika Mitra and
Rainer D{\"{o}}mer and
Petru Eles and
Aviral Shrivastava and
Andreas Gerstlauer and
Shuvra S. Bhattacharyya},
editor = {Soonhoi Ha and
J{\"{u}}rgen Teich},
title = {Introduction to Hardware/Software Codesign},
booktitle = {Handbook of Hardware/Software Codesign},
pages = {3--26},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-94-017-7267-9\_41},
doi = {10.1007/978-94-017-7267-9\_41},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/reference/hwswco/HaTHGMDESGB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/hwswco/Mueller-GritschnederG17,
author = {Daniel Mueller{-}Gritschneder and
Andreas Gerstlauer},
editor = {Soonhoi Ha and
J{\"{u}}rgen Teich},
title = {Host-Compiled Simulation},
booktitle = {Handbook of Hardware/Software Codesign},
pages = {593--619},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-94-017-7267-9\_18},
doi = {10.1007/978-94-017-7267-9\_18},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/reference/hwswco/Mueller-GritschnederG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/hwswco/SchirnerGD17,
author = {Gunar Schirner and
Andreas Gerstlauer and
Rainer D{\"{o}}mer},
editor = {Soonhoi Ha and
J{\"{u}}rgen Teich},
title = {{SCE:} System-on-Chip Environment},
booktitle = {Handbook of Hardware/Software Codesign},
pages = {1019--1050},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-94-017-7267-9\_31},
doi = {10.1007/978-94-017-7267-9\_31},
timestamp = {Tue, 06 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/reference/hwswco/SchirnerGD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bigdataconf/SongZGJ16,
author = {Shuang Song and
Xinnian Zheng and
Andreas Gerstlauer and
Lizy K. John},
editor = {James Joshi and
George Karypis and
Ling Liu and
Xiaohua Hu and
Ronay Ak and
Yinglong Xia and
Weijia Xu and
Aki{-}Hiro Sato and
Sudarsan Rachuri and
Lyle H. Ungar and
Philip S. Yu and
Rama Govindaraju and
Toyotaro Suzumura},
title = {Fine-grained power analysis of emerging graph processing workloads
for cloud operations management},
booktitle = {2016 {IEEE} International Conference on Big Data {(IEEE} BigData 2016),
Washington DC, USA, December 5-8, 2016},
pages = {2121--2126},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/BigData.2016.7840840},
doi = {10.1109/BIGDATA.2016.7840840},
timestamp = {Fri, 19 Nov 2021 16:08:20 +0100},
biburl = {https://dblp.org/rec/conf/bigdataconf/SongZGJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ZhengJG16,
author = {Xinnian Zheng and
Lizy K. John and
Andreas Gerstlauer},
title = {Accurate phase-level cross-platform power and performance estimation},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {4:1--4:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2897977},
doi = {10.1145/2897937.2897977},
timestamp = {Tue, 06 Nov 2018 16:58:19 +0100},
biburl = {https://dblp.org/rec/conf/dac/ZhengJG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/AmrouchKGH16,
author = {Hussam Amrouch and
Behnam Khaleghi and
Andreas Gerstlauer and
J{\"{o}}rg Henkel},
title = {Reliability-aware design to suppress aging},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {12:1--12:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2898082},
doi = {10.1145/2897937.2898082},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/AmrouchKGH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/SongLZLRPGJ16,
author = {Shuang Song and
Meng Li and
Xinnian Zheng and
Michael LeBeane and
Jee Ho Ryoo and
Reena Panda and
Andreas Gerstlauer and
Lizy K. John},
title = {Proxy-Guided Load Balancing of Graph Processing Workloads on Heterogeneous
Clusters},
booktitle = {45th International Conference on Parallel Processing, {ICPP} 2016,
Philadelphia, PA, USA, August 16-19, 2016},
pages = {77--86},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ICPP.2016.16},
doi = {10.1109/ICPP.2016.16},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpp/SongLZLRPGJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icppw/WangKBGJ16,
author = {Jiajun Wang and
Ahmed Khawaja and
George Biros and
Andreas Gerstlauer and
Lizy K. John},
title = {Optimizing {GPGPU} Kernel Summation for Performance and Energy Efficiency},
booktitle = {45th International Conference on Parallel Processing Workshops, {ICPP}
Workshops 2016, Philadelphia, PA, USA, August 16-19, 2016},
pages = {123--132},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ICPPW.2016.32},
doi = {10.1109/ICPPW.2016.32},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icppw/WangKBGJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LeeLHSJG16,
author = {Seogoo Lee and
Dongwook Lee and
Kyungtae Han and
Emily Shriver and
Lizy K. John and
Andreas Gerstlauer},
title = {Statistical quality modeling of approximate hardware},
booktitle = {17th International Symposium on Quality Electronic Design, {ISQED}
2016, Santa Clara, CA, USA, March 15-16, 2016},
pages = {163--168},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISQED.2016.7479194},
doi = {10.1109/ISQED.2016.7479194},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/LeeLHSJG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/AsriPJG16,
author = {Mochamad Asri and
Ardavan Pedram and
Lizy K. John and
Andreas Gerstlauer},
editor = {Walid A. Najjar and
Andreas Gerstlauer},
title = {Simulator calibration for accelerator-rich architecture studies},
booktitle = {International Conference on Embedded Computer Systems: Architectures,
Modeling and Simulation, {SAMOS} 2016, Agios Konstantinos, Samos Island,
Greece, July 17-21, 2016},
pages = {88--95},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/SAMOS.2016.7818335},
doi = {10.1109/SAMOS.2016.7818335},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/samos/AsriPJG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/PandaZSRLGJ16,
author = {Reena Panda and
Xinnian Zheng and
Shuang Song and
Jee Ho Ryoo and
Michael LeBeane and
Andreas Gerstlauer and
Lizy K. John},
editor = {Walid A. Najjar and
Andreas Gerstlauer},
title = {Genesys: Automatically generating representative training sets for
predictive benchmarking},
booktitle = {International Conference on Embedded Computer Systems: Architectures,
Modeling and Simulation, {SAMOS} 2016, Agios Konstantinos, Samos Island,
Greece, July 17-21, 2016},
pages = {116--123},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/SAMOS.2016.7818338},
doi = {10.1109/SAMOS.2016.7818338},
timestamp = {Mon, 03 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/samos/PandaZSRLGJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wsc/PfeiferGV16,
author = {Dylan Pfeifer and
Andreas Gerstlauer and
Jonathan Valvano},
title = {Adaptive resolution control in distributed cyber-physical system simulation},
booktitle = {Winter Simulation Conference, {WSC} 2016, Washington, DC, USA, December
11-14, 2016},
pages = {1487--1498},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/WSC.2016.7822200},
doi = {10.1109/WSC.2016.7822200},
timestamp = {Thu, 10 Jun 2021 22:21:51 +0200},
biburl = {https://dblp.org/rec/conf/wsc/PfeiferGV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/samos/2016,
editor = {Walid A. Najjar and
Andreas Gerstlauer},
title = {International Conference on Embedded Computer Systems: Architectures,
Modeling and Simulation, {SAMOS} 2016, Agios Konstantinos, Samos Island,
Greece, July 17-21, 2016},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/xpl/conhome/7803477/proceeding},
isbn = {978-1-5090-3076-7},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/samos/2016.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvt/LeeGH15,
author = {Seogoo Lee and
Andreas Gerstlauer and
Robert W. Heath Jr.},
title = {Distributed Real-Time Implementation of Interference Alignment with
Analog Feedback},
journal = {{IEEE} Trans. Veh. Technol.},
volume = {64},
number = {8},
pages = {3513--3525},
year = {2015},
url = {https://doi.org/10.1109/TVT.2014.2357391},
doi = {10.1109/TVT.2014.2357391},
timestamp = {Thu, 25 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvt/LeeGH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LeeJG15,
author = {Dongwook Lee and
Lizy K. John and
Andreas Gerstlauer},
editor = {Wolfgang Nebel and
David Atienza},
title = {Dynamic power and performance back-annotation for fast and accurate
functional hardware simulation},
booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe
Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March
9-13, 2015},
pages = {1126--1131},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2757074},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/LeeJG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BringmannEGGMSS15,
author = {Oliver Bringmann and
Wolfgang Ecker and
Andreas Gerstlauer and
Ajay Goyal and
Daniel Mueller{-}Gritschneder and
Prasanth Sasidharan and
Simranjit Singh},
editor = {Wolfgang Nebel and
David Atienza},
title = {The next generation of virtual prototyping: ultra-fast yet accurate
simulation of {HW/SW} systems},
booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe
Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March
9-13, 2015},
pages = {1698--1707},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2757206},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/BringmannEGGMSS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LeeKHHJG15,
author = {Dongwook Lee and
Taemin Kim and
Kyungtae Han and
Yatin Hoskote and
Lizy K. John and
Andreas Gerstlauer},
editor = {Diana Marculescu and
Frank Liu},
title = {Learning-Based Power Modeling of System-Level Black-Box IPs},
booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
pages = {847--853},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCAD.2015.7372659},
doi = {10.1109/ICCAD.2015.7372659},
timestamp = {Mon, 26 Jun 2023 16:43:56 +0200},
biburl = {https://dblp.org/rec/conf/iccad/LeeKHHJG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/LeeKRSGJ15,
author = {Wooseok Lee and
Youngchun Kim and
Jee Ho Ryoo and
Dam Sunwoo and
Andreas Gerstlauer and
Lizy K. John},
title = {PowerTrain: {A} learning-based calibration of McPAT power models},
booktitle = {{IEEE/ACM} International Symposium on Low Power Electronics and Design,
{ISLPED} 2015, Rome, Italy, July 22-24, 2015},
pages = {189--194},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISLPED.2015.7273512},
doi = {10.1109/ISLPED.2015.7273512},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/LeeKRSGJ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/ZhengRJG15,
author = {Xinnian Zheng and
Pradeep Ravikumar and
Lizy K. John and
Andreas Gerstlauer},
editor = {Dimitrios Soudris and
Luigi Carro},
title = {Learning-based analytical cross-platform performance prediction},
booktitle = {2015 International Conference on Embedded Computer Systems: Architectures,
Modeling, and Simulation, {SAMOS} 2015, Samos, Greece, July 19-23,
2015},
pages = {52--59},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/SAMOS.2015.7363659},
doi = {10.1109/SAMOS.2015.7363659},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/samos/ZhengRJG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/codes/2015,
editor = {Gabriela Nicolescu and
Andreas Gerstlauer},
title = {2015 International Conference on Hardware/Software Codesign and System
Synthesis, {CODES+ISSS} 2015, Amsterdam, Netherlands, October 4-9,
2015},
publisher = {{IEEE}},
year = {2015},
url = {https://ieeexplore.ieee.org/xpl/conhome/7318233/proceeding},
isbn = {978-1-4673-8321-9},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/codes/2015.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PedramGG14,
author = {Ardavan Pedram and
Andreas Gerstlauer and
Robert A. van de Geijn},
title = {Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix
Factorization Accelerator},
journal = {{IEEE} Trans. Computers},
volume = {63},
number = {8},
pages = {1854--1867},
year = {2014},
url = {https://doi.org/10.1109/TC.2014.2315627},
doi = {10.1109/TC.2014.2315627},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PedramGG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/RazaghiG14,
author = {Parisa Razaghi and
Andreas Gerstlauer},
title = {Host-Compiled Multicore System Simulation for Early Real-Time Performance
Evaluation},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {13},
number = {5s},
pages = {166:1--166:26},
year = {2014},
url = {https://doi.org/10.1145/2678020},
doi = {10.1145/2678020},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/RazaghiG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/PedramMG14,
author = {Ardavan Pedram and
John D. McCalpin and
Andreas Gerstlauer},
title = {A Highly Efficient Multicore Floating-Point {FFT} Architecture Based
on Hybrid Linear Algebra/FFT Cores},
journal = {J. Signal Process. Syst.},
volume = {77},
number = {1-2},
pages = {169--190},
year = {2014},
url = {https://doi.org/10.1007/s11265-014-0896-x},
doi = {10.1007/S11265-014-0896-X},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/PedramMG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MiaoGO14,
author = {Jin Miao and
Andreas Gerstlauer and
Michael Orshansky},
editor = {Yao{-}Wen Chang},
title = {Multi-level approximate logic synthesis under general error constraints},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2014, San Jose, CA, USA, November 3-6, 2014},
pages = {504--510},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICCAD.2014.7001398},
doi = {10.1109/ICCAD.2014.7001398},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/MiaoGO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpads/KhawajaWGJMB14,
author = {Ahmed Khawaja and
Jiajun Wang and
Andreas Gerstlauer and
Lizy K. John and
Dhairya Malhotra and
George Biros},
title = {Performance analysis of {HPC} applications with irregular tree data
structures},
booktitle = {20th {IEEE} International Conference on Parallel and Distributed Systems,
{ICPADS} 2014, Hsinchu, Taiwan, December 16-19, 2014},
pages = {418--425},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/PADSW.2014.7097837},
doi = {10.1109/PADSW.2014.7097837},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icpads/KhawajaWGJMB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/GandhiGJ14,
author = {Darshan Gandhi and
Andreas Gerstlauer and
Lizy K. John},
title = {FastSpot: Host-compiled thermal estimation for early design space
exploration},
booktitle = {Fifteenth International Symposium on Quality Electronic Design, {ISQED}
2014, Santa Clara, CA, USA, March 3-5, 2014},
pages = {625--632},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISQED.2014.6783385},
doi = {10.1109/ISQED.2014.6783385},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/GandhiGJ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/Abdel-HadiGV14,
author = {Ahmed Abdel{-}Hadi and
Andreas Gerstlauer and
Sriram Vishwanath},
title = {Real-Time Rate-Distortion Optimized Streaming of Wireless Video},
journal = {CoRR},
volume = {abs/1406.1915},
year = {2014},
url = {http://arxiv.org/abs/1406.1915},
eprinttype = {arXiv},
eprint = {1406.1915},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/Abdel-HadiGV14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/simulation/PfeiferVG13,
author = {Dylan Pfeifer and
Jonathan Valvano and
Andreas Gerstlauer},
title = {SimConnect and SimTalk for distributed cyber-physical system simulation},
journal = {Simul.},
volume = {89},
number = {10},
pages = {1254--1271},
year = {2013},
url = {https://doi.org/10.1177/0037549712472755},
doi = {10.1177/0037549712472755},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/simulation/PfeiferVG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcsv/HeGO13,
author = {Ku He and
Andreas Gerstlauer and
Michael Orshansky},
title = {Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient
DCT/IDCT-Based Systems},
journal = {{IEEE} Trans. Circuits Syst. Video Technol.},
volume = {23},
number = {6},
pages = {961--974},
year = {2013},
url = {https://doi.org/10.1109/TCSVT.2013.2243658},
doi = {10.1109/TCSVT.2013.2243658},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcsv/HeGO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/PedramGG13,
author = {Ardavan Pedram and
Andreas Gerstlauer and
Robert A. van de Geijn},
editor = {Alberto Nannarelli and
Peter{-}Michael Seidel and
Ping Tak Peter Tang},
title = {Floating Point Architecture Extensions for Optimized Matrix Factorization},
booktitle = {21st {IEEE} Symposium on Computer Arithmetic, {ARITH} 2013, Austin,
TX, USA, April 7-10, 2013},
pages = {49--58},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ARITH.2013.21},
doi = {10.1109/ARITH.2013.21},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arith/PedramGG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/ParkG13,
author = {Hyungman Park and
Andreas Gerstlauer},
title = {Toward a fast stochastic simulation processor for biochemical reaction
networks},
booktitle = {24th International Conference on Application-Specific Systems, Architectures
and Processors, {ASAP} 2013, Washington, DC, USA, June 5-7, 2013},
pages = {50--58},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ASAP.2013.6567550},
doi = {10.1109/ASAP.2013.6567550},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/ParkG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/PedramMG13,
author = {Ardavan Pedram and
John D. McCalpin and
Andreas Gerstlauer},
title = {Transforming a linear algebra core to an {FFT} accelerator},
booktitle = {24th International Conference on Application-Specific Systems, Architectures
and Processors, {ASAP} 2013, Washington, DC, USA, June 5-7, 2013},
pages = {175--184},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ASAP.2013.6567572},
doi = {10.1109/ASAP.2013.6567572},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/PedramMG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/ChakravartyZG13,
author = {Suhas Chakravarty and
Zhuoran Zhao and
Andreas Gerstlauer},
title = {Automated, retargetable back-annotation for host compiled performance
and power modeling},
booktitle = {Proceedings of the International Conference on Hardware/Software Codesign
and System Synthesis, {CODES+ISSS} 2013, Montreal, QC, Canada, September
29 - October 4, 2013},
pages = {36:1--36:10},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CODES-ISSS.2013.6659023},
doi = {10.1109/CODES-ISSS.2013.6659023},
timestamp = {Wed, 16 Oct 2019 14:14:48 +0200},
biburl = {https://dblp.org/rec/conf/codes/ChakravartyZG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MiaoGO13,
author = {Jin Miao and
Andreas Gerstlauer and
Michael Orshansky},
editor = {J{\"{o}}rg Henkel},
title = {Approximate logic synthesis under general error magnitude and frequency
constraints},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
ICCAD'13, San Jose, CA, USA, November 18-21, 2013},
pages = {779--786},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ICCAD.2013.6691202},
doi = {10.1109/ICCAD.2013.6691202},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/MiaoGO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iess/MarianoLGC13,
author = {Artur Mariano and
Dongwook Lee and
Andreas Gerstlauer and
Derek Chiou},
editor = {Gunar Schirner and
Marcelo G{\"{o}}tz and
Achim Rettberg and
Mauro Cesar Zanella and
Franz J. Rammig},
title = {Hardware and Software Implementations of Prim's Algorithm for Efficient
Minimum Spanning Tree Computation},
booktitle = {Embedded Systems: Design, Analysis and Verification - 4th {IFIP} {TC}
10 International Embedded Systems Symposium, {IESS} 2013, Paderborn,
Germany, June 17-19, 2013. Proceedings},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {403},
pages = {151--158},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-642-38853-8\_14},
doi = {10.1007/978-3-642-38853-8\_14},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iess/MarianoLGC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/HeGO13,
author = {Ku He and
Andreas Gerstlauer and
Michael Orshansky},
title = {Low-energy digital filter design based on controlled timing error
acceptance},
booktitle = {International Symposium on Quality Electronic Design, {ISQED} 2013,
Santa Clara, CA, USA, March 4-6, 2013},
pages = {151--157},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISQED.2013.6523603},
doi = {10.1109/ISQED.2013.6523603},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/HeGO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pads/PfeiferGV13,
author = {Dylan Pfeifer and
Andreas Gerstlauer and
Jonathan Valvano},
editor = {Margaret L. Loper and
Gabriel A. Wainer},
title = {Dynamic resolution in distributed cyber-physical system simulation},
booktitle = {{SIGSIM} Principles of Advanced Discrete Simulation, {SIGSIM-PADS}
'13, Montreal, QC, Canada, May 19-22, 2013},
pages = {277--284},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2486092.2486127},
doi = {10.1145/2486092.2486127},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/pads/PfeiferGV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeG13a,
author = {Seogoo Lee and
Andreas Gerstlauer},
editor = {Alex Orailoglu and
H. Fatih Ugurdag and
Lu{\'{\i}}s Miguel Silveira and
Martin Margala and
Ricardo Reis},
title = {Fine Grain Precision Scaling for Datapath Approximations in Digital
Signal Processing Systems},
booktitle = {VLSI-SoC: At the Crossroads of Emerging Trends - 21st {IFIP} {WG}
10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {461},
pages = {119--143},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-319-23799-2\_6},
doi = {10.1007/978-3-319-23799-2\_6},
timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LeeG13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeG13,
author = {Seogoo Lee and
Andreas Gerstlauer},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Fine grain word length optimization for dynamic precision scaling
in {DSP} systems},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {266--271},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673287},
doi = {10.1109/VLSI-SOC.2013.6673287},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LeeG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/RazaghiG12,
author = {Parisa Razaghi and
Andreas Gerstlauer},
title = {Predictive {OS} Modeling for Host-Compiled Simulation of Periodic
Real-Time Task Sets},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {4},
number = {1},
pages = {5--8},
year = {2012},
url = {https://doi.org/10.1109/LES.2012.2186281},
doi = {10.1109/LES.2012.2186281},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/RazaghiG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PedramGG12,
author = {Ardavan Pedram and
Robert A. van de Geijn and
Andreas Gerstlauer},
title = {Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra
Architectures},
journal = {{IEEE} Trans. Computers},
volume = {61},
number = {12},
pages = {1724--1736},
year = {2012},
url = {https://doi.org/10.1109/TC.2012.132},
doi = {10.1109/TC.2012.132},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PedramGG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/LinGE12,
author = {Jing Lin and
Andreas Gerstlauer and
Brian L. Evans},
title = {Communication-aware Heterogeneous Multiprocessor Mapping for Real-time
Streaming Systems},
journal = {J. Signal Process. Syst.},
volume = {69},
number = {3},
pages = {279--291},
year = {2012},
url = {https://doi.org/10.1007/s11265-012-0674-6},
doi = {10.1007/S11265-012-0674-6},
timestamp = {Thu, 03 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/LinGE12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/acssc/MasseySLLGH12,
author = {Jackson W. Massey and
Jonathan Starr and
Seogoo Lee and
Dongwook Lee and
Andreas Gerstlauer and
Robert W. Heath Jr.},
editor = {Michael B. Matthews},
title = {Implementation of a real-time wireless interference alignment network},
booktitle = {Conference Record of the Forty Sixth Asilomar Conference on Signals,
Systems and Computers, {ACSCC} 2012, Pacific Grove, CA, USA, November
4-7, 2012},
pages = {104--108},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ACSSC.2012.6488968},
doi = {10.1109/ACSSC.2012.6488968},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/acssc/MasseySLLGH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/PedramGKGSG12,
author = {Ardavan Pedram and
Syed Zohaib Gilani and
Nam Sung Kim and
Robert A. van de Geijn and
Michael J. Schulte and
Andreas Gerstlauer},
title = {A Linear Algebra Core Design for Efficient Level-3 {BLAS}},
booktitle = {23rd {IEEE} International Conference on Application-Specific Systems,
Architectures and Processors, {ASAP} 2012, Delft, The Netherlands,
July 9-11, 2012},
pages = {149--152},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ASAP.2012.18},
doi = {10.1109/ASAP.2012.18},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/PedramGKGSG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GerstlauerCKR12,
author = {Andreas Gerstlauer and
Suhas Chakravarty and
Manan Kathuria and
Parisa Razaghi},
title = {Abstract system-level models for early performance and power exploration},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {213--218},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6164947},
doi = {10.1109/ASPDAC.2012.6164947},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/GerstlauerCKR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/RazaghiG12,
author = {Parisa Razaghi and
Andreas Gerstlauer},
title = {Automatic timing granularity adjustment for host-compiled software
simulation},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {567--572},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6165021},
doi = {10.1109/ASPDAC.2012.6165021},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/RazaghiG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/LeePG12,
author = {Dongwook Lee and
Hyungman Park and
Andreas Gerstlauer},
editor = {Ahmed Jerraya and
Luca P. Carloni and
Naehyuck Chang and
Franco Fummi},
title = {Synthesis of optimized hardware transactors from abstract communication
specifications},
booktitle = {Proceedings of the 10th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2012, part of ESWeek '12
Eighth Embedded Systems Week, Tampere, Finland, October 7-12, 2012},
pages = {403--412},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2380445.2380508},
doi = {10.1145/2380445.2380508},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/LeePG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MiaoHGO12,
author = {Jin Miao and
Ku He and
Andreas Gerstlauer and
Michael Orshansky},
editor = {Alan J. Hu},
title = {Modeling and synthesis of quality-energy optimal approximate adders},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {728--735},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429542},
doi = {10.1145/2429384.2429542},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/MiaoHGO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icicdt/HeGO12,
author = {Ku He and
Andreas Gerstlauer and
Michael Orshansky},
title = {Low-energy signal processing using circuit-level timing-error acceptance},
booktitle = {{IEEE} International Conference on {IC} Design {\&} Technology,
{ICICDT} 2012, Austin, TX, USA, May 30 - June 1, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ICICDT.2012.6232873},
doi = {10.1109/ICICDT.2012.6232873},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/icicdt/HeGO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbac-pad/PedramGG12,
author = {Ardavan Pedram and
Andreas Gerstlauer and
Robert A. van de Geijn},
editor = {Jairo Panetta and
Jos{\'{e}} E. Moreira and
David A. Padua and
Philippe O. A. Navaux},
title = {On the Efficiency of Register File versus Broadcast Interconnect for
Collective Communications in Data-Parallel Hardware Accelerators},
booktitle = {{IEEE} 24th International Symposium on Computer Architecture and High
Performance Computing, {SBAC-PAD} 2012, New York, NY, USA, October
24-26, 2012},
pages = {19--26},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/SBAC-PAD.2012.35},
doi = {10.1109/SBAC-PAD.2012.35},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbac-pad/PedramGG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/PedramGG11,
author = {Ardavan Pedram and
Andreas Gerstlauer and
Robert A. van de Geijn},
editor = {Joseph R. Cavallaro and
Milos D. Ercegovac and
Frank Hannig and
Paolo Ienne and
Earl E. Swartzlander Jr. and
Alexandre F. Tenca},
title = {A high-performance, low-power linear algebra core},
booktitle = {22nd {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2011, Santa Monica, CA, USA,
Sept. 11-14, 2011},
pages = {35--42},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ASAP.2011.6043234},
doi = {10.1109/ASAP.2011.6043234},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/PedramGG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DomerCHG11,
author = {Rainer D{\"{o}}mer and
Weiwei Chen and
Xu Han and
Andreas Gerstlauer},
title = {Multi-core parallel simulation of System-level Description Languages},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {311--316},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722205},
doi = {10.1109/ASPDAC.2011.5722205},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/DomerCHG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RazaghiG11,
author = {Parisa Razaghi and
Andreas Gerstlauer},
title = {Host-compiled multicore {RTOS} simulator for embedded real-time software
development},
booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
March 14-18, 2011},
pages = {222--227},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/DATE.2011.5763046},
doi = {10.1109/DATE.2011.5763046},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/RazaghiG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HeGO11,
author = {Ku He and
Andreas Gerstlauer and
Michael Orshansky},
title = {Controlled timing-error acceptance for low energy {IDCT} design},
booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
March 14-18, 2011},
pages = {758--763},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/DATE.2011.5763129},
doi = {10.1109/DATE.2011.5763129},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/HeGO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsrt/PfeiferG11,
author = {Dylan Pfeifer and
Andreas Gerstlauer},
editor = {David J. Roberts and
J. Mark Pullen and
Georgios Theodoropoulos and
Nick J. Avis},
title = {Expression-Level Parallelism for Distributed Spice Circuit Simulation},
booktitle = {15th {IEEE/ACM} International Symposium on Distributed Simulation
and Real Time Applications, {DS-RT} 2011, Salford, United Kingdom,
September 4-7, 2011},
pages = {12--17},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/DS-RT.2011.32},
doi = {10.1109/DS-RT.2011.32},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsrt/PfeiferG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/embc/LopezGAM11,
author = {Martha Salome Lopez and
Andreas Gerstlauer and
Alfonso {\'{A}}vila and
Sergio Omar Martinez{-}Chapa},
title = {A programmable and configurable multi-port System-on-Chip for stimulating
electrokinetically-driven microfluidic devices},
booktitle = {33rd Annual International Conference of the {IEEE} Engineering in
Medicine and Biology Society, {EMBC} 2011, Boston, MA, USA, August
30 - Sept. 3, 2011},
pages = {8361--8364},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/IEMBS.2011.6092062},
doi = {10.1109/IEMBS.2011.6092062},
timestamp = {Tue, 31 Mar 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/embc/LopezGAM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/LinSGE11,
author = {Jing Lin and
Akshaya Srivatsa and
Andreas Gerstlauer and
Brian L. Evans},
title = {Heterogeneous multiprocessor mapping for real-time streaming systems},
booktitle = {Proceedings of the {IEEE} International Conference on Acoustics, Speech,
and Signal Processing, {ICASSP} 2011, May 22-27, 2011, Prague Congress
Center, Prague, Czech Republic},
pages = {1605--1608},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ICASSP.2011.5946804},
doi = {10.1109/ICASSP.2011.5946804},
timestamp = {Thu, 03 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icassp/LinSGE11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vtc/Abdel-HadiMGV11,
author = {Ahmed Abdel{-}Hadi and
Jonas Michel and
Andreas Gerstlauer and
Sriram Vishwanath},
title = {Real-Time Optimization of Video Transmission in a Network of AAVs},
booktitle = {Proceedings of the 74th {IEEE} Vehicular Technology Conference, {VTC}
Fall 2011, 5-8 September 2011, San Francisco, CA, {USA}},
pages = {1--5},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VETECF.2011.6093186},
doi = {10.1109/VETECF.2011.6093186},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/vtc/Abdel-HadiMGV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SchirnerGD10,
author = {Gunar Schirner and
Andreas Gerstlauer and
Rainer D{\"{o}}mer},
title = {Fast and accurate processor models for efficient MPSoC design},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {15},
number = {2},
pages = {10:1--10:26},
year = {2010},
url = {https://doi.org/10.1145/1698759.1698760},
doi = {10.1145/1698759.1698760},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/SchirnerGD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GerstlauerS10,
author = {Andreas Gerstlauer and
Gunar Schirner},
title = {Platform modeling for exploration and synthesis},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {725--731},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419794},
doi = {10.1109/ASPDAC.2010.5419794},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/GerstlauerS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SchirnerGD10,
author = {Gunar Schirner and
Andreas Gerstlauer and
Rainer D{\"{o}}mer},
title = {System-level development of embedded software},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {903--909},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419674},
doi = {10.1109/ASPDAC.2010.5419674},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/SchirnerGD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/Gerstlauer10,
author = {Andreas Gerstlauer},
title = {Host-compiled simulation of multi-core platforms},
booktitle = {Proceedings of the 21st {IEEE} International Symposium on Rapid System
Prototyping, {RSP} 2010, Fairfax, VA, USA, 8-11 June, 2010},
pages = {1--6},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/RSP.2010.5656352},
doi = {10.1109/RSP.2010.5656352},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/rsp/Gerstlauer10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/Gerstlauer10a,
author = {Andreas Gerstlauer},
title = {Host-compiled simulation of multi-core platforms},
booktitle = {Proceedings of the 21st {IEEE} International Symposium on Rapid System
Prototyping, {RSP} 2010, Fairfax, VA, USA, 8-11 June, 2010},
pages = {1--6},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/RSP.2010.5656355},
doi = {10.1109/RSP.2010.5656355},
timestamp = {Thu, 25 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rsp/Gerstlauer10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/GladigauGHST10,
author = {Jens Gladigau and
Andreas Gerstlauer and
Christian Haubelt and
Martin Streub{\"{u}}hr and
J{\"{u}}rgen Teich},
editor = {Fadi J. Kurdahi and
Jarmo Takala},
title = {A system-level synthesis approach from formal application models to
generic bus-based MPSoCs},
booktitle = {Proceedings of the 2010 International Conference on Embedded Computer
Systems: Architectures, Modeling and Simulation {(IC-SAMOS} 2010),
Samos, Greece, July 19-22, 2010},
pages = {118--125},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICSAMOS.2010.5642076},
doi = {10.1109/ICSAMOS.2010.5642076},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/samos/GladigauGHST10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GerstlauerHPSGT09,
author = {Andreas Gerstlauer and
Christian Haubelt and
Andy D. Pimentel and
Todor P. Stefanov and
Daniel D. Gajski and
J{\"{u}}rgen Teich},
title = {Electronic System-Level Synthesis Methodologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {10},
pages = {1517--1530},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2026356},
doi = {10.1109/TCAD.2009.2026356},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GerstlauerHPSGT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DomerG009,
author = {Rainer D{\"{o}}mer and
Andreas Gerstlauer and
Wolfgang M{\"{u}}ller},
editor = {Kazutoshi Wakabayashi},
title = {Introduction to hardware-dependent software design hardware-dependent
software for multi- and many-core embedded systems},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {290--292},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796495},
doi = {10.1109/ASPDAC.2009.4796495},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/DomerG009.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iess/BanerjeeG09,
author = {Amal Banerjee and
Andreas Gerstlauer},
editor = {Achim Rettberg and
Mauro Cesar Zanella and
Michael Amann and
Michael Keckeisen and
Franz J. Rammig},
title = {Transaction Level Modeling of Best-Effort Channels for Networked Embedded
Devices},
booktitle = {Analysis, Architectures and Modelling of Embedded Systems, Third {IFIP}
{TC} 10 International Embedded Systems Symposium, {IESS} 2009, Langenargen,
Germany, September 14-16, 2009. Proceedings},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {310},
pages = {77--88},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-642-04284-3\_8},
doi = {10.1007/978-3-642-04284-3\_8},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iess/BanerjeeG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iess/PedramCG09,
author = {Ardavan Pedram and
David Craven and
Andreas Gerstlauer},
editor = {Achim Rettberg and
Mauro Cesar Zanella and
Michael Amann and
Michael Keckeisen and
Franz J. Rammig},
title = {Modeling Cache Effects at the Transaction Level},
booktitle = {Analysis, Architectures and Modelling of Embedded Systems, Third {IFIP}
{TC} 10 International Embedded Systems Symposium, {IESS} 2009, Langenargen,
Germany, September 14-16, 2009. Proceedings},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {310},
pages = {89--101},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-642-04284-3\_9},
doi = {10.1007/978-3-642-04284-3\_9},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iess/PedramCG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ejes/DomerGPSCYAG08,
author = {Rainer D{\"{o}}mer and
Andreas Gerstlauer and
Junyu Peng and
Dongwan Shin and
Lukai Cai and
Haobo Yu and
Samar Abdi and
Daniel D. Gajski},
title = {System-on-Chip Environment: {A} SpecC-Based Framework for Heterogeneous
MPSoC Design},
journal = {{EURASIP} J. Embed. Syst.},
volume = {2008},
year = {2008},
url = {https://doi.org/10.1155/2008/647953},
doi = {10.1155/2008/647953},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ejes/DomerGPSCYAG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShinGDG08,
author = {Dongwan Shin and
Andreas Gerstlauer and
Rainer D{\"{o}}mer and
Daniel Gajski},
title = {An Interactive Design Environment for C-Based High-Level Synthesis
of {RTL} Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {4},
pages = {466--475},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2007.915390},
doi = {10.1109/TVLSI.2007.915390},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShinGDG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SchirnerGD08,
author = {Gunar Schirner and
Andreas Gerstlauer and
Rainer D{\"{o}}mer},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Automatic generation of hardware dependent software for MPSoCs from
abstract system specifications},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {271--276},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4483954},
doi = {10.1109/ASPDAC.2008.4483954},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/SchirnerGD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/GerstlauerPSGNAN08,
author = {Andreas Gerstlauer and
Junyu Peng and
Dongwan Shin and
Daniel Gajski and
Atsushi Nakamura and
Dai Araki and
Yuuji Nishihara},
editor = {Limor Fix},
title = {Specify-explore-refine {(SER):} from specification to implementation},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {586--591},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391617},
doi = {10.1145/1391469.1391617},
timestamp = {Fri, 28 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/GerstlauerPSGNAN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GerstlauerSPDG07,
author = {Andreas Gerstlauer and
Dongwan Shin and
Junyu Peng and
Rainer D{\"{o}}mer and
Daniel Gajski},
title = {Automatic Layer-Based Generation of System-On-Chip Bus Communication
Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1676--1687},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895794},
doi = {10.1109/TCAD.2007.895794},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GerstlauerSPDG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SchirnerGD07,
author = {Gunar Schirner and
Andreas Gerstlauer and
Rainer D{\"{o}}mer},
title = {Abstract, Multifaceted Modeling of Embedded Processors for System
Level Design},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {384--389},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.358016},
doi = {10.1109/ASPDAC.2007.358016},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/SchirnerGD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iess/ShinGDG07,
author = {Dongwan Shin and
Andreas Gerstlauer and
Rainer D{\"{o}}mer and
Daniel D. Gajski},
editor = {Achim Rettberg and
Mauro Cesar Zanella and
Rainer D{\"{o}}mer and
Andreas Gerstlauer and
Franz{-}Josef Rammig},
title = {An Interactive Design Environment for C-based High-Level Synthesis},
booktitle = {Embedded System Design: Topics, Techniques and Trends, {IFIP} {TC10}
Working Conference: International Embedded Systems Symposium (IESS),
May 30 - June 1, 2007, Irvine, CA, {USA}},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {231},
pages = {135--144},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-0-387-72258-0\_12},
doi = {10.1007/978-0-387-72258-0\_12},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iess/ShinGDG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iess/SchirnerSGD07,
author = {Gunar Schirner and
Gautam Sachdeva and
Andreas Gerstlauer and
Rainer D{\"{o}}mer},
editor = {Achim Rettberg and
Mauro Cesar Zanella and
Rainer D{\"{o}}mer and
Andreas Gerstlauer and
Franz{-}Josef Rammig},
title = {Embedded Software Development in a System-Level Design Flow},
booktitle = {Embedded System Design: Topics, Techniques and Trends, {IFIP} {TC10}
Working Conference: International Embedded Systems Symposium (IESS),
May 30 - June 1, 2007, Irvine, CA, {USA}},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {231},
pages = {289--298},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-0-387-72258-0\_25},
doi = {10.1007/978-0-387-72258-0\_25},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iess/SchirnerSGD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iess/2007,
editor = {Achim Rettberg and
Mauro Cesar Zanella and
Rainer D{\"{o}}mer and
Andreas Gerstlauer and
Franz{-}Josef Rammig},
title = {Embedded System Design: Topics, Techniques and Trends, {IFIP} {TC10}
Working Conference: International Embedded Systems Symposium (IESS),
May 30 - June 1, 2007, Irvine, CA, {USA}},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {231},
publisher = {Springer},
year = {2007},
isbn = {978-0-387-72257-3},
timestamp = {Tue, 12 Jun 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iess/2007.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/ShinGPDG06,
author = {Dongwan Shin and
Andreas Gerstlauer and
Junyu Peng and
Rainer D{\"{o}}mer and
Daniel D. Gajski},
editor = {Reinaldo A. Bergamaschi and
Kiyoung Choi},
title = {Automatic generation of transaction level models for rapid design
space exploration},
booktitle = {Proceedings of the 4th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2006, Seoul, Korea, October
22-25, 2006},
pages = {64--69},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1176254.1176272},
doi = {10.1145/1176254.1176272},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/ShinGPDG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GerstlauerSDG05,
author = {Andreas Gerstlauer and
Dongwan Shin and
Rainer D{\"{o}}mer and
Daniel D. Gajski},
editor = {Tingao Tang},
title = {System-level communication modeling for network-on-chip synthesis},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {45--48},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120740},
doi = {10.1145/1120725.1120740},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/GerstlauerSDG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/CaiGG05,
author = {Lukai Cai and
Andreas Gerstlauer and
Daniel Gajski},
editor = {Tingao Tang},
title = {Multi-metric and multi-entity characterization of applications for
early system design exploration},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {944--947},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120763},
doi = {10.1145/1120725.1120763},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/CaiGG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/ShinGDG05,
author = {Dongwan Shin and
Andreas Gerstlauer and
Rainer D{\"{o}}mer and
Daniel D. Gajski},
editor = {Petru Eles and
Axel Jantsch and
Reinaldo A. Bergamaschi},
title = {Automatic network generation for system-on-chip communication design},
booktitle = {Proceedings of the 3rd {IEEE/ACM/IFIP} International Conference on
Hardware/Software Codesign and System Synthesis, {CODES+ISSS} 2005,
Jersey City, NJ, USA, September 19-21, 2005},
pages = {255--260},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1084834.1084899},
doi = {10.1145/1084834.1084899},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/ShinGDG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iess/ShinGDG05,
author = {Dongwan Shin and
Andreas Gerstlauer and
Rainer D{\"{o}}mer and
Daniel D. Gajski},
editor = {Achim Rettberg and
Mauro Cesar Zanella and
Franz J. Rammig},
title = {Automatic Generation of Communication Architectures},
booktitle = {From Specification to Embedded Systems Application [International
Embedded Systems Symposium, {IESS} 2005, Manaus, Brazil, August 2005]},
series = {{IFIP}},
volume = {184},
pages = {179--188},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11523277\_18},
doi = {10.1007/11523277\_18},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iess/ShinGDG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/CaiGG04,
author = {Lukai Cai and
Andreas Gerstlauer and
Daniel Gajski},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {Retargetable profiling for rapid, early system-level design space
exploration},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {281--286},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996651},
doi = {10.1145/996566.996651},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/CaiGG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/YuGG03,
author = {Haobo Yu and
Andreas Gerstlauer and
Daniel Gajski},
editor = {Rajesh Gupta and
Yukihiro Nakamura and
Alex Orailoglu and
Pai H. Chou},
title = {{RTOS} scheduling in transaction level models},
booktitle = {Proceedings of the 1st {IEEE/ACM/IFIP} International Conference on
Hardware/Software Codesign and System Synthesis, {CODES+ISSS} 2003,
Newport Beach, CA, USA, October 1-3, 2003},
pages = {31--36},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/944645.944653},
doi = {10.1145/944645.944653},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/YuGG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GerstlauerYG03,
author = {Andreas Gerstlauer and
Haobo Yu and
Daniel Gajski},
title = {{RTOS} Modeling for System Level Design},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {10130--10135},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10140},
doi = {10.1109/DATE.2003.10140},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/GerstlauerYG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/03/GerstlauerYG03,
author = {Andreas Gerstlauer and
Haobo Yu and
Daniel D. Gajski},
editor = {Ahmed Amine Jerraya and
Sungjoo Yoo and
Diederik Verkest and
Norbert Wehn},
title = {{RTOS} Modeling for System Level Design},
booktitle = {Embedded Software for SoC},
pages = {55--68},
publisher = {Kluwer / Springer},
year = {2003},
url = {https://doi.org/10.1007/0-306-48709-8\_5},
doi = {10.1007/0-306-48709-8\_5},
timestamp = {Thu, 04 Jul 2019 16:02:30 +0200},
biburl = {https://dblp.org/rec/books/sp/03/GerstlauerYG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/IEEEisic/SaoudGG02,
author = {Slim Ben Saoud and
Daniel D. Gajski and
Andreas Gerstlauer},
title = {Co-design of embedded controllers for power electronics and electric
systems},
booktitle = {Proceedings of the 2002 {IEEE} International Symposium on Intelligent
Control, {ISIC} 2002, Vancouver, BC, Canada, October 27-30, 2002},
pages = {379--383},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ISIC.2002.1157793},
doi = {10.1109/ISIC.2002.1157793},
timestamp = {Mon, 17 Jul 2023 10:53:50 +0200},
biburl = {https://dblp.org/rec/conf/IEEEisic/SaoudGG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isss/DomerGM02,
author = {Rainer D{\"{o}}mer and
Andreas Gerstlauer and
Wolfgang M{\"{u}}ller},
editor = {El Mostapha Aboulhamid and
Yukihiro Nakamura},
title = {The Formal Execution Semantics of SpecC},
booktitle = {Proceedings of the 15th International Symposium on System Synthesis
{(ISSS} 2002), October 2-4, 2002, Kyoto, Japan},
pages = {150--155},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227168},
doi = {10.1109/ISSS.2002.1227168},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isss/DomerGM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isss/GajskiG02,
author = {Daniel Gajski and
Andreas Gerstlauer},
editor = {El Mostapha Aboulhamid and
Yukihiro Nakamura},
title = {System-Level Abstraction Semantics},
booktitle = {Proceedings of the 15th International Symposium on System Synthesis
{(ISSS} 2002), October 2-4, 2002, Kyoto, Japan},
pages = {231--236},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227183},
doi = {10.1109/ISSS.2002.1227183},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isss/GajskiG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smc/SaoudGG02,
author = {Slim Ben Saoud and
Daniel D. Gajski and
Andreas Gerstlauer},
title = {Seamless approach for the design of control systems for power electronics
and electric drives},
booktitle = {{IEEE} International Conference on Systems, Man and Cybernetics: Bridging
the Digital Divide, Yasmine Hammamet, Tunisia, October 6-9, 2002 -
Volume 1},
pages = {6},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ICSMC.2002.1175617},
doi = {10.1109/ICSMC.2002.1175617},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/smc/SaoudGG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0036856,
author = {Andreas Gerstlauer and
Rainer D{\"{o}}mer and
Junyu Peng and
Daniel D. Gajski},
title = {System Design - {A} Practical Guide with SpecC},
publisher = {Springer},
year = {2001},
url = {https://doi.org/10.1007/978-1-4615-1481-7},
doi = {10.1007/978-1-4615-1481-7},
isbn = {978-0-7923-7387-2},
timestamp = {Tue, 16 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0036856.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip10-3/RettbergRGGHK00,
author = {Achim Rettberg and
Franz J. Rammig and
Andreas Gerstlauer and
Daniel Gajski and
Wolfram Hardt and
Bernd Kleinjohann},
editor = {Bernd Kleinjohann},
title = {The Specification Language SpecC within the {PARADISE} Design Environment},
booktitle = {Architecture and Design of Distributed Embedded Systems, {IFIP} {WG10.3/WG10.4/WG10.5}
International Workshop on Distributed and Parallel Embedded Systems
{(DIPES} 2000), October 18-19, 2000, Schlo{\ss} Eringerfeld, Germany},
series = {{IFIP} Conference Proceedings},
volume = {189},
pages = {111--120},
publisher = {Kluwer},
year = {2000},
timestamp = {Tue, 27 Jul 2004 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ifip10-3/RettbergRGGHK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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