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ORCIDBibTeX records: Wolfgang Günther 0001
@article{DBLP:journals/jgaa/EschbachGB06,
author = {Thomas Eschbach and
Wolfgang G{\"{u}}nther and
Bernd Becker},
title = {Orthogonal Hypergraph Drawing for Improved Visibility},
journal = {J. Graph Algorithms Appl.},
volume = {10},
number = {2},
pages = {141--157},
year = {2006},
url = {https://doi.org/10.7155/jgaa.00122},
doi = {10.7155/JGAA.00122},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jgaa/EschbachGB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EbendtGD05,
author = {R{\"{u}}diger Ebendt and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Combining ordered best-first search with branch and bound for exact
{BDD} minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {10},
pages = {1515--1529},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2005.852053},
doi = {10.1109/TCAD.2005.852053},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EbendtGD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/EschbachGB05,
author = {Thomas Eschbach and
Wolfgang G{\"{u}}nther and
Bernd Becker},
title = {Orthogonal Circuit Visualization Improved by Merging the Placement
and Routing Phases},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {433--438},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.134},
doi = {10.1109/ICVD.2005.134},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/EschbachGB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/EbendtGD04,
author = {R{\"{u}}diger Ebendt and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
editor = {Masaharu Imai},
title = {Minimization of the expected path length in BDDs based on local changes},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {865--870},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.135},
doi = {10.1109/ASPDAC.2004.135},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/EbendtGD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/EbendtGD04a,
author = {R{\"{u}}diger Ebendt and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
editor = {Masaharu Imai},
title = {Combining ordered best-first search with branch and bound for exact
{BDD} minimization},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {875--878},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.69},
doi = {10.1109/ASPDAC.2004.69},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/EbendtGD04a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/EschbachGB04,
author = {Thomas Eschbach and
Wolfgang G{\"{u}}nther and
Bernd Becker},
editor = {David Garrett and
John C. Lach and
Charles A. Zukowski},
title = {Orthogonal hypergraph routing for improved visibility},
booktitle = {Proceedings of the 14th {ACM} Great Lakes Symposium on {VLSI} 2004,
Boston, MA, USA, April 26-28, 2004},
pages = {385--388},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/988952.989045},
doi = {10.1145/988952.989045},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/EschbachGB04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/GuntherH04,
author = {Wolfgang G{\"{u}}nther and
Stefan H{\"{o}}reth},
editor = {Dominik Stoffel and
Wolfgang Kunz},
title = {Some Common Synthesis-Simulation-Mismatches},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February
24-25, 2004},
pages = {127--136},
publisher = {Shaker},
year = {2004},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/GuntherH04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/DrechslerGS04,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Burkhard Stubert},
editor = {Dominik Stoffel and
Wolfgang Kunz},
title = {Efficient (Non-)Reachability Analysis of Counterexamples},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February
24-25, 2004},
pages = {250--259},
publisher = {Shaker},
year = {2004},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/DrechslerGS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PolianGB03,
author = {Ilia Polian and
Wolfgang G{\"{u}}nther and
Bernd Becker},
title = {Pattern-based verification of connections to intellectual property
cores},
journal = {Integr.},
volume = {35},
number = {1},
pages = {25--44},
year = {2003},
url = {https://doi.org/10.1016/S0167-9260(03)00003-8},
doi = {10.1016/S0167-9260(03)00003-8},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PolianGB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/DrechslerGELA03,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Thomas Eschbach and
Lothar Linhard and
Gerhard Angst},
title = {Recursive bi-partitioning of netlists for large number of partitions},
journal = {J. Syst. Archit.},
volume = {49},
number = {12-15},
pages = {521--528},
year = {2003},
url = {https://doi.org/10.1016/S1383-7621(03)00093-6},
doi = {10.1016/S1383-7621(03)00093-6},
timestamp = {Tue, 19 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/DrechslerGELA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/GuntherD03,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Efficient Minimization and Manipulation of Linearly Transformed Binary
Decision Diagrams},
journal = {{IEEE} Trans. Computers},
volume = {52},
number = {9},
pages = {1196--1209},
year = {2003},
url = {https://doi.org/10.1109/TC.2003.1228514},
doi = {10.1109/TC.2003.1228514},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/GuntherD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EbendtGD03,
author = {R{\"{u}}diger Ebendt and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {An improved branch and bound algorithm for exact {BDD} minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {12},
pages = {1657--1663},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.819427},
doi = {10.1109/TCAD.2003.819427},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EbendtGD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/EbendtGD03,
author = {R{\"{u}}diger Ebendt and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Combination of Lower Bounds in Exact {BDD} Minimization},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {10758--10763},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10040},
doi = {10.1109/DATE.2003.10040},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/EbendtGD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/PolianGB03,
author = {Ilia Polian and
Wolfgang G{\"{u}}nther and
Bernd Becker},
editor = {Rolf Drechsler},
title = {The Case for 2-POF},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25,
2003},
pages = {164--173},
publisher = {Shaker},
year = {2003},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/PolianGB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EschbachGB03,
author = {Thomas Eschbach and
Wolfgang G{\"{u}}nther and
Bernd Becker},
editor = {Hamid R. Arabnia and
Laurence Tianruo Yang},
title = {Cross Reduction for Orthogonal Circuit Visualization},
booktitle = {Proceedings of the International Conference on VLSI, {VLSI} '03, June
23 - 26, 2003, Las Vegas, Nevada, {USA}},
pages = {107--113},
publisher = {{CSREA} Press},
year = {2003},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/EschbachGB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuntherD02,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Minimization of free BDDs},
journal = {Integr.},
volume = {32},
number = {1-2},
pages = {41--59},
year = {2002},
url = {https://doi.org/10.1016/S0167-9260(02)00041-X},
doi = {10.1016/S0167-9260(02)00041-X},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GuntherD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DrechslerGH02,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Stefan H{\"{o}}reth},
title = {Minimization of Word-Level Decision Diagrams},
journal = {Integr.},
volume = {33},
number = {1-2},
pages = {39--70},
year = {2002},
url = {https://doi.org/10.1016/S0167-9260(02)00047-0},
doi = {10.1016/S0167-9260(02)00047-0},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DrechslerGH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ThorntonDG02,
author = {Mitchell A. Thornton and
Rolf Drechsler and
Wolfgang G{\"{u}}nther},
title = {Logic Circuit Equivalence Checking Using Haar Spectral Coefficients
and Partial BDDs},
journal = {{VLSI} Design},
volume = {14},
number = {1},
pages = {53--64},
year = {2002},
url = {https://doi.org/10.1080/10655140290009800},
doi = {10.1080/10655140290009800},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ThorntonDG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/DrechslerGELA02,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Thomas Eschbach and
Lothar Linhard and
Gerhard Angst},
title = {Recursive Bi-Partitioning of Netlists for Large Number of Partitions},
booktitle = {2002 Euromicro Symposium on Digital Systems Design {(DSD} 2002), Systems-on-Chip,
4-6 September 2002, Dortmund, Germany},
pages = {38--44},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DSD.2002.1115349},
doi = {10.1109/DSD.2002.1115349},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/DrechslerGELA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gd/EschbachGDB02,
author = {Thomas Eschbach and
Wolfgang G{\"{u}}nther and
Rolf Drechsler and
Bernd Becker},
editor = {Stephen G. Kobourov and
Michael T. Goodrich},
title = {Crossing Reduction by Windows Optimization},
booktitle = {Graph Drawing, 10th International Symposium, {GD} 2002, Irvine, CA,
USA, August 26-28, 2002, Revised Papers},
series = {Lecture Notes in Computer Science},
volume = {2528},
pages = {285--294},
publisher = {Springer},
year = {2002},
url = {https://doi.org/10.1007/3-540-36151-0\_27},
doi = {10.1007/3-540-36151-0\_27},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/gd/EschbachGDB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/dnb/Gunther01,
author = {Wolfgang G{\"{u}}nther},
title = {Minimierung von Entscheidungsdiagrammen und Anwendungen im Schaltkreisentwurf},
school = {University of Freiburg, Freiburg im Breisgau, Germany},
year = {2001},
url = {https://d-nb.info/963675761},
timestamp = {Sat, 17 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/dnb/Gunther01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DrechslerG01,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther},
title = {History-based dynamic {BDD} minimization},
journal = {Integr.},
volume = {31},
number = {1},
pages = {51--63},
year = {2001},
url = {https://doi.org/10.1016/S0167-9260(01)00021-9},
doi = {10.1016/S0167-9260(01)00021-9},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DrechslerG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerGS01,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Fabio Somenzi},
title = {Using lower bounds during dynamic {BDD} minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {51--57},
year = {2001},
url = {https://doi.org/10.1109/43.905674},
doi = {10.1109/43.905674},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerGS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GuntherHB01,
author = {Wolfgang G{\"{u}}nther and
Andreas Hett and
Bernd Becker},
editor = {Satoshi Goto},
title = {Application of linearly transformed BDDs in sequential verification},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {91--96},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370286},
doi = {10.1145/370155.370286},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/GuntherHB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PoliaGB01,
author = {Ilia Polian and
Wolfgang G{\"{u}}nther and
Bernd Becker},
title = {Efficient Pattern-Based Verification of Connections to {IP} Cores},
booktitle = {10th Asian Test Symposium {(ATS} 2001), 19-21 November 2001, Kyoto,
Japan},
pages = {443--448},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ATS.2001.990324},
doi = {10.1109/ATS.2001.990324},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PoliaGB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/BeckerEDG01,
author = {Bernd Becker and
Thomas Eschbach and
Rolf Drechsler and
Wolfgang G{\"{u}}nther},
title = {Greedy{\_}IIP: Partitioning Large Graphs by Greedy Iterative Improvement},
booktitle = {Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001),
4-6 September 2001, Warsaw, Poland},
pages = {54--61},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DSD.2001.952117},
doi = {10.1109/DSD.2001.952117},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/BeckerEDG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/DrechslerGLA01,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Lothar Linhard and
Gerhard Angst},
title = {Level Assignment for Displaying Combinational Logic},
booktitle = {Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001),
4-6 September 2001, Warsaw, Poland},
pages = {148--151},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DSD.2001.952262},
doi = {10.1109/DSD.2001.952262},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/DrechslerGLA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/SchmiedleGD01,
author = {Frank Schmiedle and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Selection of Efficient Re-Ordering Heuristics for {MDD} Construction},
booktitle = {31st {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2001, Warsaw, Poland, May 22-24, 2001, Proceedings},
pages = {299--304},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ISMVL.2001.924587},
doi = {10.1109/ISMVL.2001.924587},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/SchmiedleGD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/PolianGB01,
author = {Ilia Polian and
Wolfgang G{\"{u}}nther and
Bernd Becker},
editor = {Dieter Monjau},
title = {Efficient Pattern-Based Verification of Connections to Intellectual
Property Cores},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Mei{\ss}en, Germany, February
19-21, 2001},
pages = {111--120},
publisher = {MoPress},
year = {2001},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/PolianGB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GuntherD01,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Implementation of Read- k-times BDDs on Top of Standard {BDD} Packages},
booktitle = {14th International Conference on {VLSI} Design {(VLSI} Design 2001),
3-7 January 2001, Bangalore, India},
pages = {173--178},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICVD.2001.902657},
doi = {10.1109/ICVD.2001.902657},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GuntherD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GuntherD01a,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Performance Driven Optimization for {MUX} based FPGAs},
booktitle = {14th International Conference on {VLSI} Design {(VLSI} Design 2001),
3-7 January 2001, Bangalore, India},
pages = {311--316},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICVD.2001.902678},
doi = {10.1109/ICVD.2001.902678},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GuntherD01a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipl/GuntherD00,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {On the computational power of linearly transformed BDDs},
journal = {Inf. Process. Lett.},
volume = {75},
number = {3},
pages = {119--125},
year = {2000},
url = {https://doi.org/10.1016/S0020-0190(00)00083-1},
doi = {10.1016/S0020-0190(00)00083-1},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipl/GuntherD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/GuntherD00,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {ACTion: Combining logic synthesis and technology mapping for MUX-based
FPGAs},
journal = {J. Syst. Archit.},
volume = {46},
number = {14},
pages = {1321--1334},
year = {2000},
url = {https://doi.org/10.1016/S1383-7621(00)00027-8},
doi = {10.1016/S1383-7621(00)00027-8},
timestamp = {Tue, 19 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/GuntherD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerDG00,
author = {Rolf Drechsler and
Nicole Drechsler and
Wolfgang G{\"{u}}nther},
title = {Fast exact minimization of BDD's},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {19},
number = {3},
pages = {384--389},
year = {2000},
url = {https://doi.org/10.1109/43.833206},
doi = {10.1109/43.833206},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerDG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/GuntherDDB00,
author = {Wolfgang G{\"{u}}nther and
Nicole Drechsler and
Rolf Drechsler and
Bernd Becker},
title = {Verification of Designs Containing Black Boxes},
booktitle = {26th {EUROMICRO} 2000 Conference, Informatics: Inventing the Future,
5-7 September 2000, Maastricht, The Netherlands},
pages = {1100--1105},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/EURMIC.2000.874621},
doi = {10.1109/EURMIC.2000.874621},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/GuntherDDB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/GuntherD00,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {ACTion: Combining Logic Synthesis and Technology Mapping for {MUX}
Based FPGAs},
booktitle = {26th {EUROMICRO} 2000 Conference, Informatics: Inventing the Future,
5-7 September 2000, Maastricht, The Netherlands},
pages = {1130--1137},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.ieeecomputersociety.org/10.1109/EUROMICRO.2000.10007},
doi = {10.1109/EUROMICRO.2000.10007},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/GuntherD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/DrechslerGB00,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Bernd Becker},
title = {Testability of Circuits Derived from Lattice Diagrams},
booktitle = {26th {EUROMICRO} 2000 Conference, Informatics: Inventing the Future,
5-7 September 2000, Maastricht, The Netherlands},
pages = {1188--1192},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/EURMIC.2000.874632},
doi = {10.1109/EURMIC.2000.874632},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/DrechslerGB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gd/GuntherSBM00,
author = {Wolfgang G{\"{u}}nther and
Robby Sch{\"{o}}nfeld and
Bernd Becker and
Paul Molitor},
editor = {Joe Marks},
title = {\emph{k}-Layer Straightline Crossing Minimization by Speeding Up Sifting},
booktitle = {Graph Drawing, 8th International Symposium, {GD} 2000, Colonial Williamsburg,
VA, USA, September 20-23, 2000, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1984},
pages = {253--258},
publisher = {Springer},
year = {2000},
url = {https://doi.org/10.1007/3-540-44541-2\_24},
doi = {10.1007/3-540-44541-2\_24},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/gd/GuntherSBM00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/GuntherD00,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
editor = {L. Darrell Whitley and
David E. Goldberg and
Erick Cant{\'{u}}{-}Paz and
Lee Spector and
Ian C. Parmee and
Hans{-}Georg Beyer},
title = {Improving EAs for Sequencing Problems},
booktitle = {Proceedings of the Genetic and Evolutionary Computation Conference
{(GECCO} '00), Las Vegas, Nevada, USA, July 8-12, 2000},
pages = {175--180},
publisher = {Morgan Kaufmann},
year = {2000},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/gecco/GuntherD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/DrechslerG00,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther},
editor = {L. Darrell Whitley and
David E. Goldberg and
Erick Cant{\'{u}}{-}Paz and
Lee Spector and
Ian C. Parmee and
Hans{-}Georg Beyer},
title = {Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints},
booktitle = {Proceedings of the Genetic and Evolutionary Computation Conference
{(GECCO} '00), Las Vegas, Nevada, USA, July 8-12, 2000},
pages = {513--518},
publisher = {Morgan Kaufmann},
year = {2000},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/gecco/DrechslerG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/GuntherDH00,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler and
Stefan H{\"{o}}reth},
title = {Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound
Computation},
booktitle = {Proceedings of the {IEEE} International Conference On Computer Design:
{VLSI} In Computers {\&} Processors, {ICCD} '00, Austin, Texas,
USA, September 17-20, 2000},
pages = {383--388},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCD.2000.878312},
doi = {10.1109/ICCD.2000.878312},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/GuntherDH00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DrechslerG00,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther},
title = {Optimization of sequential verification by history-based dynamic minimization
of BDDs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
May 2000, Proceedings},
pages = {737--740},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ISCAS.2000.858857},
doi = {10.1109/ISCAS.2000.858857},
timestamp = {Fri, 13 Aug 2021 09:26:01 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DrechslerG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/JankovicGD00,
author = {Dragan Jankovic and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Lower Bound Sifting for MDDs},
booktitle = {30th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings},
pages = {193--198},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISMVL.2000.848619},
doi = {10.1109/ISMVL.2000.848619},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ismvl/JankovicGD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/SchmiedleGD00,
author = {Frank Schmiedle and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Dynamic Re-Encoding During {MDD} Minimization},
booktitle = {30th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings},
pages = {239--244},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISMVL.2000.848626},
doi = {10.1109/ISMVL.2000.848626},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/SchmiedleGD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/ThorntonDG00,
author = {Mitchell A. Thornton and
Rolf Drechsler and
Wolfgang G{\"{u}}nther},
title = {A Method for Approximate Equivalence Checking},
booktitle = {30th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings},
pages = {447--452},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISMVL.2000.848656},
doi = {10.1109/ISMVL.2000.848656},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/ThorntonDG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/Drechsler0000,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Bernd Becker},
title = {Testability of Circuits Derived from Lattice Diagrams},
booktitle = {1st Latin American Test Workshop, {LATW} 2000, Rio de Janeiro, RJ,
Brazil, March 13-15, 2000},
pages = {77--81},
publisher = {{IEEE}},
year = {2000},
timestamp = {Tue, 25 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/latw/Drechsler0000.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/GuntherDDB00,
author = {Wolfgang G{\"{u}}nther and
Nicole Drechsler and
Rolf Drechsler and
Bernd Becker},
editor = {Klaus Waldschmidt and
Christoph Grimm},
title = {Verification of Designs Containing Black Boxes},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February
28 - March 1, 2000},
pages = {19--26},
publisher = {{VDE}},
year = {2000},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/GuntherDDB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GuntherD99,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Minimization of Free BDDs},
booktitle = {Proceedings of the 1999 Conference on Asia South Pacific Design Automation,
Wanchai, Hong Kong, China, January 18-21, 1999},
pages = {323--326},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ASPDAC.1999.760024},
doi = {10.1109/ASPDAC.1999.760024},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/GuntherD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DrechslerG99,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther},
editor = {Mary Jane Irwin},
title = {Using Lower Bounds During Dynamic {BDD} Minimization},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {29--32},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.309858},
doi = {10.1145/309847.309858},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DrechslerG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/DrechslerG99,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther},
title = {Generation of Optimal Universal Logic Modules},
booktitle = {25th {EUROMICRO} '99 Conference, Informatics: Theory and Practice
for the New Millenium, 8-10 September 1999, Milan, Italy},
pages = {1080--1085},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/EURMIC.1999.794451},
doi = {10.1109/EURMIC.1999.794451},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/DrechslerG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fuzzy/DrechslerGD99,
author = {Nicole Drechsler and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
editor = {Bernd Reusch},
title = {Efficient Graph Coloring by Evolutionary Algorithms},
booktitle = {Computational Intelligence, Theory and Applications, International
Conference, 6th Fuzzy Days, Dortmund, Germany, May 25-28, 1999, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1625},
pages = {30--39},
publisher = {Springer},
year = {1999},
url = {https://doi.org/10.1007/3-540-48774-3\_4},
doi = {10.1007/3-540-48774-3\_4},
timestamp = {Tue, 14 May 2019 10:00:38 +0200},
biburl = {https://dblp.org/rec/conf/fuzzy/DrechslerGD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/GuntherD99,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
editor = {Jacob K. White and
Ellen Sentovich},
title = {Efficient manipulation algorithms for linearly transformed BDDs},
booktitle = {Proceedings of the 1999 {IEEE/ACM} International Conference on Computer-Aided
Design, 1999, San Jose, California, USA, November 7-11, 1999},
pages = {50--54},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCAD.1999.810620},
doi = {10.1109/ICCAD.1999.810620},
timestamp = {Mon, 08 May 2023 21:43:38 +0200},
biburl = {https://dblp.org/rec/conf/iccad/GuntherD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip10-5/DrechslerG99,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther},
editor = {L. Miguel Silveira and
Srinivas Devadas and
Ricardo Augusto da Luz Reis},
title = {History-Based Dynamic Minimization During {BDD} Construction},
booktitle = {{VLSI:} Systems on a Chip, {IFIP} {TC10/WG10.5} Tenth International
Conference on Very Large Scale Integration {(VLSI} '99), December
1-4, 1999, Lisbon, Portugal},
series = {{IFIP} Conference Proceedings},
volume = {162},
pages = {334--345},
publisher = {Kluwer},
year = {1999},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ifip10-5/DrechslerG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GuntherD99,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Minimization of BDDs using linear transformations based on evolutionary
techniques},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {387--390},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.777884},
doi = {10.1109/ISCAS.1999.777884},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GuntherD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GuntherD99a,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Creating hard problem instances in logic synthesis using exact minimization},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {436--439},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.780188},
doi = {10.1109/ISCAS.1999.780188},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/GuntherD99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DrechslerDG98,
author = {Rolf Drechsler and
Nicole Drechsler and
Wolfgang G{\"{u}}nther},
editor = {Basant R. Chawla and
Randal E. Bryant and
Jan M. Rabaey},
title = {Fast Exact Minimization of BDDs},
booktitle = {Proceedings of the 35th Conference on Design Automation, Moscone center,
San Francico, California, USA, June 15-19, 1998},
pages = {200--205},
publisher = {{ACM} Press},
year = {1998},
url = {https://doi.org/10.1145/277044.277099},
doi = {10.1145/277044.277099},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DrechslerDG98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GuntherD98,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Linear Transformations and Exact Minimization of BDDs},
booktitle = {8th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '98), 19-21 February
1998, Lafayette, LA, {USA}},
pages = {325--330},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/GLSV.1998.665287},
doi = {10.1109/GLSV.1998.665287},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/GuntherD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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