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ORCIDBibTeX records: Joshua Friedrich
@article{DBLP:journals/jssc/GonzalezFFRDSRH18,
author = {Christopher J. Gonzalez and
Michael S. Floyd and
Eric Fluhr and
Phillip J. Restle and
Daniel Dreps and
Michael A. Sperling and
Rahul M. Rao and
David Hogenmiller and
Christos Vezyrtzis and
Pierce Chuang and
Daniel Lewis and
Ricardo Escobar and
Vinod Ramadurai and
Ryan Kruse and
Juergen Pille and
Ryan Nett and
Pawel Owczarczyk and
Joshua Friedrich and
Jose Paredes and
Timothy Diemoz and
Md. Saiful Islam and
Donald W. Plass and
Paul Muench},
title = {The 24-Core {POWER9} Processor With Adaptive Clocking, 25-Gb/s Accelerator
Links, and 16-Gb/s PCIe Gen4},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {1},
pages = {91--101},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2017.2748623},
doi = {10.1109/JSSC.2017.2748623},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/GonzalezFFRDSRH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FloydRSOFFMDCV17,
author = {Michael S. Floyd and
Phillip J. Restle and
Michael A. Sperling and
Pawel Owczarczyk and
Eric J. Fluhr and
Joshua Friedrich and
Paul Muench and
Timothy Diemoz and
Pierce Chuang and
Christos Vezyrtzis},
title = {26.5 Adaptive clocking in the POWER9{\texttrademark} processor for
voltage droop protection},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {444--445},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870452},
doi = {10.1109/ISSCC.2017.7870452},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FloydRSOFFMDCV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/ZyubanFDPPRDZCI15,
author = {Victor V. Zyuban and
Joshua Friedrich and
Daniel M. Dreps and
J{\"{u}}rgen Pille and
Donald W. Plass and
Phillip J. Restle and
Zeynep Toprak Deniz and
Matthew M. Ziegler and
Sam G. Chu and
Md. Saiful Islam and
James D. Warnock and
Bob Philhower and
Rahul M. Rao and
Gregory S. Still and
David Shan and
Eric Fluhr and
Jose Paredes and
Dieter F. Wendel and
Christopher J. Gonzalez and
D. Hogenmiller and
Ruchir Puri and
Scott A. Taylor and
Stephen D. Posluszny},
title = {{IBM} {POWER8} circuit design and energy optimization},
journal = {{IBM} J. Res. Dev.},
volume = {59},
number = {1},
year = {2015},
url = {https://doi.org/10.1147/JRD.2014.2380200},
doi = {10.1147/JRD.2014.2380200},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/ZyubanFDPPRDZCI15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15,
author = {Eric J. Fluhr and
Steve Baumgartner and
David W. Boerstler and
John F. Bulzacchelli and
Timothy Diemoz and
Daniel Dreps and
George English and
Joshua Friedrich and
Anne Gattiker and
Tilman Gloekler and
Christopher J. Gonzalez and
Jason Hibbeler and
Keith A. Jenkins and
Yong Kim and
Paul Muench and
Ryan Nett and
Jose Paredes and
Juergen Pille and
Donald W. Plass and
Phillip J. Restle and
Raphael Robertazzi and
David Shan and
David W. Siljenberg and
Michael A. Sperling and
Kevin Stawiasz and
Gregory S. Still and
Zeynep Toprak Deniz and
James D. Warnock and
Glen A. Wiedemeier and
Victor V. Zyuban},
title = {The 12-Core POWER8{\texttrademark} Processor With 7.6 Tb/s {IO} Bandwidth,
Integrated Voltage Regulation, and Resonant Clocking},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {1},
pages = {10--23},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2014.2358553},
doi = {10.1109/JSSC.2014.2358553},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/FluhrBBBDDEFGGGHJKMNPPPRRSSSSSDWWZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icicdt/FriedrichLSSSFD14,
author = {Joshua Friedrich and
Hung Q. Le and
William J. Starke and
Jeff Stuecheli and
Balaram Sinharoy and
Eric J. Fluhr and
Daniel M. Dreps and
Victor V. Zyuban and
Gregory S. Still and
Christopher J. Gonzalez and
David Hogenmiller and
Frank Malgioglio and
Ryan Nett and
Ruchir Puri and
Phillip J. Restle and
David Shan and
Zeynep Toprak Deniz and
Dieter F. Wendel and
Matthew M. Ziegler and
Dave W. Victor},
title = {The POWER8\({}^{\mbox{TM}}\) processor: Designed for big data, analytics,
and cloud environments},
booktitle = {2014 {IEEE} International Conference on {IC} Design {\&} Technology,
{ICICDT} 2014, Austin, TX, USA, May 28-30, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICICDT.2014.6838618},
doi = {10.1109/ICICDT.2014.6838618},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icicdt/FriedrichLSSSFD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FluhrFDZSGHHMNP14,
author = {Eric J. Fluhr and
Joshua Friedrich and
Daniel M. Dreps and
Victor V. Zyuban and
Gregory S. Still and
Christopher J. Gonzalez and
Allen Hall and
David Hogenmiller and
Frank Malgioglio and
Ryan Nett and
Jose Paredes and
Juergen Pille and
Donald W. Plass and
Ruchir Puri and
Phillip J. Restle and
David Shan and
Kevin Stawiasz and
Zeynep Toprak Deniz and
Dieter F. Wendel and
Matthew M. Ziegler},
title = {5.1 POWER8\({}^{\mbox{TM}}\): {A} 12-core server-class processor in
22nm {SOI} with 7.6Tb/s off-chip bandwidth},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {96--97},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757353},
doi = {10.1109/ISSCC.2014.6757353},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/FluhrFDZSGHHMNP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/DenizSBSKKBGRSD14,
author = {Zeynep Toprak Deniz and
Michael A. Sperling and
John F. Bulzacchelli and
Gregory S. Still and
Ryan Kruse and
Seongwon Kim and
David Boerstler and
Tilman Gloekler and
Raphael Robertazzi and
Kevin Stawiasz and
Tim Diemoz and
George English and
David Hui and
Paul Muench and
Joshua Friedrich},
title = {5.2 Distributed system of digitally controlled microregulators enabling
per-core {DVFS} for the POWER8\({}^{\mbox{TM}}\) microprocessor},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {98--99},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757354},
doi = {10.1109/ISSCC.2014.6757354},
timestamp = {Mon, 10 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/DenizSBSKKBGRSD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/RestleSHKDHBSJF14,
author = {Phillip J. Restle and
David Shan and
David Hogenmiller and
Yong Kim and
Alan J. Drake and
Jason Hibbeler and
Thomas J. Bucelot and
Gregory S. Still and
Keith A. Jenkins and
Joshua Friedrich},
title = {5.3 Wide-frequency-range resonant clock with on-the-fly mode changing
for the POWER8\({}^{\mbox{TM}}\) microprocessor},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {100--101},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757355},
doi = {10.1109/ISSCC.2014.6757355},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/RestleSHKDHBSJF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/ZyubanTCHGFCTR13,
author = {Victor V. Zyuban and
Scott A. Taylor and
Birger Christensen and
A. R. Hall and
Christopher J. Gonzalez and
Joshua Friedrich and
Frances Clougherty and
Jon Tetzloff and
Rajeev R. Rao},
title = {{IBM} {POWER7+} design for higher frequency at fixed power},
journal = {{IBM} J. Res. Dev.},
volume = {57},
number = {6},
year = {2013},
url = {https://doi.org/10.1147/JRD.2013.2279597},
doi = {10.1147/JRD.2013.2279597},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/ZyubanTCHGFCTR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FriedrichS12,
author = {Joshua Friedrich and
Jinuk Luke Shin},
title = {Session 3 overview: Processors: High performance digital subcommittee},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {54--55},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6177122},
doi = {10.1109/ISSCC.2012.6177122},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FriedrichS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KosonockySBCKF12,
author = {Stephen Kosonocky and
Vladimir Stojanovic and
Kees van Berkel and
Ming{-}Yang Chao and
Tobias Knoll and
Joshua Friedrich},
title = {Power/performance optimization of many-core processor SoCs},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {508--509},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6177118},
doi = {10.1109/ISSCC.2012.6177118},
timestamp = {Thu, 09 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KosonockySBCKF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FujimoriCFS12,
author = {Ichiro Fujimori and
SeongHwan Cho and
Joshua Friedrich and
John T. Stonick},
title = {Optical {PCB} interconnects, Niche or mainstream?},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {516},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6177111},
doi = {10.1109/ISSCC.2012.6177111},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/FujimoriCFS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/FriedrichPBBDHHKKKLLMNOPQRRRRRRST11,
author = {Joshua Friedrich and
Ruchir Puri and
Uwe Brandt and
Markus B{\"{u}}hler and
Jack DiLullo and
Jeremy Hopkins and
Mozammel Hossain and
Michael A. Kazda and
Joachim Keinert and
Zahi M. Kurzum and
Douglass Lamb and
Alice Lee and
Frank Musante and
Jens Noack and
Peter J. Osler and
Stephen D. Posluszny and
Haifeng Qian and
Shyam Ramji and
Vasant B. Rao and
Lakshmi N. Reddy and
Haoxing Ren and
Thomas E. Rosser and
Benjamin R. Russell and
Cliff C. N. Sze and
Gustavo E. T{\'{e}}llez},
title = {Design methodology for the {IBM} {POWER7} microprocessor},
journal = {{IBM} J. Res. Dev.},
volume = {55},
number = {3},
pages = {9},
year = {2011},
url = {https://doi.org/10.1147/JRD.2011.2105692},
doi = {10.1147/JRD.2011.2105692},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/FriedrichPBBDHHKKKLLMNOPQRRRRRRST11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WendelKWCCCDHFIKLMPPRSSSTNWWZ11,
author = {Dieter F. Wendel and
Ronald N. Kalla and
James D. Warnock and
Robert Cargnoni and
Sam G. Chu and
Joachim G. Clabes and
Daniel Dreps and
David Hrusecky and
Joshua Friedrich and
Md. Saiful Islam and
James A. Kahle and
Jens Leenstra and
Gaurav Mittal and
Jose Paredes and
Juergen Pille and
Phillip J. Restle and
Balaram Sinharoy and
George Smith and
William J. Starke and
Scott A. Taylor and
James Van Norstrand and
Stephen Weitzel and
Phillip G. Williams and
Victor V. Zyuban},
title = {POWER7{\texttrademark}, a Highly Parallel, Scalable Multi-Core High
End Server Processor},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {1},
pages = {145--161},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2010.2080611},
doi = {10.1109/JSSC.2010.2080611},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/WendelKWCCCDHFIKLMPPRSSSTNWWZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WendelKCCFFKSSTWCIZ10,
author = {Dieter F. Wendel and
Ronald N. Kalla and
Robert Cargnoni and
Joachim G. Clabes and
Joshua Friedrich and
Roland Frech and
James A. Kahle and
Balaram Sinharoy and
William J. Starke and
Scott A. Taylor and
Steve Weitzel and
Sam G. Chu and
Md. Saiful Islam and
Victor V. Zyuban},
title = {The implementation of POWER7\({}^{\mbox{TM}}\): {A} highly parallel
and scalable multi-core high-end server processor},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {102--103},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5434074},
doi = {10.1109/ISSCC.2010.5434074},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WendelKCCFFKSSTWCIZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WarnockSWMFZCK10,
author = {James D. Warnock and
Leon J. Sigal and
Dieter F. Wendel and
K. Paul Muller and
Joshua Friedrich and
Victor V. Zyuban and
Ethan H. Cannon and
A. J. KleinOsowski},
title = {POWER7\({}^{\mbox{TM}}\) local clocking and clocked storage elements},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {178--179},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5433995},
doi = {10.1109/ISSCC.2010.5433995},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WarnockSWMFZCK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ZieglerZGVF09,
author = {Matthew M. Ziegler and
Victor V. Zyuban and
George Gristede and
Milena Vratonjic and
Joshua Friedrich},
editor = {J{\"{o}}rg Henkel and
Ali Keshavarzi and
Naehyuck Chang and
Tahir Ghani},
title = {The opportunity cost of low power design: a case study in circuit
tuning},
booktitle = {Proceedings of the 2009 International Symposium on Low Power Electronics
and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009},
pages = {133--138},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1594233.1594265},
doi = {10.1145/1594233.1594265},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/ZieglerZGVF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/StoltMDMLFF08,
author = {Benjamin Stolt and
Yonatan Mittlefehldt and
Sanjay Dubey and
Gaurav Mittal and
Mike Lee and
Joshua Friedrich and
Eric Fluhr},
title = {Design and Implementation of the {POWER6} Microprocessor},
journal = {{IEEE} J. Solid State Circuits},
volume = {43},
number = {1},
pages = {21--28},
year = {2008},
url = {https://doi.org/10.1109/JSSC.2007.910963},
doi = {10.1109/JSSC.2007.910963},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/StoltMDMLFF08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/FranchRNHFDWGS08,
author = {Robert L. Franch and
Phillip J. Restle and
James K. Norman and
William V. Huott and
Joshua Friedrich and
R. Dixon and
Steve Weitzel and
K. van Goor and
Gerard Salem},
editor = {Douglas Young and
Nur A. Touba},
title = {On-chip Timing Uncertainty Measurements on {IBM} Microprocessors},
booktitle = {2008 {IEEE} International Test Conference, {ITC} 2008, Santa Clara,
California, USA, October 26-31, 2008},
pages = {1--7},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/TEST.2008.4700707},
doi = {10.1109/TEST.2008.4700707},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/FranchRNHFDWGS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/CurranFPSFCH07,
author = {Brian W. Curran and
Eric Fluhr and
Jose Paredes and
Leon J. Sigal and
Joshua Friedrich and
Yiu{-}Hing Chan and
Charlie Hwang},
title = {Power-constrained high-frequency circuits for the {IBM} {POWER6} microprocessor},
journal = {{IBM} J. Res. Dev.},
volume = {51},
number = {6},
pages = {715--732},
year = {2007},
url = {https://doi.org/10.1147/rd.516.0715},
doi = {10.1147/RD.516.0715},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/CurranFPSFCH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FriedrichMJHCFMCCPCLCRTDL07,
author = {Joshua Friedrich and
Bradley D. McCredie and
Norman K. James and
Bill Huott and
Brian W. Curran and
Eric Fluhr and
Gaurav Mittal and
Eddie Chan and
Yuen H. Chan and
Donald W. Plass and
Sam G. Chu and
Hung Q. Le and
Leo Clark and
John R. Ripley and
Scott A. Taylor and
Jack DiLullo and
Mary Yvonne Lanzerotti},
title = {Design of the Power6 Microprocessor},
booktitle = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2007, Digest of Technical Papers, San Francisco, CA, USA, February
11-15, 2007},
pages = {96--97},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISSCC.2007.373605},
doi = {10.1109/ISSCC.2007.373605},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FriedrichMJHCFMCCPCLCRTDL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/JamesRFHM07,
author = {Norman K. James and
Phillip J. Restle and
Joshua Friedrich and
Bill Huott and
Bradley D. McCredie},
title = {Comparison of Split-Versus Connected-Core Supplies in the {POWER6}
Microprocessor},
booktitle = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2007, Digest of Technical Papers, San Francisco, CA, USA, February
11-15, 2007},
pages = {298--604},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISSCC.2007.373412},
doi = {10.1109/ISSCC.2007.373412},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/JamesRFHM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/FranchRNHFDWGS07,
author = {Robert L. Franch and
Phillip J. Restle and
James K. Norman and
William V. Huott and
Joshua Friedrich and
R. Dixon and
Steve Weitzel and
K. van Goor and
Gerard Salem},
editor = {Jill Sibert and
Janusz Rajski},
title = {On-chip timing uncertainty measurements on {IBM} microprocessors},
booktitle = {2007 {IEEE} International Test Conference, {ITC} 2007, Santa Clara,
California, USA, October 21-26, 2007},
pages = {1--7},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/TEST.2007.4437560},
doi = {10.1109/TEST.2007.4437560},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/FranchRNHFDWGS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ClabesFSDCPDMPFSLGWSRGRKMD04,
author = {Joachim G. Clabes and
Joshua Friedrich and
Mark Sweet and
Jack DiLullo and
Sam G. Chu and
Donald W. Plass and
James Dawson and
Paul Muench and
Larry Powell and
Michael S. Floyd and
Balaram Sinharoy and
Mike Lee and
Michael Goulet and
James Wagoner and
Nicole S. Schwartz and
Stephen L. Runyon and
Gary Gorman and
Phillip J. Restle and
Ronald N. Kalla and
Joseph McGill and
J. Steve Dodson},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {Design and implementation of the {POWER5} microprocessor},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {670--672},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996749},
doi = {10.1145/996566.996749},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ClabesFSDCPDMPFSLGWSRGRKMD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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