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ORCIDBibTeX records: Rolf Drechsler
@inproceedings{DBLP:conf/vlsid/LahiriKMBBSBBWD24,
author = {Sneha Lahiri and
Megha Kesh and
Rupsa Mandal and
Anirban Bhattacharjee and
Sovan Bhattacharya and
Dola Sinha and
Chandan Bandyopadhyay and
Laxmidhar Biswal and
Robert Wille and
Rolf Drechsler},
title = {A Dynamic Programming Based Graph Traversal Approach for Efficient
Implementation of Nearest Neighbor Architecture in 2D},
booktitle = {37th International Conference on {VLSI} Design and 23rd International
Conference on Embedded Systems, {VLSID} 2024, Kolkata, India, January
6-10, 2024},
pages = {306--311},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/VLSID60093.2024.00057},
doi = {10.1109/VLSID60093.2024.00057},
timestamp = {Mon, 08 Apr 2024 20:48:39 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/LahiriKMBBSBBWD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ShirinzadehDSKDD24,
author = {Fatemeh Shirinzadeh and
Arighna Deb and
Saeideh Shirinzadeh and
Abhoy Kole and
Kamalika Datta and
Rolf Drechsler},
title = {In-Memory SAT-Solver for Self-Verification of Programmable Memristive
Architectures},
booktitle = {37th International Conference on {VLSI} Design and 23rd International
Conference on Embedded Systems, {VLSID} 2024, Kolkata, India, January
6-10, 2024},
pages = {384--389},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/VLSID60093.2024.00070},
doi = {10.1109/VLSID60093.2024.00070},
timestamp = {Mon, 08 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/ShirinzadehDSKDD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/BendeSJKCBZNPDWMR24,
author = {Ankit Bende and
Simranjeet Singh and
Chandan Kumar Jha and
Tim Kempen and
Felix C{\"{u}}ppers and
Christopher Bengel and
Andre Zambanini and
Dennis Nielinger and
Sachin B. Patkar and
Rolf Drechsler and
Rainer Waser and
Farhad Merchant and
Vikas Rana},
title = {Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx {RRAM}
Crossbar Array},
booktitle = {37th International Conference on {VLSI} Design and 23rd International
Conference on Embedded Systems, {VLSID} 2024, Kolkata, India, January
6-10, 2024},
pages = {565--570},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/VLSID60093.2024.00100},
doi = {10.1109/VLSID60093.2024.00100},
timestamp = {Mon, 08 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/BendeSJKCBZNPDWMR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/JhaAD24,
author = {Chandan Kumar Jha and
Sallar Ahmadi{-}Pour and
Rolf Drechsler},
title = {Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided
Logic},
booktitle = {37th International Conference on {VLSI} Design and 23rd International
Conference on Embedded Systems, {VLSID} 2024, Kolkata, India, January
6-10, 2024},
pages = {577--582},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/VLSID60093.2024.00102},
doi = {10.1109/VLSID60093.2024.00102},
timestamp = {Mon, 08 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/JhaAD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/SinghJBTRPDM23,
author = {Simranjeet Singh and
Chandan Kumar Jha and
Ankit Bende and
Phrangboklang Lyngton Thangkhiew and
Vikas Rana and
Sachin B. Patkar and
Rolf Drechsler and
Farhad Merchant},
title = {Should We Even Optimize for Execution Energy? Rethinking Mapping for
{MAGIC} Design Style},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {15},
number = {4},
pages = {230--233},
year = {2023},
url = {https://doi.org/10.1109/LES.2023.3298740},
doi = {10.1109/LES.2023.3298740},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/esl/SinghJBTRPDM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iotj/TempelHD23,
author = {S{\"{o}}ren Tempel and
Vladimir Herdt and
Rolf Drechsler},
title = {Specification-Based Symbolic Execution for Stateful Network Protocol
Implementations in IoT},
journal = {{IEEE} Internet Things J.},
volume = {10},
number = {11},
pages = {9544--9555},
year = {2023},
url = {https://doi.org/10.1109/JIOT.2023.3236694},
doi = {10.1109/JIOT.2023.3236694},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iotj/TempelHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/it/DattaDKD23,
author = {Kamalika Datta and
Arighna Deb and
Abhoy Kole and
Rolf Drechsler},
title = {Impact of sneak paths on in-memory logic design in memristive crossbars},
journal = {it Inf. Technol.},
volume = {65},
number = {1-2},
pages = {29--39},
year = {2023},
url = {https://doi.org/10.1515/itit-2023-0020},
doi = {10.1515/ITIT-2023-0020},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/it/DattaDKD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasII/JhaAD23,
author = {Chandan Kumar Jha and
Sallar Ahmadi{-}Pour and
Rolf Drechsler},
title = {{MARADIV:} Library of MAGIC-Based Approximate Restoring Array Divider
Benchmark Circuits for In-Memory Computing Using Memristors},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {70},
number = {7},
pages = {2635--2639},
year = {2023},
url = {https://doi.org/10.1109/TCSII.2023.3242976},
doi = {10.1109/TCSII.2023.3242976},
timestamp = {Thu, 13 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasII/JhaAD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DebD0SD23,
author = {Arighna Deb and
Kamalika Datta and
Muhammad Hassan and
Saeideh Shirinzadeh and
Rolf Drechsler},
editor = {Atsushi Takahashi},
title = {Automated Equivalence Checking Method for Majority Based In-Memory
Computing on ReRAM Crossbars},
booktitle = {Proceedings of the 28th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2023, Tokyo, Japan, January 16-19, 2023},
pages = {19--25},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3566097.3567842},
doi = {10.1145/3566097.3567842},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/DebD0SD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KraussGD23,
author = {Rune Krauss and
Mehran Goli and
Rolf Drechsler},
editor = {Atsushi Takahashi},
title = {{EDDY:} {A} Multi-Core {BDD} Package with Dynamic Memory Management
and Reduced Fragmentation},
booktitle = {Proceedings of the 28th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2023, Tokyo, Japan, January 16-19, 2023},
pages = {423--428},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3566097.3567913},
doi = {10.1145/3566097.3567913},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KraussGD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ParvinGTD23,
author = {Sajjad Parvin and
Mehran Goli and
Frank Sill Torres and
Rolf Drechsler},
editor = {Atsushi Takahashi},
title = {Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans
- {A} {RISC-V} Case Study},
booktitle = {Proceedings of the 28th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2023, Tokyo, Japan, January 16-19, 2023},
pages = {683--689},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3566097.3567919},
doi = {10.1145/3566097.3567919},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ParvinGTD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/birthday/MahzoonD23,
author = {Alireza Mahzoon and
Rolf Drechsler},
editor = {Anne E. Haxthausen and
Wen{-}ling Huang and
Markus Roggenbach},
title = {Polynomial Formal Verification of Complex Circuits Using a Hybrid
Proof Engine},
booktitle = {Applicable Formal Methods for Safe Industrial Products - Essays Dedicated
to Jan Peleska on the Occasion of His 65th Birthday},
series = {Lecture Notes in Computer Science},
volume = {14165},
pages = {308--319},
publisher = {Springer},
year = {2023},
url = {https://doi.org/10.1007/978-3-031-40132-9\_19},
doi = {10.1007/978-3-031-40132-9\_19},
timestamp = {Sun, 24 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/birthday/MahzoonD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/coins/ParvinAJTD23,
author = {Sajjad Parvin and
Sallar Ahmadi{-}Pour and
Chandan Kumar Jha and
Frank Sill Torres and
Rolf Drechsler},
title = {Lo-RISK: Design of a Low Optical Leakage and High Performance {RISC-V}
Core},
booktitle = {{IEEE} International Conference on Omni-layer Intelligent Systems,
{COINS} 2023, Berlin, Germany, July 23-25, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/COINS57856.2023.10189332},
doi = {10.1109/COINS57856.2023.10189332},
timestamp = {Fri, 04 Aug 2023 13:58:10 +0200},
biburl = {https://dblp.org/rec/conf/coins/ParvinAJTD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BrunsHD23,
author = {Niklas Bruns and
Vladimir Herdt and
Rolf Drechsler},
title = {Processor Verification using Symbolic Execution: {A} {RISC-V} Case-Study},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137202},
doi = {10.23919/DATE56975.2023.10137202},
timestamp = {Wed, 07 Jun 2023 22:08:03 +0200},
biburl = {https://dblp.org/rec/conf/date/BrunsHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/CoskunHD23,
author = {Kemal {\c{C}}aglar Coskun and
Muhammad Hassan and
Rolf Drechsler},
title = {Equivalence Checking of System-Level and SPICE-Level Models of Static
Nonlinear Circuits},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137179},
doi = {10.23919/DATE56975.2023.10137179},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/CoskunHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DrechslerM23,
author = {Rolf Drechsler and
Alireza Mahzoon},
title = {Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial
Formal Verification of Complex Circuits},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137149},
doi = {10.23919/DATE56975.2023.10137149},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/DrechslerM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KleinekathoferMD23,
author = {Jan Kleinekath{\"{o}}fer and
Alireza Mahzoon and
Rolf Drechsler},
title = {Polynomial Formal Verification of Floating Point Adders},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137166},
doi = {10.23919/DATE56975.2023.10137166},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/KleinekathoferMD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KoleDDD23,
author = {Abhoy Kole and
Arighna Deb and
Kamalika Datta and
Rolf Drechsler},
title = {Extending the Design Space of Dynamic Quantum Circuits for Toffoli
based Network},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137250},
doi = {10.23919/DATE56975.2023.10137250},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/KoleDDD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ParvinGTD23,
author = {Sajjad Parvin and
Mehran Goli and
Frank Sill Torres and
Rolf Drechsler},
title = {FELOPi: {A} Framework for Simulation and Evaluation of Post-Layout
File Against Optical Probing},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137295},
doi = {10.23919/DATE56975.2023.10137295},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/ParvinGTD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/TrommerBMHMDHDRKDKSDKW23,
author = {Jens Trommer and
N. Bhattacharjee and
Thomas Mikolajick and
Sebastian Huhn and
Marcel Merten and
M. E. Djeridane and
Muhammad Hassan and
Rolf Drechsler and
Shubham Rai and
Nima Kavand and
Armin Darjani and
Akash Kumar and
V. Sessi and
M. Drescher and
S. Kolodinski and
M. Wiatr},
title = {Design Enablement Flow for Circuits with Inherent Obfuscation based
on Reconfigurable Transistors},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10136918},
doi = {10.23919/DATE56975.2023.10136918},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/TrommerBMHMDHDRKDKSDKW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/KraussGD23,
author = {Rune Krauss and
Mehran Goli and
Rolf Drechsler},
editor = {Maksim Jenihhin and
Hana Kub{\'{a}}tov{\'{a}} and
Nele Metens and
Jaan Raik and
Foisal Ahmed and
Jan Belohoubek},
title = {Efficient Binary Decision Diagram Manipulation by Reducing the Number
of Intermediate Nodes},
booktitle = {26th International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, {DDECS} 2023, Tallinn, Estonia, May 3-5, 2023},
pages = {73--78},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DDECS57882.2023.10139373},
doi = {10.1109/DDECS57882.2023.10139373},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/KraussGD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/MertenHD23,
author = {Marcel Merten and
Muhammad Hassan and
Rolf Drechsler},
editor = {Maksim Jenihhin and
Hana Kub{\'{a}}tov{\'{a}} and
Nele Metens and
Jaan Raik and
Foisal Ahmed and
Jan Belohoubek},
title = {Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean
Optimization Techniques},
booktitle = {26th International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, {DDECS} 2023, Tallinn, Estonia, May 3-5, 2023},
pages = {105--110},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DDECS57882.2023.10139590},
doi = {10.1109/DDECS57882.2023.10139590},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/MertenHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/HabibyHD23,
author = {Payam Habiby and
Sebastian Huhn and
Rolf Drechsler},
editor = {Luca Cassano and
Mihalis Psarakis and
Marcello Traiola and
Alberto Bosio},
title = {{RC-IJTAG:} {A} Methodology for Designing Remotely-Controlled {IEEE}
1687 Scan Networks},
booktitle = {{IEEE} International Symposium on Defect and Fault Tolerance in {VLSI}
and Nanotechnology Systems, {DFT} 2023, Juan-Les-Pins, France, October
3-5, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DFT59622.2023.10313568},
doi = {10.1109/DFT59622.2023.10313568},
timestamp = {Tue, 21 Nov 2023 12:38:06 +0100},
biburl = {https://dblp.org/rec/conf/dft/HabibyHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/ZhangGHD23,
author = {Weiyan Zhang and
Mehran Goli and
Muhammad Hassan and
Rolf Drechsler},
title = {Efficient ML-Based Performance Estimation Approach Across Different
Microarchitectures for {RISC-V} Processors},
booktitle = {26th Euromicro Conference on Digital System Design, {DSD} 2023, Golem,
Albania, September 6-8, 2023},
pages = {693--699},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DSD60849.2023.00099},
doi = {10.1109/DSD60849.2023.00099},
timestamp = {Tue, 02 Apr 2024 21:06:08 +0200},
biburl = {https://dblp.org/rec/conf/dsd/ZhangGHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/HabibyLWWHD23,
author = {Payam Habiby and
Natalia Lylina and
Chih{-}Hao Wang and
Hans{-}Joachim Wunderlich and
Sebastian Huhn and
Rolf Drechsler},
title = {Synthesis of {IJTAG} Networks for Multi-Power Domain Systems on Chips},
booktitle = {{IEEE} European Test Symposium, {ETS} 2023, Venezia, Italy, May 22-26,
2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ETS56758.2023.10174127},
doi = {10.1109/ETS56758.2023.10174127},
timestamp = {Fri, 14 Jul 2023 22:01:39 +0200},
biburl = {https://dblp.org/rec/conf/ets/HabibyLWWHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/MertenHD23,
author = {Marcel Merten and
Sebastian Huhn and
Rolf Drechsler},
title = {Increasing SAT-Resilience of Logic Locking Mechanisms using Formal
Methods},
booktitle = {{IEEE} European Test Symposium, {ETS} 2023, Venezia, Italy, May 22-26,
2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ETS56758.2023.10173975},
doi = {10.1109/ETS56758.2023.10173975},
timestamp = {Fri, 14 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ets/MertenHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/FunckAHD23,
author = {Milan Funck and
Sallar Ahmadi{-}Pour and
Vladimir Herdt and
Rolf Drechsler},
title = {Identification of ISA-Level Mutation-Classes for Qualification of
{RISC-V} Formal Verification},
booktitle = {Forum on Specification {\&} Design Languages, {FDL} 2023, Turin,
Italy, September 13-15, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FDL59689.2023.10272202},
doi = {10.1109/FDL59689.2023.10272202},
timestamp = {Fri, 20 Oct 2023 17:04:56 +0200},
biburl = {https://dblp.org/rec/conf/fdl/FunckAHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/MetzPBD23,
author = {Christopher A. Metz and
Christina Plump and
Bernhard J. Berger and
Rolf Drechsler},
title = {Hybrid {PTX} Analysis for {GPU} accelerated {CNN} inferencing aiding
Computer Architecture Design},
booktitle = {Forum on Specification {\&} Design Languages, {FDL} 2023, Turin,
Italy, September 13-15, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FDL59689.2023.10272088},
doi = {10.1109/FDL59689.2023.10272088},
timestamp = {Fri, 20 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/MetzPBD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/TempelBLD23,
author = {S{\"{o}}ren Tempel and
Tobias Brandt and
Christoph L{\"{u}}th and
Rolf Drechsler},
title = {Minimally Invasive Generation of {RISC-V} Instruction Set Simulators
from Formal {ISA} Models},
booktitle = {Forum on Specification {\&} Design Languages, {FDL} 2023, Turin,
Italy, September 13-15, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FDL59689.2023.10272224},
doi = {10.1109/FDL59689.2023.10272224},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fdl/TempelBLD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/ZielaskoD23,
author = {Jan Zielasko and
Rolf Drechsler},
title = {Virtual Prototype Driven Application Specific Hardware Optimization},
booktitle = {Forum on Specification {\&} Design Languages, {FDL} 2023, Turin,
Italy, September 13-15, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FDL59689.2023.10272131},
doi = {10.1109/FDL59689.2023.10272131},
timestamp = {Fri, 20 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/ZielaskoD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/MertenKD23,
author = {Marcel Merten and
Rune Krauss and
Rolf Drechsler},
editor = {Sara Silva and
Lu{\'{\i}}s Paquete},
title = {Scalable Neuroevolution of Ensemble Learners},
booktitle = {Companion Proceedings of the Conference on Genetic and Evolutionary
Computation, {GECCO} 2023, Companion Volume, Lisbon, Portugal, July
15-19, 2023},
pages = {667--670},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3583133.3590711},
doi = {10.1145/3583133.3590711},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/gecco/MertenKD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/PlumpBD23,
author = {Christina Plump and
Bernhard J. Berger and
Rolf Drechsler},
editor = {Sara Silva and
Lu{\'{\i}}s Paquete},
title = {Repetitive Processes and Their Surrogate-Model Congruent Encoding
for Evolutionary Algorithms - {A} Theoretic Proposal},
booktitle = {Companion Proceedings of the Conference on Genetic and Evolutionary
Computation, {GECCO} 2023, Companion Volume, Lisbon, Portugal, July
15-19, 2023},
pages = {2289--2296},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3583133.3596389},
doi = {10.1145/3583133.3596389},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/gecco/PlumpBD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gi/SteinmannNOPSD23,
author = {Lena Steinmann and
Dirk Nowotka and
Lea Oberl{\"{a}}nder and
Helen Pfuhl and
Heiner Stuckenschmidt and
Rolf Drechsler},
editor = {Maike Klein and
Daniel Krupka and
Cornelia Winter and
Volker Wohlgemuth},
title = {Workshop: "Aktuelle Entwicklungen und Perspektiven (an Hochschulen)
im Bereich Data Science"},
booktitle = {53. Jahrestagung der Gesellschaft f{\"{u}}r Informatik, {INFORMATIK}
2023, Designing Future - Zuk{\"{u}}nfte gestalten, Berlin, Germany
September 26-29, 2023},
series = {{LNI}},
volume = {{P-337}},
pages = {73--80},
publisher = {Gesellschaft f{\"{u}}r Informatik, Bonn},
year = {2023},
url = {https://doi.org/10.18420/inf2023\_05},
doi = {10.18420/INF2023\_05},
timestamp = {Fri, 08 Mar 2024 15:16:29 +0100},
biburl = {https://dblp.org/rec/conf/gi/SteinmannNOPSD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icaart/MeywerkHD23,
author = {Tim Meywerk and
Vladimir Herdt and
Rolf Drechsler},
editor = {Ana Paula Rocha and
Luc Steels and
H. Jaap van den Herik},
title = {Coverage-Guided Fuzzing for Plan-Based Robotics},
booktitle = {Proceedings of the 15th International Conference on Agents and Artificial
Intelligence, {ICAART} 2023, Volume 2, Lisbon, Portugal, February
22-24, 2023},
pages = {106--114},
publisher = {{SCITEPRESS}},
year = {2023},
url = {https://doi.org/10.5220/0011630600003393},
doi = {10.5220/0011630600003393},
timestamp = {Tue, 09 May 2023 16:56:47 +0200},
biburl = {https://dblp.org/rec/conf/icaart/MeywerkHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/MetzGD23,
author = {Christopher A. Metz and
Mehran Goli and
Rolf Drechsler},
title = {Fast and Accurate: Machine Learning Techniques for Performance Estimation
of CNNs for GPGPUs},
booktitle = {{IEEE} International Parallel and Distributed Processing Symposium,
{IPDPS} 2023 - Workshops, St. Petersburg, FL, USA, May 15-19, 2023},
pages = {754--760},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/IPDPSW59300.2023.00127},
doi = {10.1109/IPDPSW59300.2023.00127},
timestamp = {Wed, 09 Aug 2023 16:25:12 +0200},
biburl = {https://dblp.org/rec/conf/ipps/MetzGD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isdcs/DrechslerM23,
author = {Rolf Drechsler and
Alireza Mahzoon},
title = {Towards Polynomial Formal Verification of AI-Generated Arithmetic
Circuits},
booktitle = {International Symposium on Devices, Circuits and Systems, {ISDCS}
2023, Higashi-Hiroshima, Japan, May 29-31, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISDCS58735.2023.10153522},
doi = {10.1109/ISDCS58735.2023.10153522},
timestamp = {Fri, 30 Jun 2023 22:35:16 +0200},
biburl = {https://dblp.org/rec/conf/isdcs/DrechslerM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/DrechslerS23,
author = {Rolf Drechsler and
Martha Schnieber},
title = {Automated Polynomial Formal Verification: Human-Readable Proof Generation},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2023,
Ahmedabad, India, December 18-20, 2023},
pages = {1--3},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/iSES58672.2023.00012},
doi = {10.1109/ISES58672.2023.00012},
timestamp = {Tue, 02 Apr 2024 12:53:25 +0200},
biburl = {https://dblp.org/rec/conf/ises/DrechslerS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/DattaD23,
author = {Kamalika Datta and
Rolf Drechsler},
title = {Memristors: Device Modeling, Design and Verification},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2023,
Ahmedabad, India, December 18-20, 2023},
pages = {254--259},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/iSES58672.2023.00059},
doi = {10.1109/ISES58672.2023.00059},
timestamp = {Tue, 02 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ises/DattaD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/Coskun0GD23,
author = {Ece Nur Demirhan Coskun and
Muhammad Hassan and
Mehran Goli and
Rolf Drechsler},
title = {{VAST:} Validation of VP-based Heterogeneous Systems against Availability
Security Properties using Static Information Flow Tracking},
booktitle = {24th International Symposium on Quality Electronic Design, {ISQED}
2023, San Francisco, CA, USA, April 5-7, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISQED57927.2023.10129337},
doi = {10.1109/ISQED57927.2023.10129337},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/Coskun0GD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/WeingartenMGD23,
author = {Lennart Weingarten and
Alireza Mahzoon and
Mehran Goli and
Rolf Drechsler},
title = {Polynomial Formal Verification of a Processor: {A} {RISC-V} Case Study},
booktitle = {24th International Symposium on Quality Electronic Design, {ISQED}
2023, San Francisco, CA, USA, April 5-7, 2023},
pages = {1--7},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISQED57927.2023.10129397},
doi = {10.1109/ISQED57927.2023.10129397},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/WeingartenMGD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ParvinGKTSTD23,
author = {Sajjad Parvin and
Mehran Goli and
Thilo Krachenfels and
Shahin Tajik and
Jean{-}Pierre Seifert and
Frank Sill Torres and
Rolf Drechsler},
title = {{LAT-UP:} Exposing Layout-Level Analog Hardware Trojans Using Contactless
Optical Probing},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2023, Foz
do Iguacu, Brazil, June 20-23, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISVLSI59464.2023.10238545},
doi = {10.1109/ISVLSI59464.2023.10238545},
timestamp = {Wed, 13 Sep 2023 08:43:37 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/ParvinGKTSTD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mc/ImamMHD23,
author = {Sana Hassan Imam and
Christopher A. Metz and
Lars Hornuf and
Rolf Drechsler},
title = {Classifying Crowdsouring Platform Users' Engagement Behaviour using
Machine Learning and {XAI}},
booktitle = {Mensch und Computer 2023 - Workshopband, Rapperswil, Switzerland,
September 3-6, 2023},
publisher = {Gesellschaft f{\"{u}}r Informatik e.V.},
year = {2023},
url = {https://doi.org/10.18420/muc2023-mci-ws16-385},
doi = {10.18420/MUC2023-MCI-WS16-385},
timestamp = {Sun, 17 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mc/ImamMHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/SchnieberD23,
author = {Martha Schnieber and
Rolf Drechsler},
editor = {Reinhard von Hanxleden and
Stephen A. Edwards and
Jens Brandt and
Qi Zhu},
title = {Polynomial Formal Verification of {KFDD} Circuits},
booktitle = {21st {ACM-IEEE} International Symposium on Formal Methods and Models
for System Design, {MEMOCODE} 2023, Hamburg, Germany, September 21-22,
2023},
pages = {82--89},
publisher = {{ACM} / {IEEE}},
year = {2023},
url = {https://ieeexplore.ieee.org/document/10316220},
timestamp = {Fri, 15 Dec 2023 12:01:04 +0100},
biburl = {https://dblp.org/rec/conf/memocode/SchnieberD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/DrechslerS23,
author = {Rolf Drechsler and
Martha Schnieber},
editor = {Reinhard von Hanxleden and
Stephen A. Edwards and
Jens Brandt and
Qi Zhu},
title = {Next-Generation Automatic Human-Readable Proofs Enabling Polynomial
Formal Verification},
booktitle = {21st {ACM-IEEE} International Symposium on Formal Methods and Models
for System Design, {MEMOCODE} 2023, Hamburg, Germany, September 21-22,
2023},
pages = {122--125},
publisher = {{ACM} / {IEEE}},
year = {2023},
url = {https://ieeexplore.ieee.org/document/10316198},
timestamp = {Sat, 02 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/memocode/DrechslerS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nanoarch/WeingartenDD23,
author = {Lennart Weingarten and
Kamalika Datta and
Rolf Drechsler},
editor = {Ronald Tetzlaff and
Fernando Corinto and
Neil Kemp and
Alon Ascoli and
Andreas M{\"{o}}gel and
Meng{-}Fan Marvin Chang and
Joseph S. Friedman and
Siting Liu and
John Paul Strachan and
Stephan Menzel and
Mehdi B. Tahoori and
Martin Ziegler and
Jason Eshraghian and
Ioannis Messaris and
Christian Koitzsch and
Thomas Mikolajick and
Vasileios G. Ntinas},
title = {PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor},
booktitle = {Proceedings of the 18th {ACM} International Symposium on Nanoscale
Architectures, {NANOARCH} 2023, Dresden, Germany, December 18-20,
2023},
pages = {24:1--24:6},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3611315.3633262},
doi = {10.1145/3611315.3633262},
timestamp = {Sat, 10 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nanoarch/WeingartenDD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/newcas/DattaDSKSD23,
author = {Kamalika Datta and
Arighna Deb and
Fatemeh Shirinzadeh and
Abhoy Kole and
Saeideh Shirinzadeh and
Rolf Drechsler},
title = {Verification of In-Memory Logic Design using ReRAM Crossbars},
booktitle = {21st {IEEE} Interregional {NEWCAS} Conference, {NEWCAS} 2023, Edinburgh,
United Kingdom, June 26-28, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/NEWCAS57931.2023.10198121},
doi = {10.1109/NEWCAS57931.2023.10198121},
timestamp = {Tue, 15 Aug 2023 11:43:59 +0200},
biburl = {https://dblp.org/rec/conf/newcas/DattaDSKSD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/newcas/JhaD23,
author = {Chandan Kumar Jha and
Rolf Drechsler},
title = {Benchmarking Multiplier Architectures for {MAGIC} Based In-Memory
Computing},
booktitle = {21st {IEEE} Interregional {NEWCAS} Conference, {NEWCAS} 2023, Edinburgh,
United Kingdom, June 26-28, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/NEWCAS57931.2023.10198203},
doi = {10.1109/NEWCAS57931.2023.10198203},
timestamp = {Tue, 15 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/newcas/JhaD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/newcas/SinghGJRDSYPM23,
author = {Simranjeet Singh and
Omar Ghazal and
Chandan Kumar Jha and
Vikas Rana and
Rolf Drechsler and
Rishad A. Shafik and
Alex Yakovlev and
Sachin B. Patkar and
Farhad Merchant},
title = {Finite State Automata Design using 1T1R ReRAM Crossbar},
booktitle = {21st {IEEE} Interregional {NEWCAS} Conference, {NEWCAS} 2023, Edinburgh,
United Kingdom, June 26-28, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/NEWCAS57931.2023.10198206},
doi = {10.1109/NEWCAS57931.2023.10198206},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/newcas/SinghGJRDSYPM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/DattaKSD23,
author = {Kamalika Datta and
Abhoy Kole and
Indranil Sengupta and
Rolf Drechsler},
editor = {Martin Kutrib and
Uwe Meyer},
title = {Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits
to 2-Dimensional Hexagonal Architecture},
booktitle = {Reversible Computation - 15th International Conference, {RC} 2023,
Giessen, Germany, July 18-19, 2023, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {13960},
pages = {218--231},
publisher = {Springer},
year = {2023},
url = {https://doi.org/10.1007/978-3-031-38100-3\_14},
doi = {10.1007/978-3-031-38100-3\_14},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/DattaKSD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/KoleDNSD23,
author = {Abhoy Kole and
Kamalika Datta and
Philipp Niemann and
Indranil Sengupta and
Rolf Drechsler},
editor = {Martin Kutrib and
Uwe Meyer},
title = {Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition
Across Architectures},
booktitle = {Reversible Computation - 15th International Conference, {RC} 2023,
Giessen, Germany, July 18-19, 2023, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {13960},
pages = {232--244},
publisher = {Springer},
year = {2023},
url = {https://doi.org/10.1007/978-3-031-38100-3\_15},
doi = {10.1007/978-3-031-38100-3\_15},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/KoleDNSD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@misc{DBLP:data/10/TempelHD23,
author = {S{\"{o}}ren Tempel and
Vladimir Herdt and
Rolf Drechsler},
title = {Artifacts for the {IEEE} Internet of Things Journal Publication: Specification-based
Symbolic Execution for Stateful Network Protocol Implementations in
the IoT (Version 1)},
publisher = {Zenodo},
year = {2023},
month = jan,
howpublished = {\url{https://doi.org/10.5281/zenodo.7515748}},
note = {Accessed on YYYY-MM-DD.},
url = {https://doi.org/10.5281/zenodo.7515748},
doi = {10.5281/ZENODO.7515748},
timestamp = {Thu, 13 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/data/10/TempelHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2304-13552,
author = {Simranjeet Singh and
Omar Ghazal and
Chandan Kumar Jha and
Vikas Rana and
Rolf Drechsler and
Rishad A. Shafik and
Alex Yakovlev and
Sachin B. Patkar and
Farhad Merchant},
title = {Finite State Automata Design using 1T1R ReRAM Crossbar},
journal = {CoRR},
volume = {abs/2304.13552},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2304.13552},
doi = {10.48550/ARXIV.2304.13552},
eprinttype = {arXiv},
eprint = {2304.13552},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2304-13552.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2307-03669,
author = {Simranjeet Singh and
Chandan Kumar Jha and
Ankit Bende and
Phrangboklang Lyngton Thangkhiew and
Vikas Rana and
Sachin B. Patkar and
Rolf Drechsler and
Farhad Merchant},
title = {Should We Even Optimize for Execution Energy? Rethinking Mapping for
{MAGIC} Design Style},
journal = {CoRR},
volume = {abs/2307.03669},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2307.03669},
doi = {10.48550/ARXIV.2307.03669},
eprinttype = {arXiv},
eprint = {2307.03669},
timestamp = {Tue, 15 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2307-03669.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2309-04868,
author = {Simranjeet Singh and
Chandan Kumar Jha and
Ankit Bende and
Vikas Rana and
Sachin B. Patkar and
Rolf Drechsler and
Farhad Merchant},
title = {MemSPICE: Automated Simulation and Energy Estimation Framework for
MAGIC-Based Logic-in-Memory},
journal = {CoRR},
volume = {abs/2309.04868},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2309.04868},
doi = {10.48550/ARXIV.2309.04868},
eprinttype = {arXiv},
eprint = {2309.04868},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2309-04868.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2310-10460,
author = {Ankit Bende and
Simranjeet Singh and
Chandan Kumar Jha and
Tim Kempen and
Felix C{\"{u}}ppers and
Christopher Bengel and
Andre Zambanini and
Dennis Nielinger and
Sachin B. Patkar and
Rolf Drechsler and
Rainer Waser and
Farhad Merchant and
Vikas Rana},
title = {Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx {RRAM}
Crossbar Array},
journal = {CoRR},
volume = {abs/2310.10460},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2310.10460},
doi = {10.48550/ARXIV.2310.10460},
eprinttype = {arXiv},
eprint = {2310.10460},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2310-10460.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2311-00442,
author = {Sallar Ahmadi{-}Pour and
Pascal Pieper and
Rolf Drechsler},
title = {Virtual-Peripheral-in-the-Loop : {A} Hardware-in-the-Loop Strategy
to Bridge the {VP/RTL} Design-Gap},
journal = {CoRR},
volume = {abs/2311.00442},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2311.00442},
doi = {10.48550/ARXIV.2311.00442},
eprinttype = {arXiv},
eprint = {2311.00442},
timestamp = {Tue, 07 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2311-00442.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/HerdtD22,
author = {Vladimir Herdt and
Rolf Drechsler},
title = {Advanced virtual prototyping for cyber-physical systems using {RISC-V:}
implementation, verification and challenges},
journal = {Sci. China Inf. Sci.},
volume = {65},
number = {1},
year = {2022},
url = {https://doi.org/10.1007/s11432-020-3308-4},
doi = {10.1007/S11432-020-3308-4},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/chinaf/HerdtD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/TempelHD22,
author = {S{\"{o}}ren Tempel and
Vladimir Herdt and
Rolf Drechsler},
title = {Towards Quantification and Visualization of the Effects of Concretization
During Concolic Testing},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {14},
number = {4},
pages = {195--198},
year = {2022},
url = {https://doi.org/10.1109/LES.2022.3171603},
doi = {10.1109/LES.2022.3171603},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/esl/TempelHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/YadavTDCDS22,
author = {Dev Narayan Yadav and
Phrangboklang Lyngton Thangkhiew and
Kamalika Datta and
Sandip Chakraborty and
Rolf Drechsler and
Indranil Sengupta},
title = {FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic
Applications},
journal = {J. Electron. Test.},
volume = {38},
number = {2},
pages = {145--163},
year = {2022},
url = {https://doi.org/10.1007/s10836-022-06001-2},
doi = {10.1007/S10836-022-06001-2},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/YadavTDCDS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/it/FrohlichD22,
author = {Saman Fr{\"{o}}hlich and
Rolf Drechsler},
title = {Unlocking approximation for in-memory computing with Cartesian genetic
programming and computer algebra for arithmetic circuits},
journal = {it Inf. Technol.},
volume = {64},
number = {3},
pages = {99--107},
year = {2022},
url = {https://doi.org/10.1515/itit-2021-0042},
doi = {10.1515/ITIT-2021-0042},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/it/FrohlichD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/WilleD22,
author = {Robert Wille and
Rolf Drechsler},
title = {Introduction to the Special Issue on Design Automation for Quantum
Computing},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {18},
number = {1},
pages = {10:1--10:2},
year = {2022},
url = {https://doi.org/10.1145/3485041},
doi = {10.1145/3485041},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/WilleD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/FrohlichSD22,
author = {Saman Fr{\"{o}}hlich and
Saeideh Shirinzadeh and
Rolf Drechsler},
title = {Parallel Computing of Graph-based Functions in ReRAM},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {18},
number = {2},
pages = {41:1--41:24},
year = {2022},
url = {https://doi.org/10.1145/3453163},
doi = {10.1145/3453163},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/FrohlichSD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/TempelHD22,
author = {S{\"{o}}ren Tempel and
Vladimir Herdt and
Rolf Drechsler},
title = {SymEx-VP: An open source virtual prototype for OS-agnostic concolic
testing of IoT firmware},
journal = {J. Syst. Archit.},
volume = {126},
pages = {102456},
year = {2022},
url = {https://doi.org/10.1016/j.sysarc.2022.102456},
doi = {10.1016/J.SYSARC.2022.102456},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/TempelHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/LalchhandamaDCD22,
author = {F. Lalchhandama and
Kamalika Datta and
Sandip Chakraborty and
Rolf Drechsler and
Indranil Sengupta},
title = {CoMIC: Complementary Memristor based in-memory computing in 3D architecture},
journal = {J. Syst. Archit.},
volume = {126},
pages = {102480},
year = {2022},
url = {https://doi.org/10.1016/j.sysarc.2022.102480},
doi = {10.1016/J.SYSARC.2022.102480},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/LalchhandamaDCD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/YadavTDCDS22,
author = {Dev Narayan Yadav and
Phrangboklang Lyngton Thangkhiew and
Kamalika Datta and
Sandip Chakraborty and
Rolf Drechsler and
Indranil Sengupta},
title = {Feed-Forward learning algorithm for resistive memories},
journal = {J. Syst. Archit.},
volume = {131},
pages = {102730},
year = {2022},
url = {https://doi.org/10.1016/j.sysarc.2022.102730},
doi = {10.1016/J.SYSARC.2022.102730},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/YadavTDCDS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/Ahmadi-PourHD22,
author = {Sallar Ahmadi{-}Pour and
Vladimir Herdt and
Rolf Drechsler},
title = {The MicroRV32 framework: An accessible and configurable open source
{RISC-V} cross-level platform for education and research},
journal = {J. Syst. Archit.},
volume = {133},
pages = {102757},
year = {2022},
url = {https://doi.org/10.1016/j.sysarc.2022.102757},
doi = {10.1016/J.SYSARC.2022.102757},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/Ahmadi-PourHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/NiemannADD22,
author = {Philipp Niemann and
Alexandre A. A. de Almeida and
Gerhard W. Dueck and
Rolf Drechsler},
title = {Template-based mapping of reversible circuits to {IBM} quantum computers},
journal = {Microprocess. Microsystems},
volume = {90},
pages = {104487},
year = {2022},
url = {https://doi.org/10.1016/j.micpro.2022.104487},
doi = {10.1016/J.MICPRO.2022.104487},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/NiemannADD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GoliD22,
author = {Mehran Goli and
Rolf Drechsler},
title = {Through the Looking Glass: Automated Design Understanding of SystemC-Based
VPs at the {ESL}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {4},
pages = {1181--1185},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3074050},
doi = {10.1109/TCAD.2021.3074050},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GoliD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MahzoonGD22,
author = {Alireza Mahzoon and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers
Using Reverse Engineering and Local Vanishing Removal},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {5},
pages = {1573--1586},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3083682},
doi = {10.1109/TCAD.2021.3083682},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MahzoonGD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/TempelHD22,
author = {S{\"{o}}ren Tempel and
Vladimir Herdt and
Rolf Drechsler},
title = {Automated Detection of Spatial Memory Safety Violations for Constrained
Devices},
booktitle = {27th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2022, Taipei, Taiwan, January 17-20, 2022},
pages = {160--165},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ASP-DAC52403.2022.9712570},
doi = {10.1109/ASP-DAC52403.2022.9712570},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/TempelHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ParvinKTSTD22,
author = {Sajjad Parvin and
Thilo Krachenfels and
Shahin Tajik and
Jean{-}Pierre Seifert and
Frank Sill Torres and
Rolf Drechsler},
title = {Toward Optical Probing Resistant Circuits: {A} Comparison of Logic
Styles and Circuit Design Techniques},
booktitle = {27th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2022, Taipei, Taiwan, January 17-20, 2022},
pages = {429--435},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ASP-DAC52403.2022.9712518},
doi = {10.1109/ASP-DAC52403.2022.9712518},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ParvinKTSTD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/atva/TempelHD22,
author = {S{\"{o}}ren Tempel and
Vladimir Herdt and
Rolf Drechsler},
editor = {Ahmed Bouajjani and
Luk{\'{a}}s Hol{\'{\i}}k and
Zhilin Wu},
title = {{SISL:} Concolic Testing of Structured Binary Input Formats via Partial
Specification},
booktitle = {Automated Technology for Verification and Analysis - 20th International
Symposium, {ATVA} 2022, Virtual Event, October 25-28, 2022, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {13505},
pages = {77--82},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-19992-9\_5},
doi = {10.1007/978-3-031-19992-9\_5},
timestamp = {Mon, 05 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/atva/TempelHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cec/PlumpBD22,
author = {Christina Plump and
Bernhard J. Berger and
Rolf Drechsler},
title = {Using density of training data to improve evolutionary algorithms
with approximative fitness functions},
booktitle = {{IEEE} Congress on Evolutionary Computation, {CEC} 2022, Padua, Italy,
July 18-23, 2022},
pages = {1--10},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/CEC55065.2022.9870352},
doi = {10.1109/CEC55065.2022.9870352},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cec/PlumpBD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PieperHGD22,
author = {Pascal Pieper and
Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Rob Oshana},
title = {Verifying SystemC {TLM} peripherals using modern {C++} symbolic execution
tools},
booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco,
California, USA, July 10 - 14, 2022},
pages = {1177--1182},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3489517.3530604},
doi = {10.1145/3489517.3530604},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/PieperHGD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MahzoonG0KD22,
author = {Alireza Mahzoon and
Daniel Gro{\ss}e and
Christoph Scholl and
Alexander Konrad and
Rolf Drechsler},
editor = {Rob Oshana},
title = {Formal verification of modular multipliers using symbolic computer
algebra and boolean satisfiability},
booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco,
California, USA, July 10 - 14, 2022},
pages = {1183--1188},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3489517.3530605},
doi = {10.1145/3489517.3530605},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/MahzoonG0KD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/EckerAMHKHDAWMS22,
author = {Wolfgang Ecker and
Peer Adelt and
Wolfgang M{\"{u}}ller and
Reinhold Heckmann and
Milos Krstic and
Vladimir Herdt and
Rolf Drechsler and
Gerhard Angst and
Ralf Wimmer and
Andreas Mauderer and
Rafael Stahl and
Karsten Emrich and
Daniel Mueller{-}Gritschneder and
Bernd Becker and
Philipp Scholl and
Eyck Jentzsch and
Jan Schlamelcher and
Kim Gr{\"{u}}ttner and
Paul Palomero Bernardo and
Oliver Bringmann and
Mihaela Damian and
Julian Oppermann and
Andreas Koch and
J{\"{o}}rg Bormann and
Johannes Partzsch and
Christian Mayr and
Wolfgang Kunz},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {The Scale4Edge {RISC-V} Ecosystem},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {808--813},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774593},
doi = {10.23919/DATE54114.2022.9774593},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/EckerAMHKHDAWMS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BrunsHJD22,
author = {Niklas Bruns and
Vladimir Herdt and
Eyck Jentzsch and
Rolf Drechsler},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {Cross-Level Processor Verification via Endless Randomized Instruction
Stream Generation with Coverage-guided Aging},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {1123--1126},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774771},
doi = {10.23919/DATE54114.2022.9774771},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/BrunsHJD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/FrohlichD22,
author = {Saman Fr{\"{o}}hlich and
Rolf Drechsler},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {LiM-HDL: HDL-Based Synthesis for In-Memory Computing},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {1395--1400},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774627},
doi = {10.23919/DATE54114.2022.9774627},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/FrohlichD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/DrechslerMG22,
author = {Rolf Drechsler and
Alireza Mahzoon and
Mehran Goli},
title = {Towards Polynomial Formal Verification of Complex Arithmetic Circuits},
booktitle = {25th International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, {DDECS} 2022, Prague, Czech Republic, April
6-8, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DDECS54261.2022.9770156},
doi = {10.1109/DDECS54261.2022.9770156},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/DrechslerMG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/FunckHD22,
author = {Milan Funck and
Vladimir Herdt and
Rolf Drechsler},
title = {Virtual Prototype driven Design, Implementation and Evaluation of
{RISC-V} Instruction Set Extensions},
booktitle = {25th International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, {DDECS} 2022, Prague, Czech Republic, April
6-8, 2022},
pages = {14--19},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DDECS54261.2022.9770108},
doi = {10.1109/DDECS54261.2022.9770108},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/FunckHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/ZhangGD22,
author = {Weiyan Zhang and
Mehran Goli and
Rolf Drechsler},
title = {Early Performance Estimation of Embedded Software on {RISC-V} Processor
using Linear Regression},
booktitle = {25th International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, {DDECS} 2022, Prague, Czech Republic, April
6-8, 2022},
pages = {20--25},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DDECS54261.2022.9770144},
doi = {10.1109/DDECS54261.2022.9770144},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/ZhangGD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/CoskunHD22,
author = {Kemal {\c{C}}aglar Coskun and
Muhammad Hassan and
Rolf Drechsler},
title = {Equivalence Checking of System-Level and SPICE-Level Models of Linear
Analog Filters},
booktitle = {25th International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, {DDECS} 2022, Prague, Czech Republic, April
6-8, 2022},
pages = {160--165},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DDECS54261.2022.9770142},
doi = {10.1109/DDECS54261.2022.9770142},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/CoskunHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/MetzGD22,
author = {Christopher A. Metz and
Mehran Goli and
Rolf Drechsler},
title = {ML-based Power Estimation of Convolutional Neural Networks on GPGPUs},
booktitle = {25th International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, {DDECS} 2022, Prague, Czech Republic, April
6-8, 2022},
pages = {166--171},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DDECS54261.2022.9770153},
doi = {10.1109/DDECS54261.2022.9770153},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/MetzGD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/Ahmadi-PourSHDM22,
author = {Sallar Ahmadi{-}Pour and
Sangeet Saha and
Vladimir Herdt and
Rolf Drechsler and
Klaus D. McDonald{-}Maier},
title = {Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time
Systems: {A} {RISC-V} Case-Study},
booktitle = {25th Euromicro Conference on Digital System Design, {DSD} 2022, Maspalomas,
Spain, August 31 - Sept. 2, 2022},
pages = {134--141},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DSD57027.2022.00027},
doi = {10.1109/DSD57027.2022.00027},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/Ahmadi-PourSHDM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/SchnieberFD22,
author = {Martha Schnieber and
Saman Fr{\"{o}}hlich and
Rolf Drechsler},
title = {Polynomial Formal Verification of Approximate Adders},
booktitle = {25th Euromicro Conference on Digital System Design, {DSD} 2022, Maspalomas,
Spain, August 31 - Sept. 2, 2022},
pages = {761--768},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DSD57027.2022.00107},
doi = {10.1109/DSD57027.2022.00107},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/SchnieberFD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/KoleDSD22,
author = {Abhoy Kole and
Kamalika Datta and
Indranil Sengupta and
Rolf Drechsler},
title = {SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally
Complete Gate Library},
booktitle = {25th Euromicro Conference on Digital System Design, {DSD} 2022, Maspalomas,
Spain, August 31 - Sept. 2, 2022},
pages = {769--776},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DSD57027.2022.00108},
doi = {10.1109/DSD57027.2022.00108},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/KoleDSD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/DattaSTSD22,
author = {Kamalika Datta and
Saeideh Shirinzadeh and
Phrangboklang Lyngton Thangkhiew and
Indranil Sengupta and
Rolf Drechsler},
title = {Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles},
booktitle = {25th Euromicro Conference on Digital System Design, {DSD} 2022, Maspalomas,
Spain, August 31 - Sept. 2, 2022},
pages = {793--800},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DSD57027.2022.00111},
doi = {10.1109/DSD57027.2022.00111},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/DattaSTSD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/FrohlichD22,
author = {Saman Fr{\"{o}}hlich and
Rolf Drechsler},
title = {Generation of Verified Programs for In-Memory Computing},
booktitle = {25th Euromicro Conference on Digital System Design, {DSD} 2022, Maspalomas,
Spain, August 31 - Sept. 2, 2022},
pages = {815--820},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DSD57027.2022.00114},
doi = {10.1109/DSD57027.2022.00114},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/FrohlichD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/MertenHD22,
author = {Marcel Merten and
Sebastian Huhn and
Rolf Drechsler},
title = {Quality Assessment of RFET-based Logic Locking Protection Mechanisms
using Formal Methods},
booktitle = {{IEEE} European Test Symposium, {ETS} 2022, Barcelona, Spain, May
23-27, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ETS54262.2022.9810459},
doi = {10.1109/ETS54262.2022.9810459},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ets/MertenHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/BrunsHD22,
author = {Niklas Bruns and
Vladimir Herdt and
Rolf Drechsler},
title = {Unified {HW/SW} Coverage: {A} Novel Metric to Boost Coverage-guided
Fuzzing for Virtual Prototype based {HW/SW} Co-Verification},
booktitle = {Forum on Specification {\&} Design Languages, {FDL} 2022, Linz,
Austria, September 14-16, 2022},
pages = {1--8},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/FDL56239.2022.9925661},
doi = {10.1109/FDL56239.2022.9925661},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/BrunsHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/FratzerHLD22,
author = {Alexander Fratzer and
Vladimir Herdt and
Christoph L{\"{u}}th and
Rolf Drechsler},
title = {Virtual Prototype based Analysis of Neural Network Cache Behavior
for Tiny Edge Device},
booktitle = {Forum on Specification {\&} Design Languages, {FDL} 2022, Linz,
Austria, September 14-16, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/FDL56239.2022.9925663},
doi = {10.1109/FDL56239.2022.9925663},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/FratzerHLD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/ZielaskoTHD22,
author = {Jan Zielasko and
S{\"{o}}ren Tempel and
Vladimir Herdt and
Rolf Drechsler},
title = {3D Visualization of Symbolic Execution Traces},
booktitle = {Forum on Specification {\&} Design Languages, {FDL} 2022, Linz,
Austria, September 14-16, 2022},
pages = {1--8},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/FDL56239.2022.9925664},
doi = {10.1109/FDL56239.2022.9925664},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/ZielaskoTHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/KonradSMGD22,
author = {Alexander Konrad and
Christoph Scholl and
Alireza Mahzoon and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Alberto Griggio and
Neha Rungta},
title = {Divider Verification Using Symbolic Computer Algebra and Delayed Don't
Care Optimization},
booktitle = {22nd Formal Methods in Computer-Aided Design, {FMCAD} 2022, Trento,
Italy, October 17-21, 2022},
pages = {1--10},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.34727/2022/isbn.978-3-85448-053-2\_17},
doi = {10.34727/2022/ISBN.978-3-85448-053-2\_17},
timestamp = {Mon, 13 Feb 2023 21:53:10 +0100},
biburl = {https://dblp.org/rec/conf/fmcad/KonradSMGD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/PlumpBD22,
author = {Christina Plump and
Bernhard J. Berger and
Rolf Drechsler},
editor = {Jonathan E. Fieldsend and
Markus Wagner},
title = {Adapting mutation and recombination operators to range-aware relations
in real-world application data},
booktitle = {{GECCO} '22: Genetic and Evolutionary Computation Conference, Companion
Volume, Boston, Massachusetts, USA, July 9 - 13, 2022},
pages = {755--758},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3520304.3529066},
doi = {10.1145/3520304.3529066},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/gecco/PlumpBD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gi/DattaK0D22,
author = {Kamalika Datta and
Abhoy Kole and
Indranil Sengupta and
Rolf Drechsler},
editor = {Daniel Demmler and
Daniel Krupka and
Hannes Federrath},
title = {Mapping Quantum Circuits to 2-Dimensional Quantum Architectures},
booktitle = {52. Jahrestagung der Gesellschaft f{\"{u}}r Informatik, {INFORMATIK}
2022, Informatik in den Naturwissenschaften, 26. - 30. September 2022,
Hamburg},
series = {{LNI}},
volume = {{P-326}},
pages = {1109--1120},
publisher = {Gesellschaft f{\"{u}}r Informatik, Bonn},
year = {2022},
url = {https://doi.org/10.18420/inf2022\_94},
doi = {10.18420/INF2022\_94},
timestamp = {Fri, 08 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/gi/DattaK0D22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/BrunsHGD22,
author = {Niklas Bruns and
Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Ioannis Savidis and
Avesta Sasan and
Himanshu Thapliyal and
Ronald F. DeMara},
title = {Efficient Cross-Level Processor Verification using Coverage-guided
Fuzzing},
booktitle = {{GLSVLSI} '22: Great Lakes Symposium on {VLSI} 2022, Irvine {CA} USA,
June 6 - 8, 2022},
pages = {97--103},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3526241.3530340},
doi = {10.1145/3526241.3530340},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/BrunsHGD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PieperHD22,
author = {Pascal Pieper and
Vladimir Herdt and
Rolf Drechsler},
editor = {Ioannis Savidis and
Avesta Sasan and
Himanshu Thapliyal and
Ronald F. DeMara},
title = {Advanced Environment Modeling and Interaction in an Open Source {RISC-V}
Virtual Prototype},
booktitle = {{GLSVLSI} '22: Great Lakes Symposium on {VLSI} 2022, Irvine {CA} USA,
June 6 - 8, 2022},
pages = {193--197},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3526241.3530374},
doi = {10.1145/3526241.3530374},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/PieperHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/DrechslerM22,
author = {Rolf Drechsler and
Alireza Mahzoon},
editor = {Tulika Mitra and
Evangeline F. Y. Young and
Jinjun Xiong},
title = {Polynomial Formal Verification: Ensuring Correctness under Resource
Constraints},
booktitle = {Proceedings of the 41st {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2022, San Diego, California, USA, 30 October 2022
- 3 November 2022},
pages = {70:1--70:9},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3508352.3561104},
doi = {10.1145/3508352.3561104},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/DrechslerM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/NiemannD22,
author = {Philipp Niemann and
Rolf Drechsler},
title = {Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued
Logic},
booktitle = {52nd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2022, Dallas, TX, USA, May 18-20, 2022},
pages = {9--14},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISMVL52857.2022.00009},
doi = {10.1109/ISMVL52857.2022.00009},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ismvl/NiemannD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/DattaKSD22,
author = {Kamalika Datta and
Abhoy Kole and
Indranil Sengupta and
Rolf Drechsler},
title = {Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal
Qubit Architecture},
booktitle = {52nd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2022, Dallas, TX, USA, May 18-20, 2022},
pages = {35--42},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISMVL52857.2022.00013},
doi = {10.1109/ISMVL52857.2022.00013},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ismvl/DattaKSD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SchnieberFD22,
author = {Martha Schnieber and
Saman Fr{\"{o}}hlich and
Rolf Drechsler},
title = {Polynomial Formal Verification of Approximate Functions},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2022, Nicosia,
Cyprus, July 4-6, 2022},
pages = {92--97},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISVLSI54635.2022.00029},
doi = {10.1109/ISVLSI54635.2022.00029},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/SchnieberFD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/0001D22,
author = {Sebastian Huhn and
Rolf Drechsler},
title = {Next Generation Design For Testability, Debug and Reliability Using
Formal Techniques},
booktitle = {{IEEE} International Test Conference, {ITC} 2022, Anaheim, CA, USA,
September 23-30, 2022},
pages = {609--618},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ITC50671.2022.00086},
doi = {10.1109/ITC50671.2022.00086},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/itc/0001D22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/Drechsler22,
author = {Rolf Drechsler},
title = {Fast and Exact is Doable: Polynomial Algorithms in Test and Verification},
booktitle = {23rd {IEEE} Latin American Test Symposium, {LATS} 2022, Montevideo,
Uruguay, September 5-8, 2022},
pages = {1--2},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/LATS57337.2022.9936904},
doi = {10.1109/LATS57337.2022.9936904},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/latw/Drechsler22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/GoliD22,
author = {Mehran Goli and
Rolf Drechsler},
title = {Simulation-based Verification of SystemC-based VPs at the {ESL}},
booktitle = {Methods and Description Languages for Modelling and Verification of
Circuits and Systems, {MBMV} 2022, 25th Workshop, Virtual Event, Germany,
February 17-18, 2022},
pages = {1--4},
publisher = {{VDE/IEEE}},
year = {2022},
url = {https://ieeexplore.ieee.org/document/9788580},
timestamp = {Fri, 12 Jan 2024 10:14:38 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/GoliD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/MahzoonD22,
author = {Alireza Mahzoon and
Rolf Drechsler},
title = {Polynomial Formal Verification of Complex Multipliers},
booktitle = {Methods and Description Languages for Modelling and Verification of
Circuits and Systems, {MBMV} 2022, 25th Workshop, Virtual Event, Germany,
February 17-18, 2022},
pages = {1--4},
publisher = {{VDE/IEEE}},
year = {2022},
url = {https://ieeexplore.ieee.org/document/9788585},
timestamp = {Fri, 12 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/MahzoonD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/med/MeywerkNHD22,
author = {Tim Meywerk and
Arthur Niedzwiecki and
Vladimir Herdt and
Rolf Drechsler},
title = {Simulation-Based Debugging of Formal Environment Models},
booktitle = {30th Mediterranean Conference on Control and Automation, {MED} 2022,
Vouliagmeni, Greece, June 28 - July 1, 2022},
pages = {890--895},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MED54222.2022.9837055},
doi = {10.1109/MED54222.2022.9837055},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/med/MeywerkNHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mlcad/MetzGD22,
author = {Christopher A. Metz and
Mehran Goli and
Rolf Drechsler},
title = {Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs
with Dynamic Frequency Scaling},
booktitle = {2022 {ACM/IEEE} Workshop on Machine Learning for CAD, {MLCAD} 2022,
Virtual Event, China, September 12-13, 2022},
pages = {103--109},
publisher = {{ACM} / {IEEE}},
year = {2022},
url = {https://doi.org/10.1145/3551901.3556481},
doi = {10.1145/3551901.3556481},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mlcad/MetzGD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/re/FeyFD22,
author = {G{\"{o}}rschwin Fey and
Martin Fr{\"{a}}nzle and
Rolf Drechsler},
title = {Self-Explanation in Systems of Systems},
booktitle = {30th {IEEE} International Requirements Engineering Conference Workshops,
{RE} 2022 - Workshops, Melbourne, Australia, August 15-19, 2022},
pages = {85--91},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/REW56159.2022.00023},
doi = {10.1109/REW56159.2022.00023},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/re/FeyFD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/ZhangGMD22,
author = {Weiyan Zhang and
Mehran Goli and
Alireza Mahzoon and
Rolf Drechsler},
title = {ANN-based Performance Estimation of Embedded Software for {RISC-V}
Processors},
booktitle = {{IEEE} International Workshop on Rapid System Prototyping, {RSP} 2022,
Shanghai, China, October 13, 2022},
pages = {22--28},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/RSP57251.2022.10039004},
doi = {10.1109/RSP57251.2022.10039004},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rsp/ZhangGMD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DattaFSYSD22,
author = {Kamalika Datta and
Saman Fr{\"{o}}hlich and
Saeideh Shirinzadeh and
Dev Narayan Yadav and
Indranil Sengupta and
Rolf Drechsler},
title = {Unlocking High Resolution Arithmetic Operations within Memristive
Crossbars for Error Tolerant Applications},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939573},
doi = {10.1109/VLSI-SOC54400.2022.9939573},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DattaFSYSD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DrechslerM22,
author = {Rolf Drechsler and
Alireza Mahzoon},
title = {Preserving Design Hierarchy Information for Polynomial Formal Verification},
booktitle = {30th {IFIP/IEEE} 30th International Conference on Very Large Scale
Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
pages = {1--7},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939650},
doi = {10.1109/VLSI-SOC54400.2022.9939650},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DrechslerM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/MertenHD22,
author = {Marcel Merten and
Sebastian Huhn and
Rolf Drechsler},
title = {A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization
Operators for On-Chip Transient Fault Detection},
booktitle = {40th {IEEE} {VLSI} Test Symposium, {VTS} 2022, San Diego, CA, USA,
April 25-27, 2022},
pages = {1--7},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VTS52500.2021.9794161},
doi = {10.1109/VTS52500.2021.9794161},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vts/MertenHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/22/AutexierLD22,
author = {Serge Autexier and
Christoph L{\"{u}}th and
Rolf Drechsler},
editor = {Mario A. Pfannstiel},
title = {Das Bremen Ambient Assisted Living Lab und dar{\"{u}}ber hinaus
- Intelligente Umgebungen, smarte Services und K{\"{u}}nstliche
Intelligenz in der Medizin f{\"{u}}r den Menschen},
booktitle = {K{\"{u}}nstliche Intelligenz im Gesundheitswesen: Entwicklungen,
Beispiele und Perspektiven},
pages = {835--850},
publisher = {Springer Fachmedien Wiesbaden},
year = {2022},
url = {https://doi.org/10.1007/978-3-658-33597-7\_40},
doi = {10.1007/978-3-658-33597-7\_40},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/sp/22/AutexierLD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@misc{DBLP:data/10/TempelHD22,
author = {S{\"{o}}ren Tempel and
Vladimir Herdt and
Rolf Drechsler},
title = {Artifacts for the 2022 {ATVA} Paper: {SISL:} Concolic Testing of Structured
Binary Input Formats via Partial Specification (Version 1)},
publisher = {Zenodo},
year = {2022},
month = jul,
howpublished = {\url{https://doi.org/10.5281/zenodo.6802198}},
note = {Accessed on YYYY-MM-DD.},
url = {https://doi.org/10.5281/zenodo.6802198},
doi = {10.5281/ZENODO.6802198},
timestamp = {Thu, 13 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/data/10/TempelHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2202-08046,
author = {Mehran Goli and
Rolf Drechsler},
title = {Simulation-based Verification of SystemC-based VPs at the {ESL}},
journal = {CoRR},
volume = {abs/2202.08046},
year = {2022},
url = {https://arxiv.org/abs/2202.08046},
eprinttype = {arXiv},
eprint = {2202.08046},
timestamp = {Tue, 01 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2202-08046.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2209-12477,
author = {Jan Kleinekath{\"{o}}fer and
Alireza Mahzoon and
Rolf Drechsler},
title = {Lower Bound Proof for the Size of BDDs representing a Shifted Addition},
journal = {CoRR},
volume = {abs/2209.12477},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2209.12477},
doi = {10.48550/ARXIV.2209.12477},
eprinttype = {arXiv},
eprint = {2209.12477},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2209-12477.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/BrunsHGD21,
author = {Niklas Bruns and
Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Toward {RISC-V} {CSR} Compliance Testing},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {13},
number = {4},
pages = {202--205},
year = {2021},
url = {https://doi.org/10.1109/LES.2021.3077368},
doi = {10.1109/LES.2021.3077368},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/esl/BrunsHGD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BhattacharjeeBN21,
author = {Anirban Bhattacharjee and
Chandan Bandyopadhyay and
Philipp Niemann and
Bappaditya Mondal and
Rolf Drechsler and
Hafizur Rahaman},
title = {An improved heuristic technique for nearest neighbor realization of
quantum circuits in 2D architecture},
journal = {Integr.},
volume = {76},
pages = {40--54},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.09.003},
doi = {10.1016/J.VLSI.2020.09.003},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BhattacharjeeBN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BhattacharjeeBM21,
author = {Anirban Bhattacharjee and
Chandan Bandyopadhyay and
Angshu Mukherjee and
Robert Wille and
Rolf Drechsler and
Hafizur Rahaman},
title = {An ant colony based mapping of quantum circuits to nearest neighbor
architectures},
journal = {Integr.},
volume = {78},
pages = {11--24},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2020.12.002},
doi = {10.1016/J.VLSI.2020.12.002},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/BhattacharjeeBM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/HerdtGTD21,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
S{\"{o}}ren Tempel and
Rolf Drechsler},
title = {Adaptive simulation with Virtual Prototypes in an open-source {RISC-V}
evaluation platform},
journal = {J. Syst. Archit.},
volume = {116},
pages = {102135},
year = {2021},
url = {https://doi.org/10.1016/j.sysarc.2021.102135},
doi = {10.1016/J.SYSARC.2021.102135},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/HerdtGTD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HerdtTGD21,
author = {Vladimir Herdt and
S{\"{o}}ren Tempel and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Mutation-based Compliance Testing for {RISC-V}},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {55--60},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431584},
doi = {10.1145/3394885.3431584},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/HerdtTGD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GoliD21,
author = {Mehran Goli and
Rolf Drechsler},
title = {ATLaS: Automatic Detection of Timing-based Information Leakage Flows
for SystemC {HLS} Designs},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {67--72},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431591},
doi = {10.1145/3394885.3431591},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/GoliD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WalterHWTD21,
author = {Marcel Walter and
Winston Haaswijk and
Robert Wille and
Frank Sill Torres and
Rolf Drechsler},
title = {One-pass Synthesis for Field-coupled Nanocomputing Technologies},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {574--580},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431607},
doi = {10.1145/3394885.3431607},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WalterHWTD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/0002GD21,
author = {Muhammad Hassan and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {System-Level Verification of Linear and Non-Linear Behaviors of {RF}
Amplifiers using Metamorphic Relations},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {761--766},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431592},
doi = {10.1145/3394885.3431592},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/0002GD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/MahzoonD21,
author = {Alireza Mahzoon and
Rolf Drechsler},
title = {Polynomial Formal Verification of Prefix Adders},
booktitle = {30th {IEEE} Asian Test Symposium, {ATS} 2021, Matsuyama, Ehime, Japan,
November 22-25, 2021},
pages = {85--90},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ATS52891.2021.00027},
doi = {10.1109/ATS52891.2021.00027},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ats/MahzoonD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cec/PlumpBD21,
author = {Christina Plump and
Bernhard J. Berger and
Rolf Drechsler},
title = {Improving Evolutionary Algorithms by Enhancing an Approximative Fitness
Function through Prediction Intervals},
booktitle = {{IEEE} Congress on Evolutionary Computation, {CEC} 2021, Krak{\'{o}}w,
Poland, June 28 - July 1, 2021},
pages = {127--135},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/CEC45853.2021.9504722},
doi = {10.1109/CEC45853.2021.9504722},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cec/PlumpBD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cec/PlumpBD21a,
author = {Christina Plump and
Bernhard J. Berger and
Rolf Drechsler},
title = {Domain-driven Correlation-aware Recombination and Mutation Operators
for Complex Real-world Applications},
booktitle = {{IEEE} Congress on Evolutionary Computation, {CEC} 2021, Krak{\'{o}}w,
Poland, June 28 - July 1, 2021},
pages = {540--548},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/CEC45853.2021.9504931},
doi = {10.1109/CEC45853.2021.9504931},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cec/PlumpBD21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/MetzGD21,
author = {Christopher A. Metz and
Mehran Goli and
Rolf Drechsler},
editor = {Jason Xue and
Chengmo Yang},
title = {Early power estimation of CUDA-based CNNs on GPGPUs: work-in-progress},
booktitle = {{CODES/ISSS} 2021, International Conference on Hardware/Software Codesign
and System Synthesis, Virtual Event, October 10-13, 2021},
pages = {29--30},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3478684.3479255},
doi = {10.1145/3478684.3479255},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/codes/MetzGD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/TempelHD21,
author = {S{\"{o}}ren Tempel and
Vladimir Herdt and
Rolf Drechsler},
title = {Towards Reliable Spatial Memory Safety for Embedded Software by Combining
Checked {C} with Concolic Testing},
booktitle = {58th {ACM/IEEE} Design Automation Conference, {DAC} 2021, San Francisco,
CA, USA, December 5-9, 2021},
pages = {667--672},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DAC18074.2021.9586170},
doi = {10.1109/DAC18074.2021.9586170},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/TempelHD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MahzoonD21,
author = {Alireza Mahzoon and
Rolf Drechsler},
title = {Late Breaking Results: Polynomial Formal Verification of Fast Adders},
booktitle = {58th {ACM/IEEE} Design Automation Conference, {DAC} 2021, San Francisco,
CA, USA, December 5-9, 2021},
pages = {1376--1377},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DAC18074.2021.9586107},
doi = {10.1109/DAC18074.2021.9586107},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/MahzoonD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/0001BD21,
author = {Philipp Niemann and
Chandan Bandyopadhyay and
Rolf Drechsler},
title = {Combining SWAPs and Remote Toffoli Gates in the Mapping to {IBM} {QX}
Architectures},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {200--205},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474217},
doi = {10.23919/DATE51398.2021.9474217},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/0001BD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/TempelHD21,
author = {S{\"{o}}ren Tempel and
Vladimir Herdt and
Rolf Drechsler},
title = {An Effective Methodology for Integrating Concolic Testing with SystemC-based
Virtual Prototypes},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {218--221},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474149},
doi = {10.23919/DATE51398.2021.9474149},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/TempelHD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SchollKMGD21,
author = {Christoph Scholl and
Alexander Konrad and
Alireza Mahzoon and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Verifying Dividers Using Symbolic Computer Algebra and Don't Care
Optimization},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1110--1115},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474019},
doi = {10.23919/DATE51398.2021.9474019},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/SchollKMGD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PolianAABBDDD0G21,
author = {Ilia Polian and
Frank Altmann and
Tolga Arul and
Christian Boit and
Ralf Brederlow and
Lucas Davi and
Rolf Drechsler and
Nan Du and
Thomas Eisenbarth and
Tim G{\"{u}}neysu and
Sascha Hermann and
Matthias Hiller and
Rainer Leupers and
Farhad Merchant and
Thomas Mussenbrock and
Stefan Katzenbeisser and
Akash Kumar and
Wolfgang Kunz and
Thomas Mikolajick and
Vivek Pachauri and
Jean{-}Pierre Seifert and
Frank Sill Torres and
Jens Trommer},
title = {Nano Security: From Nano-Electronics to Secure Systems},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1334--1339},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474187},
doi = {10.23919/DATE51398.2021.9474187},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/PolianAABBDDD0G21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/0002GD21,
author = {Muhammad Hassan and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {System Level Verification of Phase-Locked Loop using Metamorphic Relations},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1378--1381},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474211},
doi = {10.23919/DATE51398.2021.9474211},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/0002GD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RaiGPHMSKDM021,
author = {Shubham Rai and
Siddharth Garg and
Christian Pilato and
Vladimir Herdt and
Elmira Moussavi and
Dominik Sisejkovic and
Ramesh Karri and
Rolf Drechsler and
Farhad Merchant and
Akash Kumar},
title = {Vertical {IP} Protection of the Next-Generation Devices: Quo Vadis?},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1905--1914},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474132},
doi = {10.23919/DATE51398.2021.9474132},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/RaiGPHMSKDM021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/Drechsler21,
author = {Rolf Drechsler},
editor = {Muhammad Shafique and
Andreas Steininger and
Luk{\'{a}}s Sekanina and
Milos Krstic and
Goran Stojanovic and
Vojtech Mrazek},
title = {PolyAdd: Polynomial Formal Verification of Adder Circuits},
booktitle = {24th International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2021, Vienna, Austria, April 7-9,
2021},
pages = {99--104},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DDECS52668.2021.9417052},
doi = {10.1109/DDECS52668.2021.9417052},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/Drechsler21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/MertenHD21,
author = {Marcel Merten and
Sebastian Huhn and
Rolf Drechsler},
editor = {Luigi Dilillo and
Luca Cassano and
Athanasios Papadimitriou},
title = {A Codeword-based Compactor for On-Chip Generated Debug Data Using
Two-Stage Artificial Neural Networks},
booktitle = {36th {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFT} 2021, Athens, Greece,
October 6-8, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DFT52944.2021.9568298},
doi = {10.1109/DFT52944.2021.9568298},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dft/MertenHD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/NiemannMD21,
author = {Philipp Niemann and
Luca M{\"{u}}ller and
Rolf Drechsler},
editor = {Francesco Leporati and
Salvatore Vitabile and
Amund Skavhaug},
title = {Combining SWAPs and Remote {CNOT} Gates for Quantum Circuit Transformation},
booktitle = {24th Euromicro Conference on Digital System Design, {DSD} 2021, Virtual
Event / Palermo, Sicily, Italy, September 1-3, 2021},
pages = {495--501},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DSD53832.2021.00080},
doi = {10.1109/DSD53832.2021.00080},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/NiemannMD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/GoliMD21,
author = {Mehran Goli and
Alireza Mahzoon and
Rolf Drechsler},
editor = {Francesco Leporati and
Salvatore Vitabile and
Amund Skavhaug},
title = {Automated Debugging-Aware Visualization Technique for SystemC {HLS}
Designs},
booktitle = {24th Euromicro Conference on Digital System Design, {DSD} 2021, Virtual
Event / Palermo, Sicily, Italy, September 1-3, 2021},
pages = {519--526},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DSD53832.2021.00084},
doi = {10.1109/DSD53832.2021.00084},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/GoliMD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dtis/HabibyHD21,
author = {Payam Habiby and
Sebastian Huhn and
Rolf Drechsler},
title = {Optimization-based Test Scheduling for {IEEE} 1687 Multi-Power Domain
Networks Using Boolean Satisfiability},
booktitle = {16th International Conference on Design {\&} Technology of Integrated
Systems in Nanoscale Era, {DTIS} 2021, Montpellier, France, June 28-30,
2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DTIS53253.2021.9505098},
doi = {10.1109/DTIS53253.2021.9505098},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dtis/HabibyHD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/Ahmadi-PourHD21,
author = {Sallar Ahmadi{-}Pour and
Vladimir Herdt and
Rolf Drechsler},
title = {{RISC-V} {AMS} {VP:} An Open Source Evaluation Platform for Cyber-Physical
Systems},
booktitle = {24th Forum on specification {\&} Design Languages, {FDL} 2021,
Antibes, France, September 8-10, 2021},
pages = {1--7},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/FDL53530.2021.9568387},
doi = {10.1109/FDL53530.2021.9568387},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/Ahmadi-PourHD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/GoliD21,
author = {Mehran Goli and
Rolf Drechsler},
title = {{VIP-VP:} Early Validation of SoCs Information Flow Policies using
SystemC-based Virtual Prototypes},
booktitle = {24th Forum on specification {\&} Design Languages, {FDL} 2021,
Antibes, France, September 8-10, 2021},
pages = {1--8},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/FDL53530.2021.9568377},
doi = {10.1109/FDL53530.2021.9568377},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/GoliD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/TempelHD21,
author = {S{\"{o}}ren Tempel and
Vladimir Herdt and
Rolf Drechsler},
title = {In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End
Multithreaded Operating Systems using Virtual Prototypes},
booktitle = {24th Forum on specification {\&} Design Languages, {FDL} 2021,
Antibes, France, September 8-10, 2021},
pages = {1--7},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/FDL53530.2021.9568384},
doi = {10.1109/FDL53530.2021.9568384},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/TempelHD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/KraussMBD21,
author = {Rune Krauss and
Marcel Merten and
Mirco Bockholt and
Rolf Drechsler},
editor = {Krzysztof Krawiec},
title = {{ALF:} a fitness-based artificial life form for evolving large-scale
neural networks},
booktitle = {{GECCO} '21: Genetic and Evolutionary Computation Conference, Companion
Volume, Lille, France, July 10-14, 2021},
pages = {225--226},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3449726.3459545},
doi = {10.1145/3449726.3459545},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/gecco/KraussMBD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Pieper0AD21,
author = {Pascal Pieper and
Ralf Wimmer and
Gerhard Angst and
Rolf Drechsler},
editor = {Yiran Chen and
Victor V. Zhirnov and
Avesta Sasan and
Ioannis Savidis},
title = {Minimally Invasive {HW/SW} Co-debug Live Visualization on Architecture
Level},
booktitle = {{GLSVLSI} '21: Great Lakes Symposium on {VLSI} 2021, Virtual Event,
USA, June 22-25, 2021},
pages = {321--326},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3453688.3461524},
doi = {10.1145/3453688.3461524},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/Pieper0AD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/GoliD21,
author = {Mehran Goli and
Rolf Drechsler},
title = {Early Validation of SoCs Security Architecture Against Timing Flows
Using SystemC-based VPs},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--8},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643579},
doi = {10.1109/ICCAD51958.2021.9643579},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/GoliD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KlemmerFDG21,
author = {Lucas Klemmer and
Saman Fr{\"{o}}hlich and
Rolf Drechsler and
Daniel Gro{\ss}e},
title = {XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product
Encoding},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401780},
doi = {10.1109/ISCAS51556.2021.9401780},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KlemmerFDG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/0001D21,
author = {Philipp Niemann and
Rolf Drechsler},
title = {Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic},
booktitle = {51st {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2021, Nur-Sultan, Kazakhstan, May 25-27, 2021},
pages = {178--182},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISMVL51352.2021.00038},
doi = {10.1109/ISMVL51352.2021.00038},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ismvl/0001D21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SchnieberFD21,
author = {Martha Schnieber and
Saman Fr{\"{o}}hlich and
Rolf Drechsler},
title = {Depth Optimized Synthesis of Symmetric Boolean Functions},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2021, Tampa,
FL, USA, July 7-9, 2021},
pages = {61--66},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISVLSI51109.2021.00022},
doi = {10.1109/ISVLSI51109.2021.00022},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/SchnieberFD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/Ahmadi-PourHD21,
author = {Sallar Ahmadi{-}Pour and
Vladimir Herdt and
Rolf Drechsler},
title = {Constrained Random Verification for {RISC-V:} Overview, Evaluation
and Discussion},
booktitle = {Methods and Description Languages for Modelling and Verification of
Circuits and Systems, {MBMV} 2021, 24th Workshop, Virtual Event, Germany,
March 18-19, 2021},
pages = {1--8},
publisher = {{VDE/IEEE}},
year = {2021},
url = {https://ieeexplore.ieee.org/document/9399722},
timestamp = {Fri, 12 Jan 2024 10:19:10 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/Ahmadi-PourHD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/BarhoushMD21,
author = {Mohammed Barhoush and
Alireza Mahzoon and
Rolf Drechsler},
editor = {S. Arun{-}Kumar and
Dominique M{\'{e}}ry and
Indranil Saha and
Lijun Zhang},
title = {Polynomial word-level verification of arithmetic circuits},
booktitle = {{MEMOCODE} '21: 19th {ACM-IEEE} International Conference on Formal
Methods and Models for System Design, Virtual Event, China, November
20 - 22, 2021},
pages = {1--9},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3487212.3487333},
doi = {10.1145/3487212.3487333},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/memocode/BarhoushMD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/modelsward/BornebuschLWD21,
author = {Fritjof Bornebusch and
Christoph L{\"{u}}th and
Robert Wille and
Rolf Drechsler},
editor = {Slimane Hammoudi and
Lu{\'{\i}}s Ferreira Pires and
Edwin Seidewitz and
Richard Soley},
title = {Performance Aspects of Correctness-oriented Synthesis Flows},
booktitle = {Proceedings of the 9th International Conference on Model-Driven Engineering
and Software Development, {MODELSWARD} 2021, Online Streaming, February
8-10, 2021},
pages = {76--86},
publisher = {{SCITEPRESS}},
year = {2021},
url = {https://doi.org/10.5220/0010235100760086},
doi = {10.5220/0010235100760086},
timestamp = {Tue, 06 Jun 2023 14:58:00 +0200},
biburl = {https://dblp.org/rec/conf/modelsward/BornebuschLWD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/0001MD21,
author = {Philipp Niemann and
Luca M{\"{u}}ller and
Rolf Drechsler},
editor = {Shigeru Yamashita and
Tetsuo Yokoyama},
title = {Finding Optimal Implementations of Non-native {CNOT} Gates Using {SAT}},
booktitle = {Reversible Computation - 13th International Conference, {RC} 2021,
Virtual Event, July 7-8, 2021, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {12805},
pages = {242--255},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-030-79837-6\_15},
doi = {10.1007/978-3-030-79837-6\_15},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/0001MD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RieseHGD21,
author = {Frank Riese and
Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Metamorphic Testing for Processor Verification: {A} {RISC-V} Case
Study at the Instruction Level},
booktitle = {29th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSI-SoC53125.2021.9606997},
doi = {10.1109/VLSI-SOC53125.2021.9606997},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RieseHGD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:series/faia/DrechslerJN21,
author = {Rolf Drechsler and
Tommi A. Junttila and
Ilkka Niemel{\"{a}}},
editor = {Armin Biere and
Marijn Heule and
Hans van Maaren and
Toby Walsh},
title = {Non-Clausal {SAT} and {ATPG}},
booktitle = {Handbook of Satisfiability - Second Edition},
series = {Frontiers in Artificial Intelligence and Applications},
volume = {336},
pages = {1047--1086},
publisher = {{IOS} Press},
year = {2021},
url = {https://doi.org/10.3233/FAIA201011},
doi = {10.3233/FAIA201011},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/series/faia/DrechslerJN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@misc{DBLP:data/10/TempelHD21,
author = {S{\"{o}}ren Tempel and
Vladimir Herdt and
Rolf Drechsler},
title = {Artifacts for the {FDL21} Paper: In-Vivo Stack Overflow Detection
and Stack Size Estimation for Low-End Multithreaded Operating Systems
using Virtual Prototypes (Version 1)},
publisher = {Zenodo},
year = {2021},
month = sep,
howpublished = {\url{https://doi.org/10.5281/zenodo.5091709}},
note = {Accessed on YYYY-MM-DD.},
url = {https://doi.org/10.5281/zenodo.5091709},
doi = {10.5281/ZENODO.5091709},
timestamp = {Thu, 13 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/data/10/TempelHD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2102-02645,
author = {Christopher A. Metz and
Mehran Goli and
Rolf Drechsler},
title = {Pick the Right Edge Device: Towards Power and Performance Estimation
of CUDA-based CNNs on GPGPUs},
journal = {CoRR},
volume = {abs/2102.02645},
year = {2021},
url = {https://arxiv.org/abs/2102.02645},
eprinttype = {arXiv},
eprint = {2102.02645},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2102-02645.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2104-03024,
author = {Rolf Drechsler},
title = {Polynomial Circuit Verification using BDDs},
journal = {CoRR},
volume = {abs/2104.03024},
year = {2021},
url = {https://arxiv.org/abs/2104.03024},
eprinttype = {arXiv},
eprint = {2104.03024},
timestamp = {Tue, 13 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2104-03024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2104-08252,
author = {Rune Krauss and
Marcel Merten and
Mirco Bockholt and
Rolf Drechsler},
title = {{ALF} - {A} Fitness-Based Artificial Life Form for Evolving Large-Scale
Neural Networks},
journal = {CoRR},
volume = {abs/2104.08252},
year = {2021},
url = {https://arxiv.org/abs/2104.08252},
eprinttype = {arXiv},
eprint = {2104.08252},
timestamp = {Mon, 19 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2104-08252.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/TorresNWD20,
author = {Frank Sill Torres and
Philipp Niemann and
Robert Wille and
Rolf Drechsler},
title = {Near Zero-Energy Computation Using Quantum-Dot Cellular Automata},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {16},
number = {1},
pages = {11:1--11:16},
year = {2020},
url = {https://doi.org/10.1145/3365394},
doi = {10.1145/3365394},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jetc/TorresNWD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/HerdtGPD20,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
Pascal Pieper and
Rolf Drechsler},
title = {{RISC-V} based virtual prototype: An extensible and configurable platform
for the system-level},
journal = {J. Syst. Archit.},
volume = {109},
pages = {101756},
year = {2020},
url = {https://doi.org/10.1016/j.sysarc.2020.101756},
doi = {10.1016/J.SYSARC.2020.101756},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/HerdtGPD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/TorresSFWNFNCWN20,
author = {Frank Sill Torres and
Pedro Arthur Silva and
Geraldo Fontes and
Marcel Walter and
Jos{\'{e}} Augusto Miranda Nacif and
Ricardo Santos Ferreira and
Omar Paranaiba Vilela Neto and
Jeferson F. Chaves and
Robert Wille and
Philipp Niemann and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {On the impact of the synchronization constraint and interconnections
in quantum-dot cellular automata},
journal = {Microprocess. Microsystems},
volume = {76},
pages = {103109},
year = {2020},
url = {https://doi.org/10.1016/j.micpro.2020.103109},
doi = {10.1016/J.MICPRO.2020.103109},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/TorresSFWNFNCWN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/qip/NiemannWD20,
author = {Philipp Niemann and
Robert Wille and
Rolf Drechsler},
title = {Advanced exact synthesis of Clifford+T circuits},
journal = {Quantum Inf. Process.},
volume = {19},
number = {1},
year = {2020},
url = {https://doi.org/10.1007/s11128-020-02816-0},
doi = {10.1007/S11128-020-02816-0},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/qip/NiemannWD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GoliSD20,
author = {Mehran Goli and
Jannis Stoppe and
Rolf Drechsler},
title = {Automated Nonintrusive Analysis of Electronic System Level Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {2},
pages = {492--505},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2018.2889665},
doi = {10.1109/TCAD.2018.2889665},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GoliSD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NiemannZDW20,
author = {Philipp Niemann and
Alwin Zulehner and
Rolf Drechsler and
Robert Wille},
title = {Overcoming the Tradeoff Between Accuracy and Compactness in Decision
Diagrams for Quantum Computation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {12},
pages = {4657--4668},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2020.2977603},
doi = {10.1109/TCAD.2020.2977603},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NiemannZDW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tetc/CuiSZWWDK20,
author = {Xiaotong Cui and
Samah Mohamed Saeed and
Alwin Zulehner and
Robert Wille and
Kaijie Wu and
Rolf Drechsler and
Ramesh Karri},
title = {On the Difficulty of Inserting Trojans in Reversible Computing Architectures},
journal = {{IEEE} Trans. Emerg. Top. Comput.},
volume = {8},
number = {4},
pages = {960--972},
year = {2020},
url = {https://doi.org/10.1109/TETC.2018.2823315},
doi = {10.1109/TETC.2018.2823315},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tetc/CuiSZWWDK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/GoliD20,
author = {Mehran Goli and
Rolf Drechsler},
title = {{PREASC:} Automatic Portion Resilience Evaluation for Approximating
SystemC-based Designs Using Regression Analysis Techniques},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {25},
number = {5},
pages = {40:1--40:28},
year = {2020},
url = {https://doi.org/10.1145/3388140},
doi = {10.1145/3388140},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/GoliD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/BornebuschLWD20,
author = {Fritjof Bornebusch and
Christoph L{\"{u}}th and
Robert Wille and
Rolf Drechsler},
title = {Towards Automatic Hardware Synthesis from Formal Specification to
Implementation},
booktitle = {25th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2020, Beijing, China, January 13-16, 2020},
pages = {375--380},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ASP-DAC47756.2020.9045406},
doi = {10.1109/ASP-DAC47756.2020.9045406},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/BornebuschLWD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/atva/HerdtGD20,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Dang Van Hung and
Oleg Sokolsky},
title = {{RVX} - {A} Tool for Concolic Testing of Embedded Binaries Targeting
{RISC-V} Platforms},
booktitle = {Automated Technology for Verification and Analysis - 18th International
Symposium, {ATVA} 2020, Hanoi, Vietnam, October 19-23, 2020, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {12302},
pages = {543--549},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-59152-6\_31},
doi = {10.1007/978-3-030-59152-6\_31},
timestamp = {Tue, 20 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/atva/HerdtGD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HerdtGD20,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Closing the {RISC-V} Compliance Gap: Looking from the Negative Testing
Side\({}^{\mbox{*}}\)},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218629},
doi = {10.1109/DAC18072.2020.9218629},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/HerdtGD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PieperHGD20,
author = {Pascal Pieper and
Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based
Virtual Prototypes},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218494},
doi = {10.1109/DAC18072.2020.9218494},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/PieperHGD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WalterWTGD20,
author = {Marcel Walter and
Robert Wille and
Frank Sill Torres and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Verification for Field-coupled Nanocomputing Circuits},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218641},
doi = {10.1109/DAC18072.2020.9218641},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/WalterWTGD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MahzoonGSD20,
author = {Alireza Mahzoon and
Daniel Gro{\ss}e and
Christoph Scholl and
Rolf Drechsler},
title = {Towards Formal Verification of Optimized and Industrial Multipliers},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2020, Grenoble, France, March 9-13, 2020},
pages = {544--549},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.23919/DATE48585.2020.9116485},
doi = {10.23919/DATE48585.2020.9116485},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/MahzoonGSD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HerdtGD20,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Fast and Accurate Performance Evaluation for {RISC-V} using Virtual
Prototypes\({}^{\mbox{*}}\)},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2020, Grenoble, France, March 9-13, 2020},
pages = {618--621},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.23919/DATE48585.2020.9116522},
doi = {10.23919/DATE48585.2020.9116522},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/HerdtGD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RingBLWD20,
author = {Martin Ring and
Fritjof Bornebusch and
Christoph L{\"{u}}th and
Robert Wille and
Rolf Drechsler},
title = {Verification Runtime Analysis: Get the Most Out of Partial Verification},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2020, Grenoble, France, March 9-13, 2020},
pages = {873--878},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.23919/DATE48585.2020.9116543},
doi = {10.23919/DATE48585.2020.9116543},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/RingBLWD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HerdtGD20a,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Towards Specification and Testing of {RISC-V} {ISA} Compliance\({}^{\mbox{{\(\star\)}}}\)},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2020, Grenoble, France, March 9-13, 2020},
pages = {995--998},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.23919/DATE48585.2020.9116193},
doi = {10.23919/DATE48585.2020.9116193},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/HerdtGD20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/LemmaGGD20,
author = {David Lemma and
Mehran Goli and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Towards Generation of a Programmable Power Management Unit at the
Electronic System Level},
booktitle = {23rd International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2020, Novi Sad, Serbia, April 22-24,
2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DDECS50862.2020.9095712},
doi = {10.1109/DDECS50862.2020.9095712},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/LemmaGGD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/Habiby0D20,
author = {Payam Habiby and
Sebastian Huhn and
Rolf Drechsler},
editor = {Luigi Dilillo and
Mihalis Psarakis and
Taniya Siddiqua},
title = {Power-aware Test Scheduling for {IEEE} 1687 Networks with Multiple
Power Domains},
booktitle = {{IEEE} International Symposium on Defect and Fault Tolerance in {VLSI}
and Nanotechnology Systems, {DFT} 2020, Frascati, Italy, October 19-21,
2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DFT50435.2020.9250874},
doi = {10.1109/DFT50435.2020.9250874},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dft/Habiby0D20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/NiemannADD20,
author = {Philipp Niemann and
Alexandre A. A. de Almeida and
Gerhard W. Dueck and
Rolf Drechsler},
title = {Design Space Exploration in the Mapping of Reversible Circuits to
{IBM} Quantum Computers},
booktitle = {23rd Euromicro Conference on Digital System Design, {DSD} 2020, Kranj,
Slovenia, August 26-28, 2020},
pages = {401--407},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DSD51259.2020.00070},
doi = {10.1109/DSD51259.2020.00070},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/NiemannADD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/GarlandoWWRTD20,
author = {Umberto Garlando and
Marcel Walter and
Robert Wille and
Fabrizio Riente and
Frank Sill Torres and
Rolf Drechsler},
title = {ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing},
booktitle = {23rd Euromicro Conference on Digital System Design, {DSD} 2020, Kranj,
Slovenia, August 26-28, 2020},
pages = {408--415},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DSD51259.2020.00071},
doi = {10.1109/DSD51259.2020.00071},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/GarlandoWWRTD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/Drechsler0P20,
author = {Rolf Drechsler and
Sebastian Huhn and
Christina Plump},
title = {Combining Machine Learning and Formal Techniques for Small Data Applications
- {A} Framework to Explore New Structural Materials},
booktitle = {23rd Euromicro Conference on Digital System Design, {DSD} 2020, Kranj,
Slovenia, August 26-28, 2020},
pages = {518--525},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DSD51259.2020.00087},
doi = {10.1109/DSD51259.2020.00087},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/Drechsler0P20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/HerdtGJD20,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
Eyck Jentzsch and
Rolf Drechsler},
title = {Efficient Cross-Level Testing for Processor Verification: {A} {RISC-}
{V} Case-Study},
booktitle = {Forum for Specification and Design Languages, {FDL} 2020, Kiel, Germany,
September 15-17, 2020},
pages = {1--7},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/FDL50818.2020.9232941},
doi = {10.1109/FDL50818.2020.9232941},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/HerdtGJD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/KraussMBFD20,
author = {Rune Krauss and
Marcel Merten and
Mirco Bockholt and
Saman Fr{\"{o}}hlich and
Rolf Drechsler},
editor = {Carlos Artemio Coello Coello},
title = {Efficient machine learning through evolving combined deep neural networks},
booktitle = {{GECCO} '20: Genetic and Evolutionary Computation Conference, Companion
Volume, Canc{\'{u}}n, Mexico, July 8-12, 2020},
pages = {215--216},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3377929.3390055},
doi = {10.1145/3377929.3390055},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/gecco/KraussMBFD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HerdtGWGD20,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
Jonas Wloka and
Tim G{\"{u}}neysu and
Rolf Drechsler},
editor = {Tinoosh Mohsenin and
Weisheng Zhao and
Yiran Chen and
Onur Mutlu},
title = {Verification of Embedded Binaries using Coverage-guided Fuzzing with
SystemC-based Virtual Prototypes},
booktitle = {{GLSVLSI} '20: Great Lakes Symposium on {VLSI} 2020, Virtual Event,
China, September 7-9, 2020},
pages = {101--106},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3386263.3406899},
doi = {10.1145/3386263.3406899},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/HerdtGWGD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/BrunsGD20,
author = {Niklas Bruns and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Tinoosh Mohsenin and
Weisheng Zhao and
Yiran Chen and
Onur Mutlu},
title = {Early Verification of {ISA} Extension Specifications using Deep Reinforcement
Learning},
booktitle = {{GLSVLSI} '20: Great Lakes Symposium on {VLSI} 2020, Virtual Event,
China, September 7-9, 2020},
pages = {297--302},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3386263.3406901},
doi = {10.1145/3386263.3406901},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/BrunsGD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/GoliMD20,
author = {Mehran Goli and
Alireza Mahzoon and
Rolf Drechsler},
title = {ASCHyRO: Automatic Fault Localization of SystemC {HLS} Designs Using
a Hybrid Accurate Rank Ordering Technique},
booktitle = {38th {IEEE} International Conference on Computer Design, {ICCD} 2020,
Hartford, CT, USA, October 18-21, 2020},
pages = {179--186},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICCD50377.2020.00043},
doi = {10.1109/ICCD50377.2020.00043},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccd/GoliMD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/HerdtGTD20,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
S{\"{o}}ren Tempel and
Rolf Drechsler},
title = {Adaptive Simulation with Virtual Prototypes for {RISC-V:} Switching
Between Fast and Accurate at Runtime},
booktitle = {38th {IEEE} International Conference on Computer Design, {ICCD} 2020,
Hartford, CT, USA, October 18-21, 2020},
pages = {312--315},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICCD50377.2020.00059},
doi = {10.1109/ICCD50377.2020.00059},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccd/HerdtGTD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifm/MeywerkWGD20,
author = {Tim Meywerk and
Marcel Walter and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Brijesh Dongol and
Elena Troubitsyna},
title = {Clustering-Guided SMT({\textdollar}{\textbackslash}mathcal \{L{\textbackslash}!R{\textbackslash}!A\}{\textdollar})
Learning},
booktitle = {Integrated Formal Methods - 16th International Conference, {IFM} 2020,
Lugano, Switzerland, November 16-20, 2020, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {12546},
pages = {41--59},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-63461-2\_3},
doi = {10.1007/978-3-030-63461-2\_3},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ifm/MeywerkWGD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/FrohlichSD20,
author = {Saman Fr{\"{o}}hlich and
Saeideh Shirinzadeh and
Rolf Drechsler},
title = {Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on {RRAM} Crossbars},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180874},
doi = {10.1109/ISCAS45731.2020.9180874},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/FrohlichSD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isdcs/KeszoczeWD20,
author = {Oliver Kesz{\"{o}}cze and
Robert Wille and
Rolf Drechsler},
title = {One-pass Synthesis for Digital Microfluidic Biochips: {A} Survey},
booktitle = {3rd International Symposium on Devices, Circuits and Systems, {ISDCS}
2020, Howrah, India, March 4-6, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISDCS49393.2020.9263007},
doi = {10.1109/ISDCS49393.2020.9263007},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isdcs/KeszoczeWD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/BhattacharjeeBM20,
author = {Anirban Bhattacharjee and
Chandan Bandyopadhyay and
Angshu Mukherjee and
Robert Wille and
Rolf Drechsler and
Hafizur Rahaman},
title = {Efficient Implementation of Nearest Neighbor Quantum Circuits Using
Clustering with Genetic Algorithm},
booktitle = {50th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2020, Miyazaki, Japan, November 9-11, 2020},
pages = {40--45},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISMVL49045.2020.00-32},
doi = {10.1109/ISMVL49045.2020.00-32},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ismvl/BhattacharjeeBM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/FrohlichKGD20,
author = {Saman Fr{\"{o}}hlich and
Lucas Klemmer and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {ASNet: Introducing Approximate Hardware to High-Level Synthesis of
Neural Networks},
booktitle = {50th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2020, Miyazaki, Japan, November 9-11, 2020},
pages = {64--69},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISMVL49045.2020.00-28},
doi = {10.1109/ISMVL49045.2020.00-28},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ismvl/FrohlichKGD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isola/MeywerkWHKGD20,
author = {Tim Meywerk and
Marcel Walter and
Vladimir Herdt and
Jan Kleinekath{\"{o}}fer and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Tiziana Margaria and
Bernhard Steffen},
title = {Verifying Safety Properties of Robotic Plans Operating in Real-World
Environments via Logic-Based Environment Modeling},
booktitle = {Leveraging Applications of Formal Methods, Verification and Validation:
Applications - 9th International Symposium on Leveraging Applications
of Formal Methods, ISoLA 2020, Rhodes, Greece, October 20-30, 2020,
Proceedings, Part {III}},
series = {Lecture Notes in Computer Science},
volume = {12478},
pages = {326--347},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-61467-6\_21},
doi = {10.1007/978-3-030-61467-6\_21},
timestamp = {Sat, 14 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isola/MeywerkWHKGD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/WalterWTD20,
author = {Marcel Walter and
Robert Wille and
Frank Sill Torres and
Rolf Drechsler},
title = {Bail on Balancing: An Alternative Approach to the Physical Design
of Field-Coupled Nanocomputing Circuits},
booktitle = {2020 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2020,
Limassol, Cyprus, July 6-8, 2020},
pages = {66--71},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISVLSI49217.2020.00022},
doi = {10.1109/ISVLSI49217.2020.00022},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/WalterWTD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/WalterD20,
author = {Marcel Walter and
Rolf Drechsler},
title = {Design Automation for Field-Coupled Nanotechnologies},
booktitle = {2020 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2020,
Limassol, Cyprus, July 6-8, 2020},
pages = {176--181},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISVLSI49217.2020.00040},
doi = {10.1109/ISVLSI49217.2020.00040},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/WalterD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/HerdtD20,
author = {Vladimir Herdt and
Rolf Drechsler},
title = {Efficient Techniques to Strongly Enhance the Virtual Prototype Based
Design Flow},
booktitle = {2020 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2020,
Limassol, Cyprus, July 6-8, 2020},
pages = {182--187},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISVLSI49217.2020.00041},
doi = {10.1109/ISVLSI49217.2020.00041},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/HerdtD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/GoliD20,
author = {Mehran Goli and
Rolf Drechsler},
title = {Automated Design Understanding of SystemC-Based Virtual Prototypes:
Data Extraction, Analysis and Visualization},
booktitle = {2020 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2020,
Limassol, Cyprus, July 6-8, 2020},
pages = {188--193},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISVLSI49217.2020.00042},
doi = {10.1109/ISVLSI49217.2020.00042},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/GoliD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/modelsward/BornebuschLWD20a,
author = {Fritjof Bornebusch and
Christoph L{\"{u}}th and
Robert Wille and
Rolf Drechsler},
editor = {Slimane Hammoudi and
Lu{\'{\i}}s Ferreira Pires and
Bran Selic},
title = {Safety First: About the Detection of Arithmetic Overflows in Hardware
Design Specifications},
booktitle = {Model-Driven Engineering and Software Development - 8th International
Conference, {MODELSWARD} 2020, Valletta, Malta, February 25-27, 2020,
Revised Selected Papers},
series = {Communications in Computer and Information Science},
volume = {1361},
pages = {26--48},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-67445-8\_2},
doi = {10.1007/978-3-030-67445-8\_2},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/modelsward/BornebuschLWD20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/modelsward/BornebuschLWD20,
author = {Fritjof Bornebusch and
Christoph L{\"{u}}th and
Robert Wille and
Rolf Drechsler},
editor = {Slimane Hammoudi and
Lu{\'{\i}}s Ferreira Pires and
Bran Selic},
title = {Integer Overflow Detection in Hardware Designs at the Specification
Level},
booktitle = {Proceedings of the 8th International Conference on Model-Driven Engineering
and Software Development, {MODELSWARD} 2020, Valletta, Malta, February
25-27, 2020},
pages = {41--48},
publisher = {{SCITEPRESS}},
year = {2020},
url = {https://doi.org/10.5220/0008960200410048},
doi = {10.5220/0008960200410048},
timestamp = {Tue, 06 Jun 2023 14:58:00 +0200},
biburl = {https://dblp.org/rec/conf/modelsward/BornebuschLWD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sigcse/SerajKAD20,
author = {Mazyar Seraj and
Eva{-}Sophie Katterfeldt and
Serge Autexier and
Rolf Drechsler},
editor = {Jian Zhang and
Mark Sherriff and
Sarah Heckman and
Pamela A. Cutter and
Alvaro E. Monge},
title = {Impacts of Creating Smart Everyday Objects on Young Female Students'
Programming Skills and Attitudes},
booktitle = {Proceedings of the 51st {ACM} Technical Symposium on Computer Science
Education, {SIGCSE} 2020, Portland, OR, USA, March 11-14, 2020},
pages = {1234--1240},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3328778.3366841},
doi = {10.1145/3328778.3366841},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sigcse/SerajKAD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/BandyopadhyayWD20,
author = {Chandan Bandyopadhyay and
Robert Wille and
Rolf Drechsler and
Hafizur Rahaman},
title = {Post Synthesis-Optimization of Reversible Circuit using Template Matching},
booktitle = {2020 24th International Symposium on {VLSI} Design and Test (VDAT),
Bhubaneswar, India, July 23-25, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VDAT50263.2020.9190279},
doi = {10.1109/VDAT50263.2020.9190279},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vdat/BandyopadhyayWD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2009-03242,
author = {Rolf Drechsler},
title = {PolyAdd: Polynomial Formal Verification of Adder Circuits},
journal = {CoRR},
volume = {abs/2009.03242},
year = {2020},
url = {https://arxiv.org/abs/2009.03242},
eprinttype = {arXiv},
eprint = {2009.03242},
timestamp = {Thu, 17 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2009-03242.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/it/BachePWGD19,
author = {Florian Bache and
Christina Plump and
Jonas Wloka and
Tim G{\"{u}}neysu and
Rolf Drechsler},
title = {Evaluation of (power) side-channels in cryptographic implementations},
journal = {it Inf. Technol.},
volume = {61},
number = {1},
pages = {15--28},
year = {2019},
url = {https://doi.org/10.1515/itit-2018-0028},
doi = {10.1515/ITIT-2018-0028},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/it/BachePWGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/it/GoliHGD19,
author = {Mehran Goli and
Muhammad Hassan and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Security validation of VP-based SoCs using dynamic information flow
tracking},
journal = {it Inf. Technol.},
volume = {61},
number = {1},
pages = {45--58},
year = {2019},
url = {https://doi.org/10.1515/itit-2018-0027},
doi = {10.1515/ITIT-2018-0027},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/it/GoliHGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/WalterWGTD19,
author = {Marcel Walter and
Robert Wille and
Daniel Gro{\ss}e and
Frank Sill Torres and
Rolf Drechsler},
title = {Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits
Is \emph{NP}-complete (Research Note)},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {15},
number = {3},
pages = {29:1--29:10},
year = {2019},
url = {https://doi.org/10.1145/3312661},
doi = {10.1145/3312661},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/WalterWGTD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sttt/HerdtLGD19,
author = {Vladimir Herdt and
Hoang M. Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Combining sequentialization-based verification of multi-threaded {C}
programs with symbolic Partial Order Reduction},
journal = {Int. J. Softw. Tools Technol. Transf.},
volume = {21},
number = {5},
pages = {545--565},
year = {2019},
url = {https://doi.org/10.1007/s10009-019-00507-5},
doi = {10.1007/S10009-019-00507-5},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sttt/HerdtLGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HerdtLGD19,
author = {Vladimir Herdt and
Hoang M. Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Verifying SystemC Using Intermediate Verification Language and Stateful
Symbolic Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {7},
pages = {1359--1372},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2846638},
doi = {10.1109/TCAD.2018.2846638},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HerdtLGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AliotoAABBCCCCC19,
author = {Massimo Alioto and
Magdy S. Abadir and
Tughrul Arslan and
Chirn Chye Boon and
Andreas Burg and
Chip{-}Hong Chang and
Meng{-}Fan Chang and
Yao{-}Wen Chang and
Poki Chen and
Pasquale Corsonello and
Paolo Crovetti and
Shiro Dosho and
Rolf Drechsler and
Ibrahim Abe M. Elfadel and
Ruonan Han and
Masanori Hashimoto and
Chun{-}Huat Heng and
Deukhyoun Heo and
Tsung{-}Yi Ho and
Houman Homayoun and
Yuh{-}Shyan Hwang and
Ajay Joshi and
Rajiv V. Joshi and
Tanay Karnik and
Chulwoo Kim and
Tony Tae{-}Hyoung Kim and
Jaydeep Kulkarni and
Volkan Kursun and
Yoonmyung Lee and
Hai Helen Li and
Huawei Li and
Prabhat Mishra and
Baker Mohammad and
Mehran Mozaffari Kermani and
Makoto Nagata and
Koji Nii and
Partha Pratim Pande and
Bipul C. Paul and
Vasilis F. Pavlidis and
Jos{\'{e}} Pineda de Gyvez and
Ioannis Savidis and
Patrick Schaumont and
Fabio Sebastiano and
Anirban Sengupta and
Mingoo Seok and
Mircea R. Stan and
Mark M. Tehranipoor and
Aida Todri{-}Sanial and
Marian Verhelst and
Valerio Vignoli and
Xiaoqing Wen and
Jiang Xu and
Wei Zhang and
Zhengya Zhang and
Jun Zhou and
Mark Zwolinski and
Stacey Weber},
title = {Editorial {TVLSI} Positioning - Continuing and Accelerating an Upward
Trajectory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {253--280},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2886389},
doi = {10.1109/TVLSI.2018.2886389},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AliotoAABBCCCCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuhnFWD19,
author = {Sebastian Huhn and
Stefan Frehse and
Robert Wille and
Rolf Drechsler},
title = {Determining Application-Specific Knowledge for Improving Robustness
of Sequential Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {875--887},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2890601},
doi = {10.1109/TVLSI.2018.2890601},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuhnFWD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SaeedZWDK19,
author = {Samah Mohamed Saeed and
Alwin Zulehner and
Robert Wille and
Rolf Drechsler and
Ramesh Karri},
title = {Reversible Circuits: {IC/IP} Piracy Attacks and Countermeasures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2523--2535},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2934465},
doi = {10.1109/TVLSI.2019.2934465},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SaeedZWDK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/acmidc/SerajGAD19,
author = {Mazyar Seraj and
Cornelia S. Gro{\ss}e and
Serge Autexier and
Rolf Drechsler},
title = {Smart Homes Programming: Development and Evaluation of an Educational
Programming Application for Young Learners},
booktitle = {Proceedings of the 18th {ACM} International Conference on Interaction
Design and Children, {IDC} 2019, Boise, ID, USA, June 12-15, 2019},
pages = {146--152},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3311927.3323157},
doi = {10.1145/3311927.3323157},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/acmidc/SerajGAD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/SchmitzUGD19,
author = {Kenneth Schmitz and
Buse Ustaoglu and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Christian Hochberger and
Brent Nelson and
Andreas Koch and
Roger F. Woods and
Pedro C. Diniz},
title = {(ReCo)Fuse Your {PRC} or Lose Security: Finally Reliable Reconfiguration-Based
Countermeasures on FPGAs},
booktitle = {Applied Reconfigurable Computing - 15th International Symposium, {ARC}
2019, Darmstadt, Germany, April 9-11, 2019, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {11444},
pages = {112--126},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-17227-5\_9},
doi = {10.1007/978-3-030-17227-5\_9},
timestamp = {Tue, 14 May 2019 10:00:49 +0200},
biburl = {https://dblp.org/rec/conf/arc/SchmitzUGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WalterWTGD19,
author = {Marcel Walter and
Robert Wille and
Frank Sill Torres and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Toshiyuki Shibuya},
title = {Scalable design for field-coupled nanocomputing circuits},
booktitle = {Proceedings of the 24th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2019, Tokyo, Japan, January 21-24, 2019},
pages = {197--202},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3287624.3287705},
doi = {10.1145/3287624.3287705},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WalterWTGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HerdtLGD19,
author = {Vladimir Herdt and
Hoang M. Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Toshiyuki Shibuya},
title = {Maximizing power state cross coverage in firmware-based power management},
booktitle = {Proceedings of the 24th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2019, Tokyo, Japan, January 21-24, 2019},
pages = {335--340},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3287624.3287631},
doi = {10.1145/3287624.3287631},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/HerdtLGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/DrechlserG19,
author = {Rolf Drechsler and
Daniel Gro{\ss}e},
title = {Ensuring Correctness of Next Generation Devices: From Reconfigurable
to Self-Learning Systems},
booktitle = {28th {IEEE} Asian Test Symposium, {ATS} 2019, Kolkata, India, December
10-13, 2019},
pages = {159--164},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ATS47505.2019.00029},
doi = {10.1109/ATS47505.2019.00029},
timestamp = {Thu, 25 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/DrechlserG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MahzoonGD19,
author = {Alireza Mahzoon and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting
for Big and Dirty Multipliers},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {185},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3317898},
doi = {10.1145/3316781.3317898},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/MahzoonGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MassoudLCSMD19,
author = {Rehab Massoud and
Hoang M. Le and
Peter Chini and
Prakash Saivasan and
Roland Meyer and
Rolf Drechsler},
title = {Temporal Tracing of On-Chip Signals using Timeprints},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {186},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3317920},
doi = {10.1145/3316781.3317920},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/MassoudLCSMD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HerdtGLD19,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
Hoang M. Le and
Rolf Drechsler},
title = {Early Concolic Testing of Embedded Binaries with Virtual Prototypes:
{A} {RISC-V} Case Study},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {188},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3317807},
doi = {10.1145/3316781.3317807},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/HerdtGLD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ZulehnerNDW19,
author = {Alwin Zulehner and
Philipp Niemann and
Rolf Drechsler and
Robert Wille},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {Accuracy and Compactness in Decision Diagrams for Quantum Computation},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {280--283},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8715040},
doi = {10.23919/DATE.2019.8715040},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ZulehnerNDW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/FrohlichGD19,
author = {Saman Fr{\"{o}}hlich and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {One Method - All Error-Metrics: {A} Three-Stage Approach for Error-Metric
Evaluation in Approximate Computing},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {284--287},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8715138},
doi = {10.23919/DATE.2019.8715138},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/FrohlichGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HerdtGLD19,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
Hoang M. Le and
Rolf Drechsler},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {Verifying Instruction Set Simulators using Coverage-guided Fuzzing\({}^{\mbox{*}}\)},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {360--365},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8714912},
doi = {10.23919/DATE.2019.8714912},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/HerdtGLD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HassanGLD19,
author = {Muhammad Hassan and
Daniel Gro{\ss}e and
Hoang M. Le and
Rolf Drechsler},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {Data Flow Testing for SystemC-AMS Timed Data Flow Models},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {366--371},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8714903},
doi = {10.23919/DATE.2019.8714903},
timestamp = {Wed, 09 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/HassanGLD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LeGBD19,
author = {Hoang M. Le and
Daniel Gro{\ss}e and
Niklas Bruns and
Rolf Drechsler},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {Detection of Hardware Trojans in SystemC {HLS} Designs via Coverage-guided
Fuzzing},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {602--605},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8714927},
doi = {10.23919/DATE.2019.8714927},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/LeGBD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RingBLWD19,
author = {Martin Ring and
Fritjof Bornebusch and
Christoph L{\"{u}}th and
Robert Wille and
Rolf Drechsler},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {Better Late Than Never : Verification of Embedded Systems After Deployment},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {890--895},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8714967},
doi = {10.23919/DATE.2019.8714967},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/RingBLWD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/DrechslerL19,
author = {Rolf Drechsler and
Christoph L{\"{u}}th},
title = {Code is Ethics - Formal Techniques for a Better World},
booktitle = {22nd Euromicro Conference on Digital System Design, {DSD} 2019, Kallithea,
Greece, August 28-30, 2019},
pages = {1--3},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/DSD.2019.00011},
doi = {10.1109/DSD.2019.00011},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/DrechslerL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/Ustaoglu0TGD19,
author = {Buse Ustaoglu and
Sebastian Huhn and
Frank Sill Torres and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {SAT-Hard: {A} Learning-Based Hardware SAT-Solver},
booktitle = {22nd Euromicro Conference on Digital System Design, {DSD} 2019, Kallithea,
Greece, August 28-30, 2019},
pages = {74--81},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/DSD.2019.00021},
doi = {10.1109/DSD.2019.00021},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/Ustaoglu0TGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/MeywerkWHGD19,
author = {Tim Meywerk and
Marcel Walter and
Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Towards Formal Verification of Plans for Cognition-Enabled Autonomous
Robotic Agents},
booktitle = {22nd Euromicro Conference on Digital System Design, {DSD} 2019, Kallithea,
Greece, August 28-30, 2019},
pages = {129--136},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/DSD.2019.00029},
doi = {10.1109/DSD.2019.00029},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/MeywerkWHGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/GoliD19,
author = {Mehran Goli and
Rolf Drechsler},
title = {Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes},
booktitle = {22nd Euromicro Conference on Digital System Design, {DSD} 2019, Kallithea,
Greece, August 28-30, 2019},
pages = {522--529},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/DSD.2019.00081},
doi = {10.1109/DSD.2019.00081},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/GoliD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/0001TD19,
author = {Sebastian Huhn and
Daniel Tille and
Rolf Drechsler},
title = {Hybrid Architecture for Embedded Test Compression to Process Rejected
Test Patterns},
booktitle = {24th {IEEE} European Test Symposium, {ETS} 2019, Baden-Baden, Germany,
May 27-31, 2019},
pages = {1--2},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ETS.2019.8791508},
doi = {10.1109/ETS.2019.8791508},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/0001TD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/DhotreECD19,
author = {Harshad Dhotre and
Stephan Eggersgl{\"{u}}{\ss} and
Krishnendu Chakrabarty and
Rolf Drechsler},
title = {Machine Learning-based Prediction of Test Power},
booktitle = {24th {IEEE} European Test Symposium, {ETS} 2019, Baden-Baden, Germany,
May 27-31, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ETS.2019.8791548},
doi = {10.1109/ETS.2019.8791548},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/DhotreECD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/HassanGVED19,
author = {Muhammad Hassan and
Daniel Gro{\ss}e and
Thilo V{\"{o}}rtler and
Karsten Einwich and
Rolf Drechsler},
editor = {Tom J. Kazmierski and
Reinhard von Hanxleden and
Terrence S. T. Mak},
title = {Functional Coverage-Driven Characterization of {RF} Amplifiers},
booktitle = {2019 Forum for Specification and Design Languages, {FDL} 2019, Southampton,
United Kingdom, September 2-4, 2019},
pages = {1--8},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/FDL.2019.8876957},
doi = {10.1109/FDL.2019.8876957},
timestamp = {Wed, 09 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/HassanGVED19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/HerdtGDGJB0SSK19,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler and
Christoph Gerum and
Alexander Jung and
Joscha Benz and
Oliver Bringmann and
Michael Schwarz and
Dominik Stoffel and
Wolfgang Kunz},
editor = {Tom J. Kazmierski and
Reinhard von Hanxleden and
Terrence S. T. Mak},
title = {Systematic {RISC-V} based Firmware Design\({}^{\mbox{{\(\star\)}}}\)},
booktitle = {2019 Forum for Specification and Design Languages, {FDL} 2019, Southampton,
United Kingdom, September 2-4, 2019},
pages = {1--8},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/FDL.2019.8876945},
doi = {10.1109/FDL.2019.8876945},
timestamp = {Fri, 21 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/HerdtGDGJB0SSK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/formats/MassoudLD19,
author = {Rehab Massoud and
Hoang M. Le and
Rolf Drechsler},
editor = {{\'{E}}tienne Andr{\'{e}} and
Mari{\"{e}}lle Stoelinga},
title = {Property-Driven Timestamps Encoding for Timeprints-Based Tracing and
Monitoring},
booktitle = {Formal Modeling and Analysis of Timed Systems - 17th International
Conference, {FORMATS} 2019, Amsterdam, The Netherlands, August 27-29,
2019, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {11750},
pages = {41--58},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-29662-9\_3},
doi = {10.1007/978-3-030-29662-9\_3},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/formats/MassoudLD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GoliHGD19,
author = {Mehran Goli and
Muhammad Hassan and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Houman Homayoun and
Baris Taskin and
Tinoosh Mohsenin and
Weisheng Zhao},
title = {Automated Analysis of Virtual Prototypes at Electronic System Level},
booktitle = {Proceedings of the 2019 on Great Lakes Symposium on VLSI, {GLSVLSI}
2019, Tysons Corner, VA, USA, May 9-11, 2019},
pages = {307--310},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3299874.3318024},
doi = {10.1145/3299874.3318024},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/GoliHGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icse/SerajGAD19,
author = {Mazyar Seraj and
Cornelia S. Gro{\ss}e and
Serge Autexier and
Rolf Drechsler},
editor = {Sarah Beecham and
Daniela E. Damian},
title = {Look what {I} can do: acquisition of programming skills in the context
of living labs},
booktitle = {Proceedings of the 41st International Conference on Software Engineering:
Software Engineering Education and Training, {ICSE} {(SEET)} 2019,
Montreal, QC, Canada, May 25-31, 2019},
pages = {197--207},
publisher = {{IEEE} / {ACM}},
year = {2019},
url = {https://doi.org/10.1109/ICSE-SEET.2019.00029},
doi = {10.1109/ICSE-SEET.2019.00029},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icse/SerajGAD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/irps/TorresAHD19,
author = {Frank Sill Torres and
Hussam Amrouch and
J{\"{o}}rg Henkel and
Rolf Drechsler},
title = {Impact of {NBTI} on Increasing the Susceptibility of FinFET to Radiation},
booktitle = {{IEEE} International Reliability Physics Symposium, {IRPS} 2019, Monterey,
CA, USA, March 31 - April 4, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/IRPS.2019.8720468},
doi = {10.1109/IRPS.2019.8720468},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/irps/TorresAHD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/TorresOD19,
author = {Frank Sill Torres and
Alberto Garc{\'{\i}}a Ortiz and
Rolf Drechsler},
title = {HotAging - Impact of Power Dissipation on Hardware Degradation},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702073},
doi = {10.1109/ISCAS.2019.8702073},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/TorresOD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/ZulehnerNDW19,
author = {Alwin Zulehner and
Philipp Niemann and
Rolf Drechsler and
Robert Wille},
title = {One Additional Qubit is Enough: Encoded Embeddings for Boolean Components
in Quantum Circuits},
booktitle = {2019 {IEEE} 49th International Symposium on Multiple-Valued Logic
(ISMVL), Fredericton, NB, Canada, May 21-23, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISMVL.2019.00009},
doi = {10.1109/ISMVL.2019.00009},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/ZulehnerNDW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/NiemannGD19,
author = {Philipp Niemann and
Anshu Gupta and
Rolf Drechsler},
title = {T-depth Optimization for Fault-Tolerant Quantum Circuits},
booktitle = {2019 {IEEE} 49th International Symposium on Multiple-Valued Logic
(ISMVL), Fredericton, NB, Canada, May 21-23, 2019},
pages = {108--113},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISMVL.2019.00027},
doi = {10.1109/ISMVL.2019.00027},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/NiemannGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/FrohlichSD19,
author = {Saman Fr{\"{o}}hlich and
Saeideh Shirinzadeh and
Rolf Drechsler},
title = {Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits},
booktitle = {2019 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2019,
Miami, FL, USA, July 15-17, 2019},
pages = {431--436},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISVLSI.2019.00084},
doi = {10.1109/ISVLSI.2019.00084},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/FrohlichSD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/WilleWTGD19,
author = {Robert Wille and
Marcel Walter and
Frank Sill Torres and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Ignore Clocking Constraints: An Alternative Physical Design Methodology
for Field-Coupled Nanotechnologies},
booktitle = {2019 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2019,
Miami, FL, USA, July 15-17, 2019},
pages = {651--656},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISVLSI.2019.00121},
doi = {10.1109/ISVLSI.2019.00121},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/WilleWTGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc-asia/0001TD19,
author = {Sebastian Huhn and
Daniel Tille and
Rolf Drechsler},
title = {A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin
Count Test Environments in Safety-Critical Systems},
booktitle = {{IEEE} International Test Conference in Asia, ITC-Asia 2019, Tokyo,
Japan, September 3-5, 2019},
pages = {115--120},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ITC-Asia.2019.00033},
doi = {10.1109/ITC-ASIA.2019.00033},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc-asia/0001TD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/kolicalling/SerajKBAD19,
author = {Mazyar Seraj and
Eva{-}Sophie Katterfeldt and
Kerstin Bub and
Serge Autexier and
Rolf Drechsler},
editor = {Petri Ihantola and
Nick Falkner},
title = {Scratch and Google Blockly: How Girls' Programming Skills and Attitudes
are Influenced},
booktitle = {Koli Calling '19: 19th Koli Calling International Conference on Computing
Education Research, Koli, Finland, November 21-24, 2019},
pages = {23:1--23:10},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3364510.3364515},
doi = {10.1145/3364510.3364515},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/kolicalling/SerajKBAD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/DhotreED19,
author = {Harshad Dhotre and
Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {Cluster-based Localization of IR-drop in Test Application considering
Parasitic Elements},
booktitle = {{IEEE} Latin American Test Symposium, {LATS} 2019, Santiago, Chile,
March 11-13, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/LATW.2019.8704618},
doi = {10.1109/LATW.2019.8704618},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/latw/DhotreED19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/FeyD19,
author = {G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {Self-Explaining Digital Systems - Some Technical Steps},
booktitle = {22nd Workshop Methods and Description Languages for Modelling and
Verification of Circuits and Systems, {MBMV} 2019, Kaiserslautern,
Germany, March 8-9, 2019},
pages = {1--8},
publisher = {{VDE} Verlag},
year = {2019},
url = {https://ieeexplore.ieee.org/document/8727157/},
timestamp = {Thu, 11 Jul 2019 17:44:24 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/FeyD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nanoarch/FrerixSFD19,
author = {Steffen Frerix and
Saeideh Shirinzadeh and
Saman Fr{\"{o}}hlich and
Rolf Drechsler},
title = {ComPRIMe: {A} Compiler for Parallel and Scalable ReRAM-based In-Memory
Computing},
booktitle = {{IEEE/ACM} International Symposium on Nanoscale Architectures, {NANOARCH}
2019, Qingdao, China, July 17-19, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/NANOARCH47378.2019.181285},
doi = {10.1109/NANOARCH47378.2019.181285},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nanoarch/FrerixSFD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/BhattacharjeeBW19,
author = {Anirban Bhattacharjee and
Chandan Bandyopadhyay and
Robert Wille and
Rolf Drechsler and
Hafizur Rahaman},
title = {Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D
Quantum Circuits},
booktitle = {32nd International Conference on {VLSI} Design and 18th International
Conference on Embedded Systems, {VLSID} 2019, Delhi, India, January
5-9, 2019},
pages = {203--208},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSID.2019.00054},
doi = {10.1109/VLSID.2019.00054},
timestamp = {Mon, 14 Nov 2022 15:28:06 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/BhattacharjeeBW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/19/FrohlichGD19,
author = {Saman Fr{\"{o}}hlich and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Sherief Reda and
Muhammad Shafique},
title = {Approximate Hardware Generation Using Formal Techniques},
booktitle = {Approximate Circuits, Methodologies and {CAD}},
pages = {155--174},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-319-99322-5\_8},
doi = {10.1007/978-3-319-99322-5\_8},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/books/sp/19/FrohlichGD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1905-02477,
author = {Marcel Walter and
Robert Wille and
Frank Sill Torres and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {fiction: An Open Source Framework for the Design of Field-coupled
Nanocomputing Circuits},
journal = {CoRR},
volume = {abs/1905.02477},
year = {2019},
url = {http://arxiv.org/abs/1905.02477},
eprinttype = {arXiv},
eprint = {1905.02477},
timestamp = {Mon, 27 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1905-02477.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1906-02352,
author = {Alwin Zulehner and
Philipp Niemann and
Rolf Drechsler and
Robert Wille},
title = {One Additional Qubit is Enough: Encoded Embeddings for Boolean Components
in Quantum Circuits},
journal = {CoRR},
volume = {abs/1906.02352},
year = {2019},
url = {http://arxiv.org/abs/1906.02352},
eprinttype = {arXiv},
eprint = {1906.02352},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1906-02352.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0045943,
author = {Nils Przigoda and
Robert Wille and
Judith Przigoda and
Rolf Drechsler},
title = {Automated Validation {\&} Verification of {UML/OCL} Models Using
Satisfiability Solvers},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-72814-8},
doi = {10.1007/978-3-319-72814-8},
isbn = {978-3-319-72813-1},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0045943.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cl/PrzigodaNFWD18,
author = {Nils Przigoda and
Philipp Niemann and
Jonas Gomes Filho and
Robert Wille and
Rolf Drechsler},
title = {Frame conditions in the automatic validation and verification of {UML/OCL}
models: {A} symbolic formulation of \emph{modifies only} statements},
journal = {Comput. Lang. Syst. Struct.},
volume = {54},
pages = {512--527},
year = {2018},
url = {https://doi.org/10.1016/j.cl.2017.11.002},
doi = {10.1016/J.CL.2017.11.002},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cl/PrzigodaNFWD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipl/KeszoczeSD18,
author = {Oliver Kesz{\"{o}}cze and
Mathias Soeken and
Rolf Drechsler},
title = {The complexity of error metrics},
journal = {Inf. Process. Lett.},
volume = {139},
pages = {1--7},
year = {2018},
url = {https://doi.org/10.1016/j.ipl.2018.06.010},
doi = {10.1016/J.IPL.2018.06.010},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipl/KeszoczeSD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/DiepenbeckKSGD18,
author = {Melanie Diepenbeck and
Ulrich K{\"{u}}hne and
Mathias Soeken and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Behaviour Driven Development for Hardware Design},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {11},
pages = {29--45},
year = {2018},
url = {https://doi.org/10.2197/ipsjtsldm.11.29},
doi = {10.2197/IPSJTSLDM.11.29},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/DiepenbeckKSGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/BandyopadhyayDW18,
author = {Chandan Bandyopadhyay and
Rakesh Das and
Robert Wille and
Rolf Drechsler and
Hafizur Rahaman},
title = {Synthesis of circuits based on all-optical Mach-Zehnder Interferometers
using Binary Decision Diagrams},
journal = {Microelectron. J.},
volume = {71},
pages = {19--29},
year = {2018},
url = {https://doi.org/10.1016/j.mejo.2017.11.008},
doi = {10.1016/J.MEJO.2017.11.008},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/BandyopadhyayDW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/KeszoczeNFD18,
author = {Oliver Kesz{\"{o}}cze and
Philipp Niemann and
Arved Friedemann and
Rolf Drechsler},
title = {On the complexity of design tasks for Digital Microfluidic Biochips},
journal = {Microelectron. J.},
volume = {78},
pages = {35--45},
year = {2018},
url = {https://doi.org/10.1016/j.mejo.2018.05.013},
doi = {10.1016/J.MEJO.2018.05.013},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/KeszoczeNFD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShirinzadehSGD18,
author = {Saeideh Shirinzadeh and
Mathias Soeken and
Pierre{-}Emmanuel Gaillardon and
Rolf Drechsler},
title = {Logic Synthesis for RRAM-Based In-Memory Computing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1422--1435},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2750064},
doi = {10.1109/TCAD.2017.2750064},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShirinzadehSGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TorresWND18,
author = {Frank Sill Torres and
Robert Wille and
Philipp Niemann and
Rolf Drechsler},
title = {An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular
Automata},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3031--3041},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789782},
doi = {10.1109/TCAD.2018.2789782},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/TorresWND18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Chandrasekharan18,
author = {Arun Chandrasekharan and
Stephan Eggersgl{\"{u}}{\ss} and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Youngsoo Shin},
title = {Approximation-aware testing for approximate circuits},
booktitle = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2018, Jeju, Korea (South), January 22-25, 2018},
pages = {239--244},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASPDAC.2018.8297312},
doi = {10.1109/ASPDAC.2018.8297312},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/Chandrasekharan18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WalterWGTD18,
author = {Marcel Walter and
Robert Wille and
Daniel Gro{\ss}e and
Frank Sill Torres and
Rolf Drechsler},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {An exact method for design exploration of quantum-dot cellular automata},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {503--508},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342060},
doi = {10.23919/DATE.2018.8342060},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/WalterWGTD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/NiemannWD18,
author = {Philipp Niemann and
Robert Wille and
Rolf Drechsler},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Improved synthesis of Clifford+T quantum functionality},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {597--600},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342078},
doi = {10.23919/DATE.2018.8342078},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/NiemannWD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LeHGD18,
author = {Hoang M. Le and
Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Resilience evaluation via symbolic fault injection on intermediate
code},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {845--850},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342123},
doi = {10.23919/DATE.2018.8342123},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/LeHGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HassanGLVED18,
author = {Muhammad Hassan and
Daniel Gro{\ss}e and
Hoang M. Le and
Thilo V{\"{o}}rtler and
Karsten Einwich and
Rolf Drechsler},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Testbench qualification for SystemC-AMS timed data flow models},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {857--860},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342125},
doi = {10.23919/DATE.2018.8342125},
timestamp = {Wed, 09 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/HassanGLVED18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/FrohlichGD18,
author = {Saman Fr{\"{o}}hlich and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Approximate hardware generation using symbolic computer algebra employing
grobner basis},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {889--892},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342133},
doi = {10.23919/DATE.2018.8342133},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/FrohlichGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HerdtLGD18,
author = {Vladimir Herdt and
Hoang M. Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Towards fully automated TLM-to-RTL property refinement},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {1508--1511},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342253},
doi = {10.23919/DATE.2018.8342253},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/HerdtLGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/DhotreEDDP18,
author = {Harshad Dhotre and
Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler and
Mehdi Dehbashi and
Ulrike Pfannkuchen},
title = {Constraint-Based Pattern Retargeting for Reducing Localized Power
Activity During Testing},
booktitle = {21st {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2018, Budapest, Hungary, April
25-27, 2018},
pages = {79--84},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/DDECS.2018.00021},
doi = {10.1109/DDECS.2018.00021},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/DhotreEDDP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/LemmaGD18,
author = {David Lemma and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Natural Language Based Power Domain Partitioning},
booktitle = {21st {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2018, Budapest, Hungary, April
25-27, 2018},
pages = {101--106},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/DDECS.2018.00025},
doi = {10.1109/DDECS.2018.00025},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/LemmaGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/TorresSFNFNCD18,
author = {Frank Sill Torres and
Pedro Arthur Silva and
Geraldo Fontes and
Jos{\'{e}} Augusto Miranda Nacif and
Ricardo Santos Ferreira and
Omar Paranaiba Vilela Neto and
Jeferson F. Chaves and
Rolf Drechsler},
editor = {Martin Novotn{\'{y}} and
Nikos Konofaos and
Amund Skavhaug},
title = {Exploration of the Synchronization Constraint in Quantum-dot Cellular
Automata},
booktitle = {21st Euromicro Conference on Digital System Design, {DSD} 2018, Prague,
Czech Republic, August 29-31, 2018},
pages = {642--648},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/DSD.2018.00109},
doi = {10.1109/DSD.2018.00109},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/TorresSFNFNCD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/TorresWWNGD18,
author = {Frank Sill Torres and
Robert Wille and
Marcel Walter and
Philipp Niemann and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Martin Novotn{\'{y}} and
Nikos Konofaos and
Amund Skavhaug},
title = {Evaluating the Impact of Interconnections in Quantum-Dot Cellular
Automata},
booktitle = {21st Euromicro Conference on Digital System Design, {DSD} 2018, Prague,
Czech Republic, August 29-31, 2018},
pages = {649--656},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/DSD.2018.00110},
doi = {10.1109/DSD.2018.00110},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/TorresWWNGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/FrohlichGD18,
author = {Saman Fr{\"{o}}hlich and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Martin Novotn{\'{y}} and
Nikos Konofaos and
Amund Skavhaug},
title = {Towards Reversed Approximate Hardware Design},
booktitle = {21st Euromicro Conference on Digital System Design, {DSD} 2018, Prague,
Czech Republic, August 29-31, 2018},
pages = {665--671},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/DSD.2018.00112},
doi = {10.1109/DSD.2018.00112},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/FrohlichGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/HerdtGLD18,
author = {Vladimir Herdt and
Daniel Gro{\ss}e and
Hoang M. Le and
Rolf Drechsler},
editor = {Hiren D. Patel and
Tom J. Kazmierski and
Sebastian Steinhorst},
title = {Extensible and Configurable {RISC-V} Based Virtual Prototype},
booktitle = {2018 Forum on Specification {\&} Design Languages, {FDL} 2018,
Garching, Germany, September 10-12, 2018},
pages = {5--16},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/FDL.2018.8524047},
doi = {10.1109/FDL.2018.8524047},
timestamp = {Tue, 29 Nov 2022 08:40:57 +0100},
biburl = {https://dblp.org/rec/conf/fdl/HerdtGLD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/Wille0DS18,
author = {Robert Wille and
Bing Li and
Rolf Drechsler and
Ulf Schlichtmann},
editor = {Hiren D. Patel and
Tom J. Kazmierski and
Sebastian Steinhorst},
title = {Automatic Design of Microfluidic Devices},
booktitle = {2018 Forum on Specification {\&} Design Languages, {FDL} 2018,
Garching, Germany, September 10-12, 2018},
pages = {5--16},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/FDL.2018.8524091},
doi = {10.1109/FDL.2018.8524091},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fdl/Wille0DS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/UstaogluHGD18,
author = {Buse Ustaoglu and
Sebastian Huhn and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Deming Chen and
Houman Homayoun and
Baris Taskin},
title = {SAT-Lancer: {A} Hardware SAT-Solver for Self-Verification},
booktitle = {Proceedings of the 2018 on Great Lakes Symposium on VLSI, {GLSVLSI}
2018, Chicago, IL, USA, May 23-25, 2018},
pages = {479--482},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3194554.3194643},
doi = {10.1145/3194554.3194643},
timestamp = {Wed, 10 Mar 2021 14:55:38 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/UstaogluHGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SaeedCZWD0K18,
author = {Samah Mohamed Saeed and
Xiaotong Cui and
Alwin Zulehner and
Robert Wille and
Rolf Drechsler and
Kaijie Wu and
Ramesh Karri},
editor = {Iris Bahar},
title = {{IC/IP} piracy assessment of reversible logic},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {5},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240817},
doi = {10.1145/3240765.3240817},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/SaeedCZWD0K18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MahzoonGD18,
author = {Alireza Mahzoon and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Iris Bahar},
title = {PolyCleaner: clean your polynomials before backward rewriting to verify
million-gate multipliers},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {129},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240837},
doi = {10.1145/3240765.3240837},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/MahzoonGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/SchmidtMROD18,
author = {Robert Schmidt and
Rehab Massoud and
Jaan Raik and
Alberto Garc{\'{\i}}a Ortiz and
Rolf Drechsler},
editor = {Dimitris Gizopoulos and
Dan Alexandrescu and
Mihalis Maniatakos and
Panagiota Papavramidou},
title = {Reliability Improvements for Multiprocessor Systems by Health-Aware
Task Scheduling},
booktitle = {24th {IEEE} International Symposium on On-Line Testing And Robust
System Design, {IOLTS} 2018, Platja D'Aro, Spain, July 2-4, 2018},
pages = {247--250},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/IOLTS.2018.8474101},
doi = {10.1109/IOLTS.2018.8474101},
timestamp = {Thu, 16 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iolts/SchmidtMROD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/Al-WardiWD18,
author = {Zaid Al{-}Wardi and
Robert Wille and
Rolf Drechsler},
title = {Synthesis of Reversible Circuits Using Conventional Hardware Description
Languages},
booktitle = {48th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2018, Linz, Austria, May 16-18, 2018},
pages = {97--102},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISMVL.2018.00025},
doi = {10.1109/ISMVL.2018.00025},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/Al-WardiWD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/ShirinzadehDD18,
author = {Saeideh Shirinzadeh and
Kamalika Datta and
Rolf Drechsler},
title = {Logic Design Using Memristors: An Emerging Technology},
booktitle = {48th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2018, Linz, Austria, May 16-18, 2018},
pages = {121--126},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISMVL.2018.00029},
doi = {10.1109/ISMVL.2018.00029},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/ShirinzadehDD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/BhattacharjeeBW18,
author = {Anirban Bhattacharjee and
Chandan Bandyopadhyay and
Robert Wille and
Rolf Drechsler and
Hafizur Rahaman},
title = {A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits},
booktitle = {2018 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2018,
Hong Kong, China, July 8-11, 2018},
pages = {305--310},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISVLSI.2018.00063},
doi = {10.1109/ISVLSI.2018.00063},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/BhattacharjeeBW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MahzoonGD18,
author = {Alireza Mahzoon and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Combining Symbolic Computer Algebra and Boolean Satisfiability for
Automatic Debugging and Fixing of Complex Multipliers},
booktitle = {2018 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2018,
Hong Kong, China, July 8-11, 2018},
pages = {351--356},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISVLSI.2018.00071},
doi = {10.1109/ISVLSI.2018.00071},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/MahzoonGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ShirinzadehD18,
author = {Saeideh Shirinzadeh and
Rolf Drechsler},
title = {Logic Synthesis for In-memory Computing Using Resistive Memories},
booktitle = {2018 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2018,
Hong Kong, China, July 8-11, 2018},
pages = {375--380},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISVLSI.2018.00075},
doi = {10.1109/ISVLSI.2018.00075},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ShirinzadehD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SchmitzKSGD18,
author = {Kenneth Schmitz and
Oliver Kesz{\"{o}}cze and
Jurij Schmidt and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Towards Dynamic Execution Environment for System Security Protection
Against Hardware Flaws},
booktitle = {2018 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2018,
Hong Kong, China, July 8-11, 2018},
pages = {557--562},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISVLSI.2018.00107},
doi = {10.1109/ISVLSI.2018.00107},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SchmitzKSGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ivsw/DrechslerLFG18,
author = {Rolf Drechsler and
Christoph L{\"{u}}th and
G{\"{o}}rschwin Fey and
Tim G{\"{u}}neysu},
title = {Towards Self-Explaining Digital Systems: {A} Design Methodology for
the Next Generation},
booktitle = {3rd {IEEE} International Verification and Security Workshop, {IVSW}
2018, Costa Brava, Spain, July 2-4, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/IVSW.2018.8494900},
doi = {10.1109/IVSW.2018.8494900},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ivsw/DrechslerLFG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ivsw/Drechsler18,
author = {Rolf Drechsler},
title = {Keynotes: Towards Self-Explaining Digital Systems: {A} Design Methodology
for the Next Generation},
booktitle = {3rd {IEEE} International Verification and Security Workshop, {IVSW}
2018, Costa Brava, Spain, July 2-4, 2018},
pages = {i--iii},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/IVSW.2018.8494895},
doi = {10.1109/IVSW.2018.8494895},
timestamp = {Wed, 24 Oct 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ivsw/Drechsler18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ldic/StoppePHD18,
author = {Jannis Stoppe and
Christina Plump and
Sebastian Huhn and
Rolf Drechsler},
editor = {Michael Freitag and
Herbert Kotzab and
J{\"{u}}rgen Pannek},
title = {Building Fast Multi Agent Systems Using Hardware Design Languages
for High-Throughput Systems},
booktitle = {Dynamics in Logistics, Proceedings of the 6th International Conference
{LDIC} 2018, Bremen, Germany, February 20-22, 2018},
series = {Lecture Notes in Logistics},
pages = {400--405},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-74225-0\_54},
doi = {10.1007/978-3-319-74225-0\_54},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ldic/StoppePHD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/HerdtLGD18,
author = {Vladimir Herdt and
Hoang M. Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Towards Automated Refinement of {TLM} Properties to {RTL}},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen, {MBMV} 2018, T{\"{u}}bingen, Germany,
February 8-9, 2018},
publisher = {Universit{\"{a}}t T{\"{u}}bingen},
year = {2018},
url = {https://hdl.handle.net/10900/84283},
timestamp = {Wed, 04 May 2022 13:03:25 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/HerdtLGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/modelsward/NiemannPWD18,
author = {Philipp Niemann and
Nils Przigoda and
Robert Wille and
Rolf Drechsler},
editor = {Slimane Hammoudi and
Lu{\'{\i}}s Ferreira Pires and
Bran Selic},
title = {Analyzing Frame Conditions in {UML/OCL} Models - Consistency Equivalence
and Independence},
booktitle = {Proceedings of the 6th International Conference on Model-Driven Engineering
and Software Development, {MODELSWARD} 2018, Funchal, Madeira - Portugal,
January 22-24, 2018},
pages = {139--151},
publisher = {SciTePress},
year = {2018},
url = {https://doi.org/10.5220/0006602301390151},
doi = {10.5220/0006602301390151},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/modelsward/NiemannPWD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/modelsward/NiemannPWD18a,
author = {Philipp Niemann and
Nils Przigoda and
Robert Wille and
Rolf Drechsler},
editor = {Slimane Hammoudi and
Lu{\'{\i}}s Ferreira Pires and
Bran Selic},
title = {Generation and Validation of Frame Conditions in Formal Models},
booktitle = {Model-Driven Engineering and Software Development - 6th International
Conference, {MODELSWARD} 2018, Funchal, Madeira, Portugal, January
22-24, 2018, Revised Selected Papers},
series = {Communications in Computer and Information Science},
volume = {991},
pages = {259--283},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-11030-7\_12},
doi = {10.1007/978-3-030-11030-7\_12},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/modelsward/NiemannPWD18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/norchip/LemmaGGD18,
author = {David Lemma and
Mehran Goli and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Jari Nurmi and
Peeter Ellervee and
Juri Mihhailov and
Maksim Jenihhin and
Kalle Tammem{\"{a}}e},
title = {Power Intent from Initial {ESL} Prototypes: Extracting Power Management
Parameters\({}^{\mbox{*}}\)},
booktitle = {2018 {IEEE} Nordic Circuits and Systems Conference, {NORCAS} 2018:
{NORCHIP} and International Symposium of System-on-Chip (SoC), Tallinn,
Estonia, October 30-31, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/NORCHIP.2018.8573511},
doi = {10.1109/NORCHIP.2018.8573511},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/norchip/LemmaGGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/Sarvaghad-Moghaddam18,
author = {Moein Sarvaghad{-}Moghaddam and
Philipp Niemann and
Rolf Drechsler},
editor = {Jarkko Kari and
Irek Ulidowski},
title = {Multi-objective Synthesis of Quantum Circuits Using Genetic Programming},
booktitle = {Reversible Computation - 10th International Conference, {RC} 2018,
Leicester, UK, September 12-14, 2018, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {11106},
pages = {220--227},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-99498-7\_15},
doi = {10.1007/978-3-319-99498-7\_15},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rc/Sarvaghad-Moghaddam18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/GoliSD18,
author = {Mehran Goli and
Jannis Stoppe and
Rolf Drechsler},
title = {Resilience Evaluation for Approximating SystemC Designs Using Machine
Learning Techniques},
booktitle = {2018 International Symposium on Rapid System Prototyping, {RSP} 2018,
Torino, Italy, October 4-5, 2018},
pages = {97--103},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/RSP.2018.8631997},
doi = {10.1109/RSP.2018.8631997},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rsp/GoliSD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KeszoczeIWCD18,
author = {Oliver Kesz{\"{o}}cze and
Mohamed Ibrahim and
Robert Wille and
Krishnendu Chakrabarty and
Rolf Drechsler},
title = {Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways
on Digital Microfluidic Biochips},
booktitle = {31st International Conference on {VLSI} Design and 17th International
Conference on Embedded Systems, {VLSID} 2018, Pune, India, January
6-10, 2018},
pages = {121--126},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/VLSID.2018.48},
doi = {10.1109/VLSID.2018.48},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/KeszoczeIWCD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/18/WilleCDK18,
author = {Robert Wille and
Krishnendu Chakrabarty and
Rolf Drechsler and
Priyank Kalla},
editor = {Andr{\'{e}} In{\'{a}}cio Reis and
Rolf Drechsler},
title = {Emerging Circuit Technologies: An Overview on the Next Generation
of Circuits},
booktitle = {Advanced Logic Synthesis},
pages = {43--67},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-67295-3\_3},
doi = {10.1007/978-3-319-67295-3\_3},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/sp/18/WilleCDK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/sp/18/RD2018,
editor = {Andr{\'{e}} In{\'{a}}cio Reis and
Rolf Drechsler},
title = {Advanced Logic Synthesis},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-67295-3},
doi = {10.1007/978-3-319-67295-3},
isbn = {978-3-319-67294-6},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/sp/18/RD2018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1811-03894,
author = {Frank Sill Torres and
Philipp Niemann and
Robert Wille and
Rolf Drechsler},
title = {Breaking Landauer's Limit{\textbackslash}{\textbackslash}Using Quantum-dot
Cellular Automata},
journal = {CoRR},
volume = {abs/1811.03894},
year = {2018},
url = {http://arxiv.org/abs/1811.03894},
eprinttype = {arXiv},
eprint = {1811.03894},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1811-03894.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/SoekenGSDM17,
author = {Mathias Soeken and
Pierre{-}Emmanuel Gaillardon and
Saeideh Shirinzadeh and
Rolf Drechsler and
Giovanni De Micheli},
title = {A PLiM Computer for the Internet of Things},
journal = {Computer},
volume = {50},
number = {6},
pages = {35--40},
year = {2017},
url = {https://doi.org/10.1109/MC.2017.173},
doi = {10.1109/MC.2017.173},
timestamp = {Wed, 12 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/SoekenGSDM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DebWKSD17,
author = {Arighna Deb and
Robert Wille and
Oliver Kesz{\"{o}}cze and
Saeideh Shirinzadeh and
Rolf Drechsler},
title = {Synthesis of optical circuits using binary decision diagrams},
journal = {Integr.},
volume = {59},
pages = {42--51},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.05.001},
doi = {10.1016/J.VLSI.2017.05.001},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DebWKSD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/WilleKOTD17,
author = {Robert Wille and
Oliver Kesz{\"{o}}cze and
Lars Othmer and
Michael Kirkedal Thomsen and
Rolf Drechsler},
title = {An Automated Approach for Generating and Checking Control Logic for
Reversible Hardware Description Language-Based Designs},
journal = {J. Low Power Electron.},
volume = {13},
number = {4},
pages = {633--641},
year = {2017},
url = {https://doi.org/10.1166/jolpe.2017.1515},
doi = {10.1166/JOLPE.2017.1515},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jolpe/WilleKOTD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sttt/RienerHFSGDF17,
author = {Heinz Riener and
Finn Haedicke and
Stefan Frehse and
Mathias Soeken and
Daniel Gro{\ss}e and
Rolf Drechsler and
G{\"{o}}rschwin Fey},
title = {metaSMT: focus on your application and not on solver integration},
journal = {Int. J. Softw. Tools Technol. Transf.},
volume = {19},
number = {5},
pages = {605--621},
year = {2017},
url = {https://doi.org/10.1007/s10009-016-0426-1},
doi = {10.1007/S10009-016-0426-1},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sttt/RienerHFSGDF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AledoPWDS17,
author = {Pablo Gonz{\'{a}}lez de Aledo and
Nils Przigoda and
Robert Wille and
Rolf Drechsler and
Pablo S{\'{a}}nchez Espeso},
title = {Towards a Verification Flow Across Abstraction Levels Verifying Implementations
Against Their Formal Specification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {3},
pages = {475--488},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2016.2611494},
doi = {10.1109/TCAD.2016.2611494},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AledoPWDS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SchmitzCFGD17,
author = {Kenneth Schmitz and
Arun Chandrasekharan and
Jonas Gomes Filho and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Trust is good, control is better: Hardware-based instruction-replacement
for reliable processor-IPs},
booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2017, Chiba, Japan, January 16-19, 2017},
pages = {57--62},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASPDAC.2017.7858296},
doi = {10.1109/ASPDAC.2017.7858296},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/SchmitzCFGD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HuhnFWD17,
author = {Sebastian Huhn and
Stefan Frehse and
Robert Wille and
Rolf Drechsler},
title = {Enhancing robustness of sequential circuits using application-specific
knowledge and formal methods},
booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2017, Chiba, Japan, January 16-19, 2017},
pages = {182--187},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASPDAC.2017.7858317},
doi = {10.1109/ASPDAC.2017.7858317},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/HuhnFWD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KeszoczeLGWCD17,
author = {Oliver Kesz{\"{o}}cze and
Zipeng Li and
Andreas Grimmer and
Robert Wille and
Krishnendu Chakrabarty and
Rolf Drechsler},
title = {Exact routing for micro-electrode-dot-array digital microfluidic biochips},
booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2017, Chiba, Japan, January 16-19, 2017},
pages = {708--713},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASPDAC.2017.7858407},
doi = {10.1109/ASPDAC.2017.7858407},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/KeszoczeLGWCD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/DhotreED17,
author = {Harshad Dhotre and
Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {Identification of Efficient Clustering Techniques for Test Power Activity
on the Layout},
booktitle = {26th {IEEE} Asian Test Symposium, {ATS} 2017, Taipei City, Taiwan,
November 27-30, 2017},
pages = {108--113},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ATS.2017.31},
doi = {10.1109/ATS.2017.31},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/DhotreED17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HassanHLCGD17,
author = {Muhammad Hassan and
Vladimir Herdt and
Hoang M. Le and
Mingsong Chen and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {David Atienza and
Giorgio Di Natale},
title = {Data flow testing for virtual prototypes},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {380--385},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927020},
doi = {10.23919/DATE.2017.7927020},
timestamp = {Wed, 09 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/HassanHLCGD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HuhnECD17,
author = {Sebastian Huhn and
Stephan Eggersgl{\"{u}}{\ss} and
Krishnendu Chakrabarty and
Rolf Drechsler},
editor = {David Atienza and
Giorgio Di Natale},
title = {Optimization of retargeting for {IEEE} 1149.1 {TAP} controllers with
embedded compression},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {578--583},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927053},
doi = {10.23919/DATE.2017.7927053},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/HuhnECD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GoliSD17,
author = {Mehran Goli and
Jannis Stoppe and
Rolf Drechsler},
editor = {David Atienza and
Giorgio Di Natale},
title = {Automatic equivalence checking for SystemC-TLM 2.0 models against
their formal specifications},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {630--633},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927064},
doi = {10.23919/DATE.2017.7927064},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/GoliSD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ShirinzadehSGMD17,
author = {Saeideh Shirinzadeh and
Mathias Soeken and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Rolf Drechsler},
editor = {David Atienza and
Giorgio Di Natale},
title = {Endurance management for resistive Logic-In-Memory computing architectures},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {1092--1097},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927152},
doi = {10.23919/DATE.2017.7927152},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/ShirinzadehSGMD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SchneiderKSD17,
author = {Leonard Schneider and
Oliver Kesz{\"{o}}cze and
Jannis Stoppe and
Rolf Drechsler},
editor = {David Atienza and
Giorgio Di Natale},
title = {Effects of cell shapes on the routability of Digital Microfluidic
Biochips},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {1627--1630},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927252},
doi = {10.23919/DATE.2017.7927252},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/SchneiderKSD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/DhotreEDPD17,
author = {Harshad Dhotre and
Stephan Eggersgl{\"{u}}{\ss} and
Mehdi Dehbashi and
Ulrike Pfannkuchen and
Rolf Drechsler},
title = {Machine learning based test pattern analysis for localizing critical
power activity areas},
booktitle = {{IEEE} International Symposium on Defect and Fault Tolerance in {VLSI}
and Nanotechnology Systems, {DFT} 2017, Cambridge, United Kingdom,
October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/DFT.2017.8244464},
doi = {10.1109/DFT.2017.8244464},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/DhotreEDPD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/HuhnED17,
author = {Sebastian Huhn and
Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {Reconfigurable {TAP} controllers with embedded compression for large
test data volume},
booktitle = {{IEEE} International Symposium on Defect and Fault Tolerance in {VLSI}
and Nanotechnology Systems, {DFT} 2017, Cambridge, United Kingdom,
October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/DFT.2017.8244462},
doi = {10.1109/DFT.2017.8244462},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/HuhnED17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/TorresLD17,
author = {Frank Sill Torres and
Pedro Fausto Rodrigues Leite and
Rolf Drechsler},
title = {Unintrusive aging analysis based on offline learning},
booktitle = {{IEEE} International Symposium on Defect and Fault Tolerance in {VLSI}
and Nanotechnology Systems, {DFT} 2017, Cambridge, United Kingdom,
October 23-25, 2017},
pages = {1--4},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/DFT.2017.8244453},
doi = {10.1109/DFT.2017.8244453},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/TorresLD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/MichaelDESHA17,
author = {Maria K. Michael and
Rolf Drechsler and
Stephan Eggersgl{\"{u}}{\ss} and
Haralampos{-}G. D. Stratigopoulos and
Sybille Hellebrand and
Rob Aitken},
title = {Foreword},
booktitle = {22nd {IEEE} European Test Symposium, {ETS} 2017, Limassol, Cyprus,
May 22-26, 2017},
pages = {1--2},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ETS.2017.7968204},
doi = {10.1109/ETS.2017.7968204},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/ets/MichaelDESHA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/HerdtLGD17,
author = {Vladimir Herdt and
Hoang M. Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Franco Fummi and
Hiren D. Patel and
Samarjit Chakraborty},
title = {Towards early validation of firmware-based power management using
virtual prototypes: {A} constrained random approach},
booktitle = {2017 Forum on Specification and Design Languages, {FDL} 2017, Verona,
Italy, September 18-20, 2017},
pages = {1--8},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/FDL.2017.8303898},
doi = {10.1109/FDL.2017.8303898},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/fdl/HerdtLGD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/HerdtLGD17a,
author = {Vladimir Herdt and
Hoang M. Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Daniel Gro{\ss}e and
Sara Vinco and
Hiren D. Patel},
title = {Towards Early Validation of Firmware-Based Power Management Using
Virtual Prototypes: {A} Constrained Random Approach},
booktitle = {Languages, Design Methods, and Tools for Electronic System Design
- Selected Contributions from {FDL} 2017 [Verona, Italy, September
18-20, 2017]},
series = {Lecture Notes in Electrical Engineering},
volume = {530},
pages = {25--44},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-030-02215-0\_2},
doi = {10.1007/978-3-030-02215-0\_2},
timestamp = {Tue, 29 Nov 2022 08:38:47 +0100},
biburl = {https://dblp.org/rec/conf/fdl/HerdtLGD17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/formats/MassoudSGD17,
author = {Rehab Massoud and
Jannis Stoppe and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Alessandro Abate and
Gilles Geeraerts},
title = {Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction},
booktitle = {Formal Modeling and Analysis of Timed Systems - 15th International
Conference, {FORMATS} 2017, Berlin, Germany, September 5-7, 2017,
Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10419},
pages = {335--351},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-65765-3\_19},
doi = {10.1007/978-3-319-65765-3\_19},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/formats/MassoudSGD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/ShirinzadehSGD17,
author = {Saeideh Shirinzadeh and
Mathias Soeken and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Peter A. N. Bosman},
title = {An adaptive prioritized \emph{{\(\epsilon\)}}-preferred evolutionary
algorithm for approximate {BDD} optimization},
booktitle = {Proceedings of the Genetic and Evolutionary Computation Conference,
{GECCO} 2017, Berlin, Germany, July 15-19, 2017},
pages = {1232--1239},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3071178.3071281},
doi = {10.1145/3071178.3071281},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/gecco/ShirinzadehSGD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Chandrasekharan17,
author = {Arun Chandrasekharan and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Laleh Behjat and
Jie Han and
Miroslav N. Velev and
Deming Chen},
title = {ProACt: {A} Processor for High Performance On-demand Approximate Computing},
booktitle = {Proceedings of the on Great Lakes Symposium on {VLSI} 2017, Banff,
AB, Canada, May 10-12, 2017},
pages = {463--466},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3060403.3060415},
doi = {10.1145/3060403.3060415},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/Chandrasekharan17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/DebWD17,
author = {Arighna Deb and
Robert Wille and
Rolf Drechsler},
editor = {Sri Parameswaran},
title = {Dedicated synthesis for MZI-based optical circuits based on AND-inverter
graphs},
booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
pages = {233--238},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICCAD.2017.8203783},
doi = {10.1109/ICCAD.2017.8203783},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/DebWD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HassanHLGD17,
author = {Muhammad Hassan and
Vladimir Herdt and
Hoang M. Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Sri Parameswaran},
title = {Early SoC security validation by VP-based static information flow
analysis},
booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
pages = {400--407},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICCAD.2017.8203805},
doi = {10.1109/ICCAD.2017.8203805},
timestamp = {Wed, 09 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/HassanHLGD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/GoliSD17,
author = {Mehran Goli and
Jannis Stoppe and
Rolf Drechsler},
title = {Automatic Protocol Compliance Checking of SystemC {TLM-2.0} Simulation
Behavior Using Timed Automata},
booktitle = {2017 {IEEE} International Conference on Computer Design, {ICCD} 2017,
Boston, MA, USA, November 5-8, 2017},
pages = {377--384},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ICCD.2017.65},
doi = {10.1109/ICCD.2017.65},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccd/GoliSD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/BornebuschWD17,
author = {Fritjof Bornebusch and
Robert Wille and
Rolf Drechsler},
title = {Towards lightweight satisfiability solvers for self-verification},
booktitle = {7th International Symposium on Embedded Computing and System Design,
{ISED} 2017, Durgapur, India, December 18-20, 2017},
pages = {1--5},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISED.2017.8303924},
doi = {10.1109/ISED.2017.8303924},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/ised/BornebuschWD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/KoleRD0D17,
author = {Abhoy Kole and
P. Mercy Nesa Rani and
Kamalika Datta and
Indranil Sengupta and
Rolf Drechsler},
title = {Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli
Gates},
booktitle = {47th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2017, Novi Sad, Serbia, May 22-24, 2017},
pages = {179--184},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISMVL.2017.51},
doi = {10.1109/ISMVL.2017.51},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/KoleRD0D17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/Al-WardiWD17,
author = {Zaid Al{-}Wardi and
Robert Wille and
Rolf Drechsler},
title = {Extensions to the Reversible Hardware Description Language SyReC},
booktitle = {47th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2017, Novi Sad, Serbia, May 22-24, 2017},
pages = {185--190},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISMVL.2017.41},
doi = {10.1109/ISMVL.2017.41},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/Al-WardiWD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/FroehlichGD17,
author = {Saman Fr{\"{o}}hlich and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Error Bounded Exact {BDD} Minimization in Approximate Computing},
booktitle = {47th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2017, Novi Sad, Serbia, May 22-24, 2017},
pages = {254--259},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISMVL.2017.11},
doi = {10.1109/ISMVL.2017.11},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/FroehlichGD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/DebWD17,
author = {Arighna Deb and
Robert Wille and
Rolf Drechsler},
title = {OR-Inverter Graphs for the Synthesis of Optical Circuits},
booktitle = {47th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2017, Novi Sad, Serbia, May 22-24, 2017},
pages = {278--283},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISMVL.2017.31},
doi = {10.1109/ISMVL.2017.31},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/DebWD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/StoppeKLWD17,
author = {Jannis Stoppe and
Oliver Kesz{\"{o}}cze and
Maximilian Luenert and
Robert Wille and
Rolf Drechsler},
title = {BioViz: An Interactive Visualization Engine for the Design of Digital
Microfluidic Biochips},
booktitle = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
Bochum, Germany, July 3-5, 2017},
pages = {170--175},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISVLSI.2017.38},
doi = {10.1109/ISVLSI.2017.38},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/StoppeKLWD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/FrohlichGD17,
author = {Saman Fr{\"{o}}hlich and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Exakte {BDD} Minimierung mit Fehlerschranke f{\"{u}}r den Einsatz
im Approximate Computing},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen, {MBMV} 2017, Bremen, Germany, February
8-9, 2017},
pages = {27--38},
publisher = {Shaker Verlag},
year = {2017},
timestamp = {Mon, 20 Nov 2017 10:25:21 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/FrohlichGD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/SchneiderKSD17,
author = {Leonard Schneider and
Oliver Kesz{\"{o}}cze and
Jannis Stoppe and
Rolf Drechsler},
editor = {Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen, {MBMV} 2017, Bremen, Germany, February
8-9, 2017},
pages = {75--78},
publisher = {Shaker Verlag},
year = {2017},
timestamp = {Mon, 20 Nov 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/SchneiderKSD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/PrzigodaNPHWD17,
author = {Nils Przigoda and
Philipp Niemann and
Judith Peters and
Frank Hilken and
Robert Wille and
Rolf Drechsler},
editor = {Jean{-}Pierre Talpin and
Patricia Derler and
Klaus Schneider},
title = {More than true or false: native support of irregular values in the
automatic validation {\&} verification of {UML/OCL} models},
booktitle = {Proceedings of the 15th {ACM-IEEE} International Conference on Formal
Methods and Models for System Design, {MEMOCODE} 2017, Vienna, Austria,
September 29 - October 02, 2017},
pages = {77--86},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3127041.3127053},
doi = {10.1145/3127041.3127053},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/memocode/PrzigodaNPHWD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/Chandrasekharan17,
author = {Arun Chandrasekharan and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Jean{-}Pierre Talpin and
Patricia Derler and
Klaus Schneider},
title = {Yise - a novel framework for boolean networks using y-inverter graphs},
booktitle = {Proceedings of the 15th {ACM-IEEE} International Conference on Formal
Methods and Models for System Design, {MEMOCODE} 2017, Vienna, Austria,
September 29 - October 02, 2017},
pages = {114--117},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3127041.3127065},
doi = {10.1145/3127041.3127065},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/memocode/Chandrasekharan17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/Al-WardiWD17,
author = {Zaid Al{-}Wardi and
Robert Wille and
Rolf Drechsler},
editor = {Iain Phillips and
Hafizur Rahaman},
title = {Towards VHDL-Based Design of Reversible Circuits - Work in Progress
Report},
booktitle = {Reversible Computation - 9th International Conference, {RC} 2017,
Kolkata, India, July 6-7, 2017, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10301},
pages = {102--108},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-59936-6\_8},
doi = {10.1007/978-3-319-59936-6\_8},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rc/Al-WardiWD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/NiemannZWD17,
author = {Philipp Niemann and
Alwin Zulehner and
Robert Wille and
Rolf Drechsler},
editor = {Iain Phillips and
Hafizur Rahaman},
title = {Efficient Construction of QMDDs for Irreversible, Reversible, and
Quantum Functions},
booktitle = {Reversible Computation - 9th International Conference, {RC} 2017,
Kolkata, India, July 6-7, 2017, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10301},
pages = {214--231},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-59936-6\_17},
doi = {10.1007/978-3-319-59936-6\_17},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rc/NiemannZWD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ssci/HuhnSECD17,
author = {Sebastian Huhn and
Heike Sonnenberg and
Stephan Eggersgl{\"{u}}{\ss} and
Brigitte Clausen and
Rolf Drechsler},
title = {Revealing properties of structural materials by combining regression-based
algorithms and nano indentation measurements},
booktitle = {2017 {IEEE} Symposium Series on Computational Intelligence, {SSCI}
2017, Honolulu, HI, USA, November 27 - Dec. 1, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/SSCI.2017.8285180},
doi = {10.1109/SSCI.2017.8285180},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ssci/HuhnSECD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mbmv/2017,
editor = {Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen, {MBMV} 2017, Bremen, Germany, February
8-9, 2017},
publisher = {Shaker Verlag},
year = {2017},
isbn = {978-3-8440-4996-1},
timestamp = {Mon, 20 Nov 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/2017.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/SaeedCWZ0DK17,
author = {Samah Mohamed Saeed and
Xiaotong Cui and
Robert Wille and
Alwin Zulehner and
Kaijie Wu and
Rolf Drechsler and
Ramesh Karri},
title = {Towards Reverse Engineering Reversible Logic},
journal = {CoRR},
volume = {abs/1704.08397},
year = {2017},
url = {http://arxiv.org/abs/1704.08397},
eprinttype = {arXiv},
eprint = {1704.08397},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/SaeedCWZ0DK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/CuiSZWD0K17,
author = {Xiaotong Cui and
Samah Mohamed Saeed and
Alwin Zulehner and
Robert Wille and
Rolf Drechsler and
Kaijie Wu and
Ramesh Karri},
title = {On the Difficulty of Inserting Trojans in Reversible Computing Architectures},
journal = {CoRR},
volume = {abs/1705.00767},
year = {2017},
url = {http://arxiv.org/abs/1705.00767},
eprinttype = {arXiv},
eprint = {1705.00767},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/CuiSZWD0K17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cps/PrzigodaSWD16,
author = {Nils Przigoda and
Mathias Soeken and
Robert Wille and
Rolf Drechsler},
title = {Verifying the structure and behavior in {UML/OCL} models using satisfiability
solvers},
journal = {{IET} Cyper-Phys. Syst.: Theory {\&} Appl.},
volume = {1},
number = {1},
pages = {49--59},
year = {2016},
url = {https://doi.org/10.1049/iet-cps.2016.0022},
doi = {10.1049/IET-CPS.2016.0022},
timestamp = {Wed, 22 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cps/PrzigodaSWD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WilleSSD16,
author = {Robert Wille and
Eleonora Sch{\"{o}}nborn and
Mathias Soeken and
Rolf Drechsler},
title = {SyReC: {A} hardware description language for the specification and
synthesis of reversible circuits},
journal = {Integr.},
volume = {53},
pages = {39--53},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.10.001},
doi = {10.1016/J.VLSI.2015.10.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WilleSSD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/PrzigodaWD16,
author = {Nils Przigoda and
Robert Wille and
Rolf Drechsler},
title = {Analyzing Inconsistencies in {UML/OCL} Models},
journal = {J. Circuits Syst. Comput.},
volume = {25},
number = {3},
pages = {1640021:1--1640021:21},
year = {2016},
url = {https://doi.org/10.1142/S0218126616400211},
doi = {10.1142/S0218126616400211},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/PrzigodaWD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/DebDRWDB16,
author = {Arighna Deb and
Debesh K. Das and
Hafizur Rahaman and
Robert Wille and
Rolf Drechsler and
Bhargab B. Bhattacharya},
title = {Reversible Synthesis of Symmetric Functions with a Simple Regular
Structure and Easy Testability},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {12},
number = {4},
pages = {34:1--34:29},
year = {2016},
url = {https://doi.org/10.1145/2894757},
doi = {10.1145/2894757},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/DebDRWDB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/SoekenWKMD16,
author = {Mathias Soeken and
Robert Wille and
Oliver Kesz{\"{o}}cze and
D. Michael Miller and
Rolf Drechsler},
title = {Embedding of Large Boolean Functions for Reversible Logic},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {12},
number = {4},
pages = {41:1--41:26},
year = {2016},
url = {https://doi.org/10.1145/2786982},
doi = {10.1145/2786982},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jetc/SoekenWKMD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/DebWKHD16,
author = {Arighna Deb and
Robert Wille and
Oliver Kesz{\"{o}}cze and
Stefan Hillmich and
Rolf Drechsler},
title = {Gates vs. Splitters: Contradictory Optimization Objectives in the
Synthesis of Optical Circuits},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {13},
number = {1},
pages = {11:1--11:13},
year = {2016},
url = {https://doi.org/10.1145/2904445},
doi = {10.1145/2904445},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/DebWKHD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsc/SoekenTDD16,
author = {Mathias Soeken and
Laura Tague and
Gerhard W. Dueck and
Rolf Drechsler},
title = {Ancilla-free synthesis of large reversible functions using binary
decision diagrams},
journal = {J. Symb. Comput.},
volume = {73},
pages = {1--26},
year = {2016},
url = {https://doi.org/10.1016/j.jsc.2015.03.002},
doi = {10.1016/J.JSC.2015.03.002},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsc/SoekenTDD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NiemannWMTD16,
author = {Philipp Niemann and
Robert Wille and
D. Michael Miller and
Mitchell A. Thornton and
Rolf Drechsler},
title = {QMDDs: Efficient Quantum Function Representation and Manipulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {1},
pages = {86--99},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2015.2459034},
doi = {10.1109/TCAD.2015.2459034},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/NiemannWMTD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EggersgluBSKD16,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Kenneth Schmitz and
Rene Krenz{-}Baath and
Rolf Drechsler},
title = {On Optimization-Based {ATPG} and Its Application for Highly Compacted
Test Sets},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {12},
pages = {2104--2117},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2016.2552822},
doi = {10.1109/TCAD.2016.2552822},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EggersgluBSKD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcs/AbdessaiedADS16,
author = {Nabila Abdessaied and
Matthew Amy and
Rolf Drechsler and
Mathias Soeken},
title = {Complexity of reversible circuits and their quantum implementations},
journal = {Theor. Comput. Sci.},
volume = {618},
pages = {85--106},
year = {2016},
url = {https://doi.org/10.1016/j.tcs.2016.01.011},
doi = {10.1016/J.TCS.2016.01.011},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcs/AbdessaiedADS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WilleKWRCD16,
author = {Robert Wille and
Oliver Kesz{\"{o}}cze and
Marcel Walter and
Patrick Rohrs and
Anupam Chattopadhyay and
Rolf Drechsler},
title = {Look-ahead schemes for nearest neighbor optimization of 1D and 2D
quantum circuits},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {292--297},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7428026},
doi = {10.1109/ASPDAC.2016.7428026},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WilleKWRCD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SoekenGCD16,
author = {Mathias Soeken and
Daniel Gro{\ss}e and
Arun Chandrasekharan and
Rolf Drechsler},
title = {{BDD} minimization for approximate computing},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {474--479},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7428057},
doi = {10.1109/ASPDAC.2016.7428057},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/SoekenGCD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cav/HerdtLGD16,
author = {Vladimir Herdt and
Hoang Minh Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Swarat Chaudhuri and
Azadeh Farzan},
title = {ParCoSS: Efficient Parallelized Compiled Symbolic Simulation},
booktitle = {Computer Aided Verification - 28th International Conference, {CAV}
2016, Toronto, ON, Canada, July 17-23, 2016, Proceedings, Part {II}},
series = {Lecture Notes in Computer Science},
volume = {9780},
pages = {177--183},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-41540-6\_10},
doi = {10.1007/978-3-319-41540-6\_10},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cav/HerdtLGD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SoekenSGADM16,
author = {Mathias Soeken and
Saeideh Shirinzadeh and
Pierre{-}Emmanuel Gaillardon and
Luca Gaetano Amar{\`{u}} and
Rolf Drechsler and
Giovanni De Micheli},
title = {An MIG-based compiler for programmable logic-in-memory architectures},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {117:1--117:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2897985},
doi = {10.1145/2897937.2897985},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/SoekenSGADM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Chandrasekharan16,
author = {Arun Chandrasekharan and
Mathias Soeken and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Precise error determination of approximated components in sequential
circuits with model checking},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {129:1--129:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2898069},
doi = {10.1145/2897937.2898069},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/Chandrasekharan16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GuZCGD16,
author = {Fan Gu and
Xinqian Zhang and
Mingsong Chen and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {Quantitative timing analysis of {UML} activity diagrams using statistical
model checking},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {780--785},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459412/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/GuZCGD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ShirinzadehSGD16,
author = {Saeideh Shirinzadeh and
Mathias Soeken and
Pierre{-}Emmanuel Gaillardon and
Rolf Drechsler},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter
Graphs},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {948--953},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459444/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/ShirinzadehSGD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/Sayed-AhmedGKSD16,
author = {Amr A. R. Sayed{-}Ahmed and
Daniel Gro{\ss}e and
Ulrich K{\"{u}}hne and
Mathias Soeken and
Rolf Drechsler},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {Formal verification of integer multipliers by combining Gr{\"{o}}bner
basis with logic reduction},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {1048--1053},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459464/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/Sayed-AhmedGKSD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LeHGD16,
author = {Hoang Minh Le and
Vladimir Herdt and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {Towards formal verification of real-world SystemC {TLM} peripheral
models - a case study},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {1160--1163},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459486/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/LeHGD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/ShirinzadehSD16,
author = {Saeideh Shirinzadeh and
Mathias Soeken and
Rolf Drechsler},
title = {Multi-objective {BDD} optimization for {RRAM} based circuit design},
booktitle = {2016 {IEEE} 19th International Symposium on Design and Diagnostics
of Electronic Circuits {\&} Systems (DDECS), Kosice, Slovakia,
April 20-22, 2016},
pages = {46--51},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DDECS.2016.7482461},
doi = {10.1109/DDECS.2016.7482461},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/ddecs/ShirinzadehSD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/HuhnED16,
author = {Sebastian Huhn and
Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {VecTHOR: Low-cost compression architecture for {IEEE} 1149-compliant
{TAP} controllers},
booktitle = {21th {IEEE} European Test Symposium, {ETS} 2016, Amsterdam, Netherlands,
May 23-27, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ETS.2016.7519303},
doi = {10.1109/ETS.2016.7519303},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/ets/HuhnED16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/HerdtLGD16,
author = {Vladimir Herdt and
Hoang M. Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Rolf Drechsler and
Robert Wille},
title = {On the application of formal fault localization to automated RTL-to-TLM
fault correspondence analysis for fast and accurate VP-based error
effect simulation - a case study},
booktitle = {2016 Forum on Specification and Design Languages, {FDL} 2016, Bremen,
Germany, September 14-16, 2016},
pages = {1--8},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FDL.2016.7880375},
doi = {10.1109/FDL.2016.7880375},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/fdl/HerdtLGD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/RingSLD16,
author = {Martin Ring and
Jannis Stoppe and
Christoph L{\"{u}}th and
Rolf Drechsler},
editor = {Rolf Drechsler and
Robert Wille},
title = {Change impact analysis for hardware designs from natural language
to system level},
booktitle = {2016 Forum on Specification and Design Languages, {FDL} 2016, Bremen,
Germany, September 14-16, 2016},
pages = {1--7},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FDL.2016.7880369},
doi = {10.1109/FDL.2016.7880369},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/RingSLD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/Sayed-AhmedGSD16,
author = {Amr A. R. Sayed{-}Ahmed and
Daniel Gro{\ss}e and
Mathias Soeken and
Rolf Drechsler},
editor = {Ruzica Piskac and
Muralidhar Talupur},
title = {Equivalence checking using Gr{\"{o}}bner bases},
booktitle = {2016 Formal Methods in Computer-Aided Design, {FMCAD} 2016, Mountain
View, CA, USA, October 3-6, 2016},
pages = {169--176},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FMCAD.2016.7886676},
doi = {10.1109/FMCAD.2016.7886676},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/fmcad/Sayed-AhmedGSD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/ShirinzadehSGD16,
author = {Saeideh Shirinzadeh and
Mathias Soeken and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Tobias Friedrich and
Frank Neumann and
Andrew M. Sutton},
title = {Approximate {BDD} Optimization with Prioritized {\(\epsilon\)}-Preferred
Evolutionary Algorithm},
booktitle = {Genetic and Evolutionary Computation Conference, {GECCO} 2016, Denver,
CO, USA, July 20-24, 2016, Companion Material Proceedings},
pages = {79--80},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2908961.2908987},
doi = {10.1145/2908961.2908987},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/gecco/ShirinzadehSGD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HerdtLGD16,
author = {Vladimir Herdt and
Hoang M. Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Frank Liu},
title = {Compiled symbolic simulation for systemC},
booktitle = {Proceedings of the 35th International Conference on Computer-Aided
Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016},
pages = {52},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2966986.2967016},
doi = {10.1145/2966986.2967016},
timestamp = {Fri, 23 Jun 2023 22:29:48 +0200},
biburl = {https://dblp.org/rec/conf/iccad/HerdtLGD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/Chandrasekharan16,
author = {Arun Chandrasekharan and
Mathias Soeken and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Frank Liu},
title = {Approximation-aware rewriting of AIGs for error tolerant applications},
booktitle = {Proceedings of the 35th International Conference on Computer-Aided
Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016},
pages = {83},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2966986.2967003},
doi = {10.1145/2966986.2967003},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/Chandrasekharan16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WilleLSD16,
author = {Robert Wille and
Bing Li and
Ulf Schlichtmann and
Rolf Drechsler},
editor = {Frank Liu},
title = {From biochips to quantum circuits: computer-aided design for emerging
technologies},
booktitle = {Proceedings of the 35th International Conference on Computer-Aided
Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016},
pages = {132},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2966986.2980099},
doi = {10.1145/2966986.2980099},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/WilleLSD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/GoliSD16,
author = {Mehran Goli and
Jannis Stoppe and
Rolf Drechsler},
title = {{AIBA:} An Automated Intra-cycle Behavioral Analysis for SystemC-based
design exploration},
booktitle = {34th {IEEE} International Conference on Computer Design, {ICCD} 2016,
Scottsdale, AZ, USA, October 2-5, 2016},
pages = {360--363},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ICCD.2016.7753303},
doi = {10.1109/ICCD.2016.7753303},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccd/GoliSD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/GrosseLHD16,
author = {Daniel Gro{\ss}e and
Hoang M. Le and
Muhammad Hassan and
Rolf Drechsler},
title = {Guided lightweight Software test qualification for {IP} integration
using Virtual Prototypes},
booktitle = {34th {IEEE} International Conference on Computer Design, {ICCD} 2016,
Scottsdale, AZ, USA, October 2-5, 2016},
pages = {606--613},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ICCD.2016.7753347},
doi = {10.1109/ICCD.2016.7753347},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/GrosseLHD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/BurmanDW0D16,
author = {Shuchishman Burman and
Kamalika Datta and
Robert Wille and
Indranil Sengupta and
Rolf Drechsler},
title = {An improved gate library for logic synthesis of optical circuits},
booktitle = {Sixth International Symposium on Embedded Computing and System Design,
{ISED} 2016, Patna, India, December 15-17, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISED.2016.7977044},
doi = {10.1109/ISED.2016.7977044},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/ised/BurmanDW0D16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/WilleKOTD16,
author = {Robert Wille and
Oliver Kesz{\"{o}}cze and
Lars Othmer and
Michael Kirkedal Thomsen and
Rolf Drechsler},
title = {Generating and checking control logic in the HDL-based design of reversible
circuits},
booktitle = {Sixth International Symposium on Embedded Computing and System Design,
{ISED} 2016, Patna, India, December 15-17, 2016},
pages = {7--12},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISED.2016.7977045},
doi = {10.1109/ISED.2016.7977045},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ised/WilleKOTD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/DrechslerEEHM16,
author = {Rolf Drechsler and
Stephan Eggersgl{\"{u}}{\ss} and
Nils Ellendt and
Sebastian Huhn and
Lutz M{\"{a}}dler},
title = {Exploring superior structural materials using multi-objective optimization
and formal techniques},
booktitle = {Sixth International Symposium on Embedded Computing and System Design,
{ISED} 2016, Patna, India, December 15-17, 2016},
pages = {13--17},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISED.2016.7977046},
doi = {10.1109/ISED.2016.7977046},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ised/DrechslerEEHM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/FilhoPWD16,
author = {Jonas Gomes Filho and
Nils Przigoda and
Robert Wille and
Rolf Drechsler},
title = {Towards a model-based verification methodology for Complex Swarm Systems
(Invited paper)},
booktitle = {Sixth International Symposium on Embedded Computing and System Design,
{ISED} 2016, Patna, India, December 15-17, 2016},
pages = {18--23},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISED.2016.7977047},
doi = {10.1109/ISED.2016.7977047},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ised/FilhoPWD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/Al-WardiWD16,
author = {Zaid Al{-}Wardi and
Robert Wille and
Rolf Drechsler},
title = {Re-Writing {HDL} Descriptions for Line-Aware Synthesis of Reversible
Circuits},
booktitle = {46th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2016, Sapporo, Japan, May 18-20, 2016},
pages = {31--36},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISMVL.2016.36},
doi = {10.1109/ISMVL.2016.36},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/Al-WardiWD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/PrzigodaDWD16,
author = {Nils Przigoda and
Gerhard W. Dueck and
Robert Wille and
Rolf Drechsler},
title = {Fault Detection in Parity Preserving Reversible Circuits},
booktitle = {46th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2016, Sapporo, Japan, May 18-20, 2016},
pages = {44--49},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISMVL.2016.44},
doi = {10.1109/ISMVL.2016.44},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/PrzigodaDWD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/AbdessaiedASD16,
author = {Nabila Abdessaied and
Matthew Amy and
Mathias Soeken and
Rolf Drechsler},
title = {Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits},
booktitle = {46th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2016, Sapporo, Japan, May 18-20, 2016},
pages = {150--155},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISMVL.2016.33},
doi = {10.1109/ISMVL.2016.33},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/AbdessaiedASD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/BiswalBCWDR16,
author = {Laxmidhar Biswal and
Chandan Bandyopadhyay and
Anupam Chattopadhyay and
Robert Wille and
Rolf Drechsler and
Hafizur Rahaman},
title = {Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation},
booktitle = {46th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2016, Sapporo, Japan, May 18-20, 2016},
pages = {156--161},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISMVL.2016.48},
doi = {10.1109/ISMVL.2016.48},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/BiswalBCWDR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ldic/DrechslerAL16,
author = {Rolf Drechsler and
Serge Autexier and
Christoph L{\"{u}}th},
editor = {Michael Freitag and
Herbert Kotzab and
J{\"{u}}rgen Pannek},
title = {Model-Based Specification and Refinement for Cyber-Physical Systems},
booktitle = {Dynamics in Logistics, Proceedings of the 5th International Conference
{LDIC} 2016, Bremen, Germany, February 22-25, 2016},
series = {Lecture Notes in Logistics},
pages = {3--17},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-45117-6\_1},
doi = {10.1007/978-3-319-45117-6\_1},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ldic/DrechslerAL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/Chandrasekharan16,
author = {Arun Chandrasekharan and
Daniel Gro{\ss}e and
Mathias Soeken and
Rolf Drechsler},
editor = {Ralf Wimmer},
title = {Symbolic Error Metric Determination for Approximate Computing},
booktitle = {19th {GI/ITG/GMM} Workshop Methoden und Beschreibungssprachen zur
Modellierung und Verifikation von Schaltungen und Systemen, {MBMV}
2016, Freiburg im Breisgau, Germany, March 1-2, 2016},
pages = {75--76},
publisher = {Albert-Ludwigs-Universit{\"{a}}t Freiburg},
year = {2016},
url = {https://doi.org/10.6094/UNIFR/10640},
doi = {10.6094/UNIFR/10640},
timestamp = {Fri, 26 Jun 2020 16:58:03 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/Chandrasekharan16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/PrzigodaFNWD16,
author = {Nils Przigoda and
Jonas Gomes Filho and
Philipp Niemann and
Robert Wille and
Rolf Drechsler},
title = {Frame conditions in symbolic representations of {UML/OCL} models},
booktitle = {2016 {ACM/IEEE} International Conference on Formal Methods and Models
for System Design, {MEMOCODE} 2016, Kanpur, India, November 18-20,
2016},
pages = {65--70},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/MEMCOD.2016.7797747},
doi = {10.1109/MEMCOD.2016.7797747},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/memocode/PrzigodaFNWD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/PetersPWD16,
author = {Judith Peters and
Nils Przigoda and
Robert Wille and
Rolf Drechsler},
title = {Clocks vs. instants relations: Verifying {CCSL} time constraints in
{UML/MARTE} models},
booktitle = {2016 {ACM/IEEE} International Conference on Formal Methods and Models
for System Design, {MEMOCODE} 2016, Kanpur, India, November 18-20,
2016},
pages = {78--84},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/MEMCOD.2016.7797750},
doi = {10.1109/MEMCOD.2016.7797750},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/memocode/PetersPWD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/models/PrzigodaHPWGD16,
author = {Nils Przigoda and
Frank Hilken and
Judith Peters and
Robert Wille and
Martin Gogolla and
Rolf Drechsler},
editor = {Michalis Famelis and
Daniel Ratiu and
Gehan M. K. Selim},
title = {Integrating an SMT-Based ModelFinder into {USE}},
booktitle = {Proceedings of the 13th Workshop on Model-Driven Engineering, Verification
and Validation co-located with {ACM/IEEE} 19th International Conference
on Model Driven Engineering Languages and Systems {(MODELS} 2016),
Saint-Malo, France, October 3, 2016},
series = {{CEUR} Workshop Proceedings},
volume = {1713},
pages = {40--45},
publisher = {CEUR-WS.org},
year = {2016},
url = {https://ceur-ws.org/Vol-1713/MoDeVVa\_2016\_paper\_5.pdf},
timestamp = {Fri, 10 Mar 2023 16:22:21 +0100},
biburl = {https://dblp.org/rec/conf/models/PrzigodaHPWGD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/models/PrzigodaWD16,
author = {Nils Przigoda and
Robert Wille and
Rolf Drechsler},
editor = {Benoit Baudry and
Beno{\^{\i}}t Combemale},
title = {Ground setting properties for an efficient translation of {OCL} in
SMT-based model finding},
booktitle = {Proceedings of the {ACM/IEEE} 19th International Conference on Model
Driven Engineering Languages and Systems, Saint-Malo, France, October
2-7, 2016},
pages = {261--271},
publisher = {{ACM}},
year = {2016},
url = {http://dl.acm.org/citation.cfm?id=2976780},
timestamp = {Tue, 06 Nov 2018 16:57:17 +0100},
biburl = {https://dblp.org/rec/conf/models/PrzigodaWD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/WilleKOTD16,
author = {Robert Wille and
Oliver Kesz{\"{o}}cze and
Lars Othmer and
Michael Kirkedal Thomsen and
Rolf Drechsler},
editor = {Simon J. Devitt and
Ivan Lanese},
title = {Initial Ideas for Automatic Design and Verification of Control Logic
in Reversible HDLs - Work in Progress Report},
booktitle = {Reversible Computation - 8th International Conference, {RC} 2016,
Bologna, Italy, July 7-8, 2016, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {9720},
pages = {160--166},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-40578-0\_11},
doi = {10.1007/978-3-319-40578-0\_11},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/WilleKOTD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/WilleCD16,
author = {Robert Wille and
Anupam Chattopadhyay and
Rolf Drechsler},
editor = {Walid A. Najjar and
Andreas Gerstlauer},
title = {From reversible logic to quantum circuits: Logic design for an emerging
technology},
booktitle = {International Conference on Embedded Computer Systems: Architectures,
Modeling and Simulation, {SAMOS} 2016, Agios Konstantinos, Samos Island,
Greece, July 17-21, 2016},
pages = {268--274},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/SAMOS.2016.7818357},
doi = {10.1109/SAMOS.2016.7818357},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/samos/WilleCD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/DrechslerS16,
author = {Rolf Drechsler and
Jannis Stoppe},
title = {Hardware/Software Co-Visualization on the Electronic System Level
Using SystemC},
booktitle = {29th International Conference on {VLSI} Design and 15th International
Conference on Embedded Systems, {VLSID} 2016, Kolkata, India, January
4-8, 2016},
pages = {44--49},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/VLSID.2016.45},
doi = {10.1109/VLSID.2016.45},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/DrechslerS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/BiswalBWDR16,
author = {Laxmidhar Biswal and
Chandan Bandyopadhyay and
Robert Wille and
Rolf Drechsler and
Hafizur Rahaman},
title = {Improving the Realization of Multiple-Control Toffoli Gates Using
the {NCVW} Quantum Gate Library},
booktitle = {29th International Conference on {VLSI} Design and 15th International
Conference on Embedded Systems, {VLSID} 2016, Kolkata, India, January
4-8, 2016},
pages = {573--574},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/VLSID.2016.23},
doi = {10.1109/VLSID.2016.23},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/BiswalBWDR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fdl/2016,
editor = {Rolf Drechsler and
Robert Wille},
title = {2016 Forum on Specification and Design Languages, {FDL} 2016, Bremen,
Germany, September 14-16, 2016},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/xpl/conhome/7879501/proceeding},
isbn = {979-10-92279-17-7},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/2016.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0035594,
author = {Mathias Soeken and
Rolf Drechsler},
title = {Formal Specification Level - Concepts, Methods, and Algorithms},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-08699-6},
doi = {10.1007/978-3-319-08699-6},
isbn = {978-3-319-08698-9},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0035594.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chb/GrosseJD15,
author = {Cornelia S. Gro{\ss}e and
Lisa Jungmann and
Rolf Drechsler},
title = {Benefits of illustrations and videos for technical documentations},
journal = {Comput. Hum. Behav.},
volume = {45},
pages = {109--120},
year = {2015},
url = {https://doi.org/10.1016/j.chb.2014.11.095},
doi = {10.1016/J.CHB.2014.11.095},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/chb/GrosseJD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/WilleKDBK15,
author = {Robert Wille and
Oliver Kesz{\"{o}}cze and
Rolf Drechsler and
Tobias Boehnisch and
Alexander Kroker},
title = {Scalable One-Pass Synthesis for Digital Microfluidic Biochips},
journal = {{IEEE} Des. Test},
volume = {32},
number = {6},
pages = {41--50},
year = {2015},
url = {https://doi.org/10.1109/MDAT.2015.2455344},
doi = {10.1109/MDAT.2015.2455344},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/WilleKDBK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/nc/DrechslerSD15,
author = {Nicole Drechsler and
Andr{\'{e}} S{\"{u}}lflow and
Rolf Drechsler},
title = {Incorporating user preferences in many-objective optimization using
relation {\(\epsilon\)}-preferred},
journal = {Nat. Comput.},
volume = {14},
number = {3},
pages = {469--483},
year = {2015},
url = {https://doi.org/10.1007/s11047-014-9422-0},
doi = {10.1007/S11047-014-9422-0},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/nc/DrechslerSD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/StoppeD15,
author = {Jannis Stoppe and
Rolf Drechsler},
title = {Analyzing SystemC Designs: SystemC Analysis Approaches for Varying
Applications},
journal = {Sensors},
volume = {15},
number = {5},
pages = {10399--10421},
year = {2015},
url = {https://doi.org/10.3390/s150510399},
doi = {10.3390/S150510399},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sensors/StoppeD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WilleKHD15,
author = {Robert Wille and
Oliver Kesz{\"{o}}cze and
Clemens Hopfmuller and
Rolf Drechsler},
title = {Reverse BDD-based synthesis for splitter-free optical circuits},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {172--177},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7059000},
doi = {10.1109/ASPDAC.2015.7059000},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WilleKHD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LyeWD15,
author = {Aaron Lye and
Robert Wille and
Rolf Drechsler},
title = {Determining the minimal number of swap gates for multi-dimensional
nearest neighbor quantum circuits},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {178--183},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7059001},
doi = {10.1109/ASPDAC.2015.7059001},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LyeWD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/atva/HerdtLGD15,
author = {Vladimir Herdt and
Hoang Minh Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Bernd Finkbeiner and
Geguang Pu and
Lijun Zhang},
title = {Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded
{C} Programs via Symbolic Pruning of Redundant Schedules},
booktitle = {Automated Technology for Verification and Analysis - 13th International
Symposium, {ATVA} 2015, Shanghai, China, October 12-15, 2015, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {9364},
pages = {228--233},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-24953-7\_18},
doi = {10.1007/978-3-319-24953-7\_18},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/atva/HerdtLGD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HerdtLD15,
author = {Vladimir Herdt and
Hoang Minh Le and
Rolf Drechsler},
title = {Verifying SystemC using stateful symbolic simulation},
booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
CA, USA, June 7-11, 2015},
pages = {49:1--49:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2744769.2744927},
doi = {10.1145/2744769.2744927},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/HerdtLD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PetersWPKD15,
author = {Judith Peters and
Robert Wille and
Nils Przigoda and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
title = {A generic representation of {CCSL} time constraints for {UML/MARTE}
models},
booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
CA, USA, June 7-11, 2015},
pages = {122:1--122:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2744769.2744775},
doi = {10.1145/2744769.2744775},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/PetersWPKD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/StoppeWD15,
author = {Jannis Stoppe and
Robert Wille and
Rolf Drechsler},
editor = {Wolfgang Nebel and
David Atienza},
title = {Automated feature localization for dynamically generated SystemC designs},
booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe
Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March
9-13, 2015},
pages = {277--280},
publisher = {{ACM}},
year = {2015},
url = {http://dl.acm.org/citation.cfm?id=2755814},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/StoppeWD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/PrzigodaWD15,
author = {Nils Przigoda and
Robert Wille and
Rolf Drechsler},
editor = {Zoran Stamenkovic and
Witold A. Pleskacz and
Jaan Raik and
Heinrich Theodor Vierhaus},
title = {Contradiction Analysis for Inconsistent Formal Models},
booktitle = {18th {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2015, Belgrade, Serbia, April 22-24,
2015},
pages = {171--176},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/DDECS.2015.52},
doi = {10.1109/DDECS.2015.52},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/PrzigodaWD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/Allahyari-Abhari15,
author = {Arman Allahyari{-}Abhari and
Mathias Soeken and
Rolf Drechsler},
editor = {Zoran Stamenkovic and
Witold A. Pleskacz and
Jaan Raik and
Heinrich Theodor Vierhaus},
title = {Requirement Phrasing Assistance Using Automatic Quality Assessment},
booktitle = {18th {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2015, Belgrade, Serbia, April 22-24,
2015},
pages = {183--188},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/DDECS.2015.19},
doi = {10.1109/DDECS.2015.19},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/Allahyari-Abhari15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/PrzigodaWD15,
author = {Nils Przigoda and
Robert Wille and
Rolf Drechsler},
title = {Leveraging the Analysis for Invariant Independence in Formal System
Models},
booktitle = {2015 Euromicro Conference on Digital System Design, {DSD} 2015, Madeira,
Portugal, August 26-28, 2015},
pages = {359--366},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/DSD.2015.85},
doi = {10.1109/DSD.2015.85},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/PrzigodaWD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/PrzigodaSSWD15,
author = {Nils Przigoda and
Jannis Stoppe and
Julia Seiter and
Robert Wille and
Rolf Drechsler},
title = {Verification-Driven Design Across Abstraction Levels: {A} Case Study},
booktitle = {2015 Euromicro Conference on Digital System Design, {DSD} 2015, Madeira,
Portugal, August 26-28, 2015},
pages = {375--382},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/DSD.2015.88},
doi = {10.1109/DSD.2015.88},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/PrzigodaSSWD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/SoekenSDB15,
author = {Mathias Soeken and
Baruch Sterin and
Rolf Drechsler and
Robert K. Brayton},
editor = {Roope Kaivola and
Thomas Wahl},
title = {Simulation Graphs for Reverse Engineering},
booktitle = {Formal Methods in Computer-Aided Design, {FMCAD} 2015, Austin, Texas,
USA, September 27-30, 2015},
pages = {152--159},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/FMCAD.2015.7542265},
doi = {10.1109/FMCAD.2015.7542265},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fmcad/SoekenSDB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/ShirinzadehSD15,
author = {Saeideh Shirinzadeh and
Mathias Soeken and
Rolf Drechsler},
editor = {Sara Silva and
Anna Isabel Esparcia{-}Alc{\'{a}}zar},
title = {Multi-Objective {BDD} Optimization with Evolutionary Algorithms},
booktitle = {Proceedings of the Genetic and Evolutionary Computation Conference,
{GECCO} 2015, Madrid, Spain, July 11-15, 2015},
pages = {751--758},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2739480.2754718},
doi = {10.1145/2739480.2754718},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/gecco/ShirinzadehSD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/green/DrechslerW15,
author = {Rolf Drechsler and
Robert Wille},
title = {Reversible computation},
booktitle = {Sixth International Green and Sustainable Computing Conference, {IGSC}
2015, Las Vegas, NV, USA, December 14-16, 2015},
pages = {1--5},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/IGCC.2015.7393687},
doi = {10.1109/IGCC.2015.7393687},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/green/DrechslerW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WilleD15,
author = {Robert Wille and
Rolf Drechsler},
editor = {Diana Marculescu and
Frank Liu},
title = {Formal Methods for Emerging Technologies},
booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
pages = {65--70},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCAD.2015.7372551},
doi = {10.1109/ICCAD.2015.7372551},
timestamp = {Mon, 26 Jun 2023 16:43:56 +0200},
biburl = {https://dblp.org/rec/conf/iccad/WilleD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KeszoczeWCD15,
author = {Oliver Kesz{\"{o}}cze and
Robert Wille and
Krishnendu Chakrabarty and
Rolf Drechsler},
editor = {Diana Marculescu and
Frank Liu},
title = {A General and Exact Routing Methodology for Digital Microfluidic Biochips},
booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
pages = {874--881},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCAD.2015.7372663},
doi = {10.1109/ICCAD.2015.7372663},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/KeszoczeWCD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/DebWDD15,
author = {Arighna Deb and
Robert Wille and
Rolf Drechsler and
Debesh K. Das},
title = {An Efficient Reduction of Common Control Lines for Reversible Circuit
Optimization},
booktitle = {2015 {IEEE} International Symposium on Multiple-Valued Logic, Waterloo,
ON, Canada, May 18-20, 2015},
pages = {14--19},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISMVL.2015.26},
doi = {10.1109/ISMVL.2015.26},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/DebWDD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/Allahyari-Abhari15,
author = {Arman Allahyari{-}Abhari and
Robert Wille and
Rolf Drechsler},
title = {An Examination of the NCV-{\(\vert\)}u1 {\textgreater} Quantum Library
Based on Minimal Circuits},
booktitle = {2015 {IEEE} International Symposium on Multiple-Valued Logic, Waterloo,
ON, Canada, May 18-20, 2015},
pages = {42--47},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISMVL.2015.25},
doi = {10.1109/ISMVL.2015.25},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/Allahyari-Abhari15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/Sayed-AhmedKGD15,
author = {Amr A. R. Sayed{-}Ahmed and
Ulrich K{\"{u}}hne and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Recurrence Relations Revisited: Scalable Verification of Bit Level
Multiplier Circuits},
booktitle = {2015 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2015,
Montpellier, France, July 8-10, 2015},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISVLSI.2015.45},
doi = {10.1109/ISVLSI.2015.45},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/Sayed-AhmedKGD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/PrzigodaWD15,
author = {Nils Przigoda and
Robert Wille and
Rolf Drechsler},
editor = {Ulrich Heinkel and
Daniel Kriesten and
Marko R{\"{o}}{\ss}ler},
title = {Verbesserung der Fehlersuche in inkonsistenten formalen Modellen (Erweiterte
Zusammenfassung)},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen, {MBMV} 2015, Chemnitz, Germany, March
3-4, 2015},
pages = {165--172},
publisher = {S{\"{a}}chsische Landesbibliothek},
year = {2015},
timestamp = {Sat, 17 Jul 2021 09:02:10 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/PrzigodaWD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/models/PrzigodaPSWD15,
author = {Nils Przigoda and
Judith Peters and
Mathias Soeken and
Robert Wille and
Rolf Drechsler},
editor = {Michalis Famelis and
Daniel Ratiu and
Martina Seidl and
Gehan M. K. Selim},
title = {Towards an Automatic Approach for Restricting {UML/OCL} Invariability
Clauses},
booktitle = {Proceedings of the 12th Workshop on Model-Driven Engineering, Verification
and Validation co-located with {ACM/IEEE} 18th International Conference
on Model Driven Engineering Languages and Systems, MoDeVVa@MoDELS
2015, Ottawa, Canada, September 29, 2015},
series = {{CEUR} Workshop Proceedings},
volume = {1514},
pages = {44--47},
publisher = {CEUR-WS.org},
year = {2015},
url = {https://ceur-ws.org/Vol-1514/paper6.pdf},
timestamp = {Fri, 10 Mar 2023 16:22:20 +0100},
biburl = {https://dblp.org/rec/conf/models/PrzigodaPSWD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/models/PrzigodaHWPD15,
author = {Nils Przigoda and
Christoph Hilken and
Robert Wille and
Jan Peleska and
Rolf Drechsler},
editor = {Timothy Lethbridge and
Jordi Cabot and
Alexander Egyed},
title = {Checking concurrent behavior in {UML/OCL} models},
booktitle = {18th {ACM/IEEE} International Conference on Model Driven Engineering
Languages and Systems, MoDELS 2015, Ottawa, ON, Canada, September
30 - October 2, 2015},
pages = {176--185},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/MODELS.2015.7338248},
doi = {10.1109/MODELS.2015.7338248},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/models/PrzigodaHWPD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/AbdessaiedSD15,
author = {Nabila Abdessaied and
Mathias Soeken and
Rolf Drechsler},
editor = {Jean Krivine and
Jean{-}Bernard Stefani},
title = {Technology Mapping for Single Target Gate Based Circuits Using Boolean
Functional Decomposition},
booktitle = {Reversible Computation - 7th International Conference, {RC} 2015,
Grenoble, France, July 16-17, 2015, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {9138},
pages = {219--232},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-20860-2\_14},
doi = {10.1007/978-3-319-20860-2\_14},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/AbdessaiedSD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/Al-WardiWD15,
author = {Zaid Al{-}Wardi and
Robert Wille and
Rolf Drechsler},
editor = {Jean Krivine and
Jean{-}Bernard Stefani},
title = {Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis
of Reversible Circuits},
booktitle = {Reversible Computation - 7th International Conference, {RC} 2015,
Grenoble, France, July 16-17, 2015, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {9138},
pages = {233--247},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-20860-2\_15},
doi = {10.1007/978-3-319-20860-2\_15},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rc/Al-WardiWD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/recosoc/DrechslerFW15,
author = {Rolf Drechsler and
Martin Fr{\"{a}}nzle and
Robert Wille},
title = {Envisioning self-verification of electronic systems},
booktitle = {10th International Symposium on Reconfigurable Communication-centric
Systems-on-Chip, ReCoSoC 2015, Bremen, Germany, June 29 - July 1,
2015},
pages = {1--6},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ReCoSoC.2015.7238101},
doi = {10.1109/RECOSOC.2015.7238101},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/recosoc/DrechslerFW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/Chandrasekharan15,
author = {Arun Chandrasekharan and
Kenneth Schmitz and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
title = {Ensuring safety and reliability of IP-based system design - {A} container
approach},
booktitle = {2015 International Symposium on Rapid System Prototyping, {RSP} 2015,
Amsterdam, The Netherlands, October 8-9, 2015},
pages = {76--82},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/RSP.2015.7416550},
doi = {10.1109/RSP.2015.7416550},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/rsp/Chandrasekharan15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/syde/DiepenbeckD15,
author = {Melanie Diepenbeck and
Rolf Drechsler},
editor = {Rolf Drechsler and
Ulrich K{\"{u}}hne},
title = {Behavior Driven Development for Tests and Verification},
booktitle = {Formal Modeling and Verification of Cyber-Physical Systems, 1st International
Summer School on Methods and Tools for the Design of Digital Systems,
Bremen, Germany, September 2015},
pages = {275--277},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-658-09994-7\_11},
doi = {10.1007/978-3-658-09994-7\_11},
timestamp = {Sun, 02 Jun 2019 21:16:43 +0200},
biburl = {https://dblp.org/rec/conf/syde/DiepenbeckD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/syde/PetersD15,
author = {Judith Peters and
Rolf Drechsler},
editor = {Rolf Drechsler and
Ulrich K{\"{u}}hne},
title = {Analyzing and Simulating Time Descriptions from {UML/MARTE} {CCSL}},
booktitle = {Formal Modeling and Verification of Cyber-Physical Systems, 1st International
Summer School on Methods and Tools for the Design of Digital Systems,
Bremen, Germany, September 2015},
pages = {293--295},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-658-09994-7\_17},
doi = {10.1007/978-3-658-09994-7\_17},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/syde/PetersD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/syde/SchonbornD15,
author = {Eleonora Sch{\"{o}}nborn and
Rolf Drechsler},
editor = {Rolf Drechsler and
Ulrich K{\"{u}}hne},
title = {Design and Synthesis of Reversible Circuits using Hardware Description
Languages},
booktitle = {Formal Modeling and Verification of Cyber-Physical Systems, 1st International
Summer School on Methods and Tools for the Design of Digital Systems,
Bremen, Germany, September 2015},
pages = {296--298},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-658-09994-7\_18},
doi = {10.1007/978-3-658-09994-7\_18},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/syde/SchonbornD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/syde/SeiterD15,
author = {Julia Seiter and
Rolf Drechsler},
editor = {Rolf Drechsler and
Ulrich K{\"{u}}hne},
title = {Development of Consistent Formal Models},
booktitle = {Formal Modeling and Verification of Cyber-Physical Systems, 1st International
Summer School on Methods and Tools for the Design of Digital Systems,
Bremen, Germany, September 2015},
pages = {302--304},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-658-09994-7\_20},
doi = {10.1007/978-3-658-09994-7\_20},
timestamp = {Tue, 15 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/syde/SeiterD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tap/SoekenSD15,
author = {Mathias Soeken and
Julia Seiter and
Rolf Drechsler},
editor = {Jasmin Christian Blanchette and
Nikolai Kosmatov},
title = {Coverage of {OCL} Operation Specifications and Invariants},
booktitle = {Tests and Proofs - 9th International Conference, TAP@STAF 2015, L'Aquila,
Italy, July 22-24, 2015. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {9154},
pages = {191--207},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-319-21215-9\_12},
doi = {10.1007/978-3-319-21215-9\_12},
timestamp = {Tue, 15 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/tap/SoekenSD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AbdessaiedSDD15,
author = {Nabila Abdessaied and
Mathias Soeken and
Gerhard W. Dueck and
Rolf Drechsler},
title = {Reversible circuit rewriting with simulated annealing},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {286--291},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314431},
doi = {10.1109/VLSI-SOC.2015.7314431},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AbdessaiedSDD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SchonbornDWSRD15,
author = {Eleonora Sch{\"{o}}nborn and
Kamalika Datta and
Robert Wille and
Indranil Sengupta and
Hafizur Rahaman and
Rolf Drechsler},
title = {BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits},
booktitle = {28th International Conference on {VLSI} Design, {VLSID} 2015, Bangalore,
India, January 3-7, 2015},
pages = {435--440},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/VLSID.2015.79},
doi = {10.1109/VLSID.2015.79},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SchonbornDWSRD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/syde/2015,
editor = {Rolf Drechsler and
Ulrich K{\"{u}}hne},
title = {Formal Modeling and Verification of Cyber-Physical Systems, 1st International
Summer School on Methods and Tools for the Design of Digital Systems,
Bremen, Germany, September 2015},
publisher = {Springer},
year = {2015},
url = {https://doi.org/10.1007/978-3-658-09994-7},
doi = {10.1007/978-3-658-09994-7},
isbn = {978-3-658-09993-0},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/syde/2015.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WilleSMD14,
author = {Robert Wille and
Mathias Soeken and
D. Michael Miller and
Rolf Drechsler},
title = {Trading off circuit lines and gate costs in the synthesis of reversible
logic},
journal = {Integr.},
volume = {47},
number = {2},
pages = {284--294},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.08.002},
doi = {10.1016/J.VLSI.2013.08.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WilleSMD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipl/AbdessaiedSTD14,
author = {Nabila Abdessaied and
Mathias Soeken and
Michael Kirkedal Thomsen and
Rolf Drechsler},
title = {Upper bounds for reversible circuits based on Young subgroups},
journal = {Inf. Process. Lett.},
volume = {114},
number = {6},
pages = {282--286},
year = {2014},
url = {https://doi.org/10.1016/j.ipl.2014.01.003},
doi = {10.1016/J.IPL.2014.01.003},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipl/AbdessaiedSTD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/it/Drechsler14,
author = {Rolf Drechsler},
title = {Testing integrated circuits},
journal = {it Inf. Technol.},
volume = {56},
number = {4},
pages = {148--149},
year = {2014},
url = {https://doi.org/10.1515/itit-2014-1043},
doi = {10.1515/ITIT-2014-1043},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/it/Drechsler14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/it/EggersglussD14,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {An effective fault ordering heuristic for SAT-based dynamic test compaction
techniques},
journal = {it Inf. Technol.},
volume = {56},
number = {4},
pages = {157--164},
year = {2014},
url = {https://doi.org/10.1515/itit-2013-1041},
doi = {10.1515/ITIT-2013-1041},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/it/EggersglussD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/WilleDT14,
author = {Robert Wille and
Rolf Drechsler and
Mehdi Baradaran Tahoori},
title = {Introduction to the Special Issue on Reversible Computation},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {11},
number = {2},
pages = {8:1--8:2},
year = {2014},
url = {https://doi.org/10.1145/2663349},
doi = {10.1145/2663349},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/WilleDT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/qip/WilleLD14,
author = {Robert Wille and
Aaron Lye and
Rolf Drechsler},
title = {Considering nearest neighbor constraints of quantum circuits at the
reversible circuit level},
journal = {Quantum Inf. Process.},
volume = {13},
number = {2},
pages = {185--199},
year = {2014},
url = {https://doi.org/10.1007/s11128-013-0642-5},
doi = {10.1007/S11128-013-0642-5},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/qip/WilleLD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WilleLD14,
author = {Robert Wille and
Aaron Lye and
Rolf Drechsler},
title = {Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1818--1831},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2356463},
doi = {10.1109/TCAD.2014.2356463},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WilleLD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcos/DattaSRD14,
author = {Kamalika Datta and
Indranil Sengupta and
Hafizur Rahaman and
Rolf Drechsler},
title = {An Approach to Reversible Logic Synthesis Using Input and Output Permutations},
journal = {Trans. Comput. Sci.},
volume = {24},
pages = {92--110},
year = {2014},
url = {https://doi.org/10.1007/978-3-662-45711-5\_6},
doi = {10.1007/978-3-662-45711-5\_6},
timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcos/DattaSRD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcos/BandyopadhyayRD14,
author = {Chandan Bandyopadhyay and
Hafizur Rahaman and
Rolf Drechsler},
title = {Improved Cube List Based Cube Pairing Approach for Synthesis of {ESOP}
Based Reversible Logic},
journal = {Trans. Comput. Sci.},
volume = {24},
pages = {129--146},
year = {2014},
url = {https://doi.org/10.1007/978-3-662-45711-5\_8},
doi = {10.1007/978-3-662-45711-5\_8},
timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcos/BandyopadhyayRD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/NiemannWD14,
author = {Philipp Niemann and
Robert Wille and
Rolf Drechsler},
title = {Efficient synthesis of quantum circuits implementing clifford group
operations},
booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2014, Singapore, January 20-23, 2014},
pages = {483--488},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASPDAC.2014.6742938},
doi = {10.1109/ASPDAC.2014.6742938},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/NiemannWD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WilleLD14,
author = {Robert Wille and
Aaron Lye and
Rolf Drechsler},
title = {Optimal {SWAP} gate insertion for nearest neighbor quantum circuits},
booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2014, Singapore, January 20-23, 2014},
pages = {489--494},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASPDAC.2014.6742939},
doi = {10.1109/ASPDAC.2014.6742939},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WilleLD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/birthday/HerbstrittD14,
author = {Marc Herbstritt and
Rolf Drechsler},
editor = {Rolf Drechsler},
title = {Der h2-lndex: Zur vermessenen Vermessung der wissenschaftlichen Welt},
booktitle = {Aspekte der Technischen Informatik - Festschrift zum 60. Geburtstag
von Bernd Becker},
pages = {35--50},
publisher = {MV-Wissenschaft},
year = {2014},
timestamp = {Thu, 04 Jun 2020 17:02:05 +0200},
biburl = {https://dblp.org/rec/conf/birthday/HerbstrittD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/OetjensBBBBCCDEGKKLM0MPPRRRSSTV14,
author = {Jan{-}Hendrik Oetjens and
Nico Bannow and
Markus Becker and
Oliver Bringmann and
Andreas Burger and
Moomen Chaari and
Samarjit Chakraborty and
Rolf Drechsler and
Wolfgang Ecker and
Kim Gr{\"{u}}ttner and
Thomas Kruse and
Christoph Kuznik and
Hoang Minh Le and
Andreas Mauderer and
Wolfgang M{\"{u}}ller and
Daniel M{\"{u}}ller{-}Gritschneder and
Frank Poppen and
Hendrik Post and
Sebastian Reiter and
Wolfgang Rosenstiel and
S. Roth and
Ulf Schlichtmann and
Andreas von Schwerin and
Bogdan{-}Andrei Tabacaru and
Alexander Viehl},
title = {Safety Evaluation of Automotive Electronics Using Virtual Prototypes:
State of the Art and Research Challenges},
booktitle = {The 51st Annual Design Automation Conference 2014, {DAC} '14, San
Francisco, CA, USA, June 1-5, 2014},
pages = {113:1--113:6},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2593069.2602976},
doi = {10.1145/2593069.2602976},
timestamp = {Wed, 25 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/OetjensBBBBCCDEGKKLM0MPPRRRSSTV14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KeszoczeWHD14,
author = {Oliver Kesz{\"{o}}cze and
Robert Wille and
Tsung{-}Yi Ho and
Rolf Drechsler},
title = {Exact One-pass Synthesis of Digital Microfluidic Biochips},
booktitle = {The 51st Annual Design Automation Conference 2014, {DAC} '14, San
Francisco, CA, USA, June 1-5, 2014},
pages = {142:1--142:6},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2593069.2593135},
doi = {10.1145/2593069.2593135},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/KeszoczeWHD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DrechslerCFHMSG14,
author = {Rolf Drechsler and
Christophe Chevallaz and
Franco Fummi and
Alan J. Hu and
Ronny Morad and
Frank Schirrmeister and
Alex Goryachev},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Panel: Future SoC verification methodology: {UVM} evolution or revolution?},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--5},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.385},
doi = {10.7873/DATE.2014.385},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/DrechslerCFHMSG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LeD14,
author = {Hoang Minh Le and
Rolf Drechsler},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Towards verifying determinism of SystemC designs},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--4},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.166},
doi = {10.7873/DATE.2014.166},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/LeD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/SchonbornDWSRD14,
author = {Eleonora Sch{\"{o}}nborn and
Kamalika Datta and
Robert Wille and
Indranil Sengupta and
Hafizur Rahaman and
Rolf Drechsler},
title = {Optimizing DD-based synthesis of reversible circuits using negative
control lines},
booktitle = {17th International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2014, Warsaw, Poland, 23-25 April,
2014},
pages = {129--134},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/DDECS.2014.6868776},
doi = {10.1109/DDECS.2014.6868776},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/SchonbornDWSRD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/YangWD14,
author = {Shuo Yang and
Robert Wille and
Rolf Drechsler},
title = {Improving Coverage of Simulation-Based Verification by Dedicated Stimuli
Generation},
booktitle = {17th Euromicro Conference on Digital System Design, {DSD} 2014, Verona,
Italy, August 27-29, 2014},
pages = {599--606},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/DSD.2014.100},
doi = {10.1109/DSD.2014.100},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/YangWD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dtis/BeckerDES14,
author = {Bernd Becker and
Rolf Drechsler and
Stephan Eggersgl{\"{u}}{\ss} and
Matthias Sauer},
title = {Recent advances in SAT-based {ATPG:} Non-standard fault models, multi
constraints and optimization},
booktitle = {Proceedings of the 9th International Conference on Design {\&}
Technology of Integrated Systems in Nanoscale Era, {DTIS} 2014, Santorini,
Greece, May 6-8, 2014},
pages = {1--10},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/DTIS.2014.6850674},
doi = {10.1109/DTIS.2014.6850674},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dtis/BeckerDES14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/EggersglussSKD14,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Kenneth Schmitz and
Rene Krenz{-}Baath and
Rolf Drechsler},
editor = {Giorgio Di Natale},
title = {Optimization-based multiple target test generation for highly compacted
test sets},
booktitle = {19th {IEEE} European Test Symposium, {ETS} 2014, Paderborn, Germany,
May 26-30, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ETS.2014.6847807},
doi = {10.1109/ETS.2014.6847807},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/ets/EggersglussSKD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/HilkenSWKD14,
author = {Christoph Hilken and
Julia Seiter and
Robert Wille and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
title = {Verifying consistency between activity diagrams and their corresponding
{OCL} contracts},
booktitle = {Proceedings of the 2014 Forum on Specification and Design Languages,
{FDL} 2014, Munich, Germany, October 14-16, 2014},
pages = {1--7},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FDL.2014.7119340},
doi = {10.1109/FDL.2014.7119340},
timestamp = {Tue, 15 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/HilkenSWKD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/RienerSWFD14,
author = {Heinz Riener and
Mathias Soeken and
Clemens Werther and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {MetaSMT: a unified interface to {SMT-LIB2}},
booktitle = {Proceedings of the 2014 Forum on Specification and Design Languages,
{FDL} 2014, Munich, Germany, October 14-16, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FDL.2014.7119353},
doi = {10.1109/FDL.2014.7119353},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/RienerSWFD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/SeiterWKD14,
author = {Julia Seiter and
Robert Wille and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
title = {Automatic refinement checking for formal system models},
booktitle = {Proceedings of the 2014 Forum on Specification and Design Languages,
{FDL} 2014, Munich, Germany, October 14-16, 2014},
pages = {1--8},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FDL.2014.7119339},
doi = {10.1109/FDL.2014.7119339},
timestamp = {Tue, 15 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/SeiterWKD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/SoekenHAHD14,
author = {Mathias Soeken and
Christopher B. Harris and
Nabila Abdessaied and
Ian G. Harris and
Rolf Drechsler},
title = {Automating the translation of assertions using natural language processing
techniques},
booktitle = {Proceedings of the 2014 Forum on Specification and Design Languages,
{FDL} 2014, Munich, Germany, October 14-16, 2014},
pages = {1--8},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FDL.2014.7119356},
doi = {10.1109/FDL.2014.7119356},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/SoekenHAHD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KeszoczeWD14,
author = {Oliver Kesz{\"{o}}cze and
Robert Wille and
Rolf Drechsler},
editor = {Yao{-}Wen Chang},
title = {Exact routing for digital microfluidic biochips with temporary blockages},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2014, San Jose, CA, USA, November 3-6, 2014},
pages = {405--410},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICCAD.2014.7001383},
doi = {10.1109/ICCAD.2014.7001383},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/KeszoczeWD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/DrechslerSW14,
author = {Rolf Drechsler and
Mathias Soeken and
Robert Wille},
editor = {Yao{-}Wen Chang},
title = {Automated and quality-driven requirements engineering},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2014, San Jose, CA, USA, November 3-6, 2014},
pages = {586--590},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICCAD.2014.7001410},
doi = {10.1109/ICCAD.2014.7001410},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/DrechslerSW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iceccs/PetersWD14,
author = {Judith Peters and
Robert Wille and
Rolf Drechsler},
title = {Generating SystemC Implementations for Clock Constraints Specified
in {UML/MARTE} {CCSL}},
booktitle = {2014 19th International Conference on Engineering of Complex Computer
Systems, Tianjin, China, August 4-7, 2014},
pages = {116--125},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ICECCS.2014.24},
doi = {10.1109/ICECCS.2014.24},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iceccs/PetersWD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip5-7/WiesnerGSTD14,
author = {Stefan A. Wiesner and
Christian Gorldt and
Mathias Soeken and
Klaus{-}Dieter Thoben and
Rolf Drechsler},
editor = {Bernard Grabot and
Bruno Vallespir and
Samuel Gomes and
Abdelaziz Bouras and
Dimitris Kiritsis},
title = {Requirements Engineering for Cyber-Physical Systems - Challenges in
the Context of "Industrie 4.0"},
booktitle = {Advances in Production Management Systems. Innovative and Knowledge-Based
Production Management in a Global-Local World - {IFIP} {WG} 5.7 International
Conference, {APMS} 2014, Ajaccio, France, September 20-24, 2014, Proceedings,
Part {I}},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {438},
pages = {281--288},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-662-44739-0\_35},
doi = {10.1007/978-3-662-44739-0\_35},
timestamp = {Fri, 10 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ifip5-7/WiesnerGSTD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/DrechslerK14,
author = {Rolf Drechsler and
Ulrich K{\"{u}}hne},
title = {Safe {IP} Integration Using Container Modules},
booktitle = {2014 Fifth International Symposium on Electronic System Design, Surathkal,
Mangalore, India, December 15-17, 2014},
pages = {1--4},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISED.2014.8},
doi = {10.1109/ISED.2014.8},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ised/DrechslerK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/BandyopadhyayRD14,
author = {Chandan Bandyopadhyay and
Hafizur Rahaman and
Rolf Drechsler},
title = {A Cube Pairing Approach for Synthesis of ESOP-Based Reversible Circuit},
booktitle = {{IEEE} 44th International Symposium on Multiple-Valued Logic, {ISMVL}
2014, Bremen, Germany, May 19-21, 2014},
pages = {109--114},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISMVL.2014.27},
doi = {10.1109/ISMVL.2014.27},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/BandyopadhyayRD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/WindhorstLGD14,
author = {Aljoscha Windhorst and
Hoang Minh Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {J{\"{u}}rgen Ruf and
Dirk Allmendinger and
Matteo Michel},
title = {Funktionale Abdeckungsanalyse von C-Programmen},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen, {MBMV} 2014, B{\"{o}}blingen, Germany},
pages = {201--204},
publisher = {Cuvillier},
year = {2014},
timestamp = {Tue, 12 Jul 2016 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/WindhorstLGD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/SoekenND14,
author = {Mathias Soeken and
Max Nitze and
Rolf Drechsler},
editor = {J{\"{u}}rgen Ruf and
Dirk Allmendinger and
Matteo Michel},
title = {Formale Methoden f{\"{u}}r Alle},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen, {MBMV} 2014, B{\"{o}}blingen, Germany},
pages = {213--216},
publisher = {Cuvillier},
year = {2014},
timestamp = {Thu, 13 Mar 2014 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/SoekenND14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/RienerKDF14,
author = {Heinz Riener and
Oliver Kesz{\"{o}}cze and
Rolf Drechsler and
G{\"{o}}rschwin Fey},
editor = {J{\"{u}}rgen Ruf and
Dirk Allmendinger and
Matteo Michel},
title = {A Logic for Cardinality Constraints (Extended Abstract)},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen, {MBMV} 2014, B{\"{o}}blingen, Germany},
pages = {217--220},
publisher = {Cuvillier},
year = {2014},
timestamp = {Tue, 14 Nov 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/RienerKDF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/WilleSSDD14,
author = {Robert Wille and
Jannis Stoppe and
Eleonora Sch{\"{o}}nborn and
Kamalika Datta and
Rolf Drechsler},
editor = {Shigeru Yamashita and
Shin{-}ichi Minato},
title = {RevVis: Visualization of Structures and Properties in Reversible Circuits},
booktitle = {Reversible Computation - 6th International Conference, {RC} 2014,
Kyoto, Japan, July 10-11, 2014. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {8507},
pages = {111--124},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-08494-7\_9},
doi = {10.1007/978-3-319-08494-7\_9},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/WilleSSDD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/AbdessaiedSD14,
author = {Nabila Abdessaied and
Mathias Soeken and
Rolf Drechsler},
editor = {Shigeru Yamashita and
Shin{-}ichi Minato},
title = {Quantum Circuit Optimization by Hadamard Gate Reduction},
booktitle = {Reversible Computation - 6th International Conference, {RC} 2014,
Kyoto, Japan, July 10-11, 2014. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {8507},
pages = {149--162},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-08494-7\_12},
doi = {10.1007/978-3-319-08494-7\_12},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/AbdessaiedSD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/MillerSD14,
author = {D. Michael Miller and
Mathias Soeken and
Rolf Drechsler},
editor = {Shigeru Yamashita and
Shin{-}ichi Minato},
title = {Mapping {NCV} Circuits to Optimized Clifford+T Circuits},
booktitle = {Reversible Computation - 6th International Conference, {RC} 2014,
Kyoto, Japan, July 10-11, 2014. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {8507},
pages = {163--175},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-08494-7\_13},
doi = {10.1007/978-3-319-08494-7\_13},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/MillerSD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/NiemannWD14,
author = {Philipp Niemann and
Robert Wille and
Rolf Drechsler},
editor = {Shigeru Yamashita and
Shin{-}ichi Minato},
title = {Equivalence Checking in Multi-level Quantum Systems},
booktitle = {Reversible Computation - 6th International Conference, {RC} 2014,
Kyoto, Japan, July 10-11, 2014. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {8507},
pages = {201--215},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-08494-7\_16},
doi = {10.1007/978-3-319-08494-7\_16},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rc/NiemannWD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/YangWD14,
author = {Shuo Yang and
Robert Wille and
Rolf Drechsler},
editor = {Edward David Moreno Ordonez and
Rodolfo Jardim de Azevedo and
Peter R. Kinget},
title = {Determining Cases of Scenarios to Improve Coverage in Simulation-based
Verification},
booktitle = {Proceedings of the 27th Symposium on Integrated Circuits and Systems
Design, Aracaju, Brazil, September 1-5, 2014},
pages = {11:1--11:7},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2660540.2660979},
doi = {10.1145/2660540.2660979},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/YangWD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/StoppeWD14,
author = {Jannis Stoppe and
Robert Wille and
Rolf Drechsler},
editor = {Edward David Moreno Ordonez and
Rodolfo Jardim de Azevedo and
Peter R. Kinget},
title = {Validating SystemC Implementations Against Their Formal Specifications},
booktitle = {Proceedings of the 27th Symposium on Integrated Circuits and Systems
Design, Aracaju, Brazil, September 1-5, 2014},
pages = {13:1--13:8},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2660540.2660981},
doi = {10.1145/2660540.2660981},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/StoppeWD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/DrechslerLS14,
author = {Rolf Drechsler and
Hoang Minh Le and
Mathias Soeken},
editor = {Edward David Moreno Ordonez and
Rodolfo Jardim de Azevedo and
Peter R. Kinget},
title = {Self-Verification as the Key Technology for Next Generation Electronic
Systems},
booktitle = {Proceedings of the 27th Symposium on Integrated Circuits and Systems
Design, Aracaju, Brazil, September 1-5, 2014},
pages = {15:1--15:4},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2660540.2660983},
doi = {10.1145/2660540.2660983},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/DrechslerLS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/semeval/BornebuschCDDDF14,
author = {Fritjof Bornebusch and
Glaucia Cancino and
Melanie Diepenbeck and
Rolf Drechsler and
Smith Djomkam and
Alvine Nzeungang Fanseu and
Maryam Jalali and
Marc Michael and
Jamal Mohsen and
Max Nitze and
Christina Plump and
Mathias Soeken and
Hubert Fred Tchambo and
Toni and
Henning Ziegler},
editor = {Preslav Nakov and
Torsten Zesch},
title = {iTac: Aspect Based Sentiment Analysis using Sentiment Trees and Dictionaries},
booktitle = {Proceedings of the 8th International Workshop on Semantic Evaluation,
SemEval@COLING 2014, Dublin, Ireland, August 23-24, 2014},
pages = {351--355},
publisher = {The Association for Computer Linguistics},
year = {2014},
url = {https://doi.org/10.3115/v1/s14-2059},
doi = {10.3115/V1/S14-2059},
timestamp = {Fri, 06 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/semeval/BornebuschCDDDF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tap/DiepenbeckKSD14,
author = {Melanie Diepenbeck and
Ulrich K{\"{u}}hne and
Mathias Soeken and
Rolf Drechsler},
editor = {Martina Seidl and
Nikolai Tillmann},
title = {Behaviour Driven Development for Tests and Verification},
booktitle = {Tests and Proofs - 8th International Conference, TAP@STAF 2014, York,
UK, July 24-25, 2014. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {8570},
pages = {61--77},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-09099-3\_5},
doi = {10.1007/978-3-319-09099-3\_5},
timestamp = {Tue, 23 Jun 2020 17:47:28 +0200},
biburl = {https://dblp.org/rec/conf/tap/DiepenbeckKSD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/birthday/2014becker,
editor = {Rolf Drechsler},
title = {Aspekte der Technischen Informatik - Festschrift zum 60. Geburtstag
von Bernd Becker},
publisher = {MV-Wissenschaft},
year = {2014},
isbn = {978-3-9564523-5-2},
timestamp = {Thu, 04 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/birthday/2014becker.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/SoekenAD14,
author = {Mathias Soeken and
Nabila Abdessaied and
Rolf Drechsler},
title = {A framework for reversible circuit complexity},
journal = {CoRR},
volume = {abs/1407.5878},
year = {2014},
url = {http://arxiv.org/abs/1407.5878},
eprinttype = {arXiv},
eprint = {1407.5878},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/SoekenAD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/SoekenWKMD14,
author = {Mathias Soeken and
Robert Wille and
Oliver Kesz{\"{o}}cze and
D. Michael Miller and
Rolf Drechsler},
title = {Embedding of Large Boolean Functions for Reversible Logic},
journal = {CoRR},
volume = {abs/1408.3586},
year = {2014},
url = {http://arxiv.org/abs/1408.3586},
eprinttype = {arXiv},
eprint = {1408.3586},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/SoekenWKMD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/SoekenTDD14,
author = {Mathias Soeken and
Laura Tague and
Gerhard W. Dueck and
Rolf Drechsler},
title = {Ancilla-free synthesis of large reversible functions using binary
decision diagrams},
journal = {CoRR},
volume = {abs/1408.3955},
year = {2014},
url = {http://arxiv.org/abs/1408.3955},
eprinttype = {arXiv},
eprint = {1408.3955},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/SoekenTDD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/eceasst/GrosseFD13,
author = {Daniel Gro{\ss}e and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {Enhanced Formal Verification Flow for Circuits Integrating Debugging
and Coverage Analysis},
journal = {Electron. Commun. Eur. Assoc. Softw. Sci. Technol.},
volume = {62},
year = {2013},
url = {https://doi.org/10.14279/tuj.eceasst.62.860},
doi = {10.14279/TUJ.ECEASST.62.860},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/eceasst/GrosseFD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/irob/KirchnerD13,
author = {Elsa Andrea Kirchner and
Rolf Drechsler},
title = {A formal model for embedded brain reading},
journal = {Ind. Robot},
volume = {40},
number = {6},
pages = {530--540},
year = {2013},
url = {https://doi.org/10.1108/IR-01-2013-318},
doi = {10.1108/IR-01-2013-318},
timestamp = {Thu, 16 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/irob/KirchnerD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/WilleSPD13,
author = {Robert Wille and
Mathias Soeken and
Nils Przigoda and
Rolf Drechsler},
title = {Effect of Negative Control Lines on the Exact Synthesis of Reversible
Circuits},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {21},
number = {5-6},
pages = {627--640},
year = {2013},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-21-number-5-6-2013/mvlsc-21-5-6-p-627-640/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/WilleSPD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/africon/WillePD13,
author = {Robert Wille and
Nils Przigoda and
Rolf Drechsler},
title = {A compact and efficient {SAT} encoding for quantum circuits},
booktitle = {{AFRICON} 2013, Pointe aux Piments, Mauritius, September 9-12, 2013},
pages = {1--6},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/AFRCON.2013.6757630},
doi = {10.1109/AFRCON.2013.6757630},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/africon/WillePD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/africon/WilleSD13,
author = {Robert Wille and
Simon Stelter and
Rolf Drechsler},
title = {Exploiting reversibility in the complete simulation of reversible
circuits},
booktitle = {{AFRICON} 2013, Pointe aux Piments, Mauritius, September 9-12, 2013},
pages = {1--6},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/AFRCON.2013.6757629},
doi = {10.1109/AFRCON.2013.6757629},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/africon/WilleSD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WilleSOD13,
author = {Robert Wille and
Mathias Soeken and
Christian Otterstedt and
Rolf Drechsler},
title = {Improving the mapping of reversible circuits to quantum circuits using
multiple target lines},
booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2013, Yokohama, Japan, January 22-25, 2013},
pages = {145--150},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASPDAC.2013.6509587},
doi = {10.1109/ASPDAC.2013.6509587},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WilleSOD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LeGHD13,
author = {Hoang Minh Le and
Daniel Gro{\ss}e and
Vladimir Herdt and
Rolf Drechsler},
title = {Verifying SystemC using an intermediate verification language and
symbolic simulation},
booktitle = {The 50th Annual Design Automation Conference 2013, {DAC} '13, Austin,
TX, USA, May 29 - June 07, 2013},
pages = {116:1--116:6},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2463209.2488877},
doi = {10.1145/2463209.2488877},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/LeGHD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LeGD13,
author = {Hoang Minh Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Enrico Macii},
title = {Scalable fault localization for SystemC {TLM} designs},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {35--38},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.022},
doi = {10.7873/DATE.2013.022},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/LeGD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SeiterWSD13,
author = {Julia Seiter and
Robert Wille and
Mathias Soeken and
Rolf Drechsler},
editor = {Enrico Macii},
title = {Determining relevant model elements for the verification of {UML/OCL}
specifications},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {1189--1192},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.247},
doi = {10.7873/DATE.2013.247},
timestamp = {Tue, 15 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/SeiterWSD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WilleGSKD13,
author = {Robert Wille and
Martin Gogolla and
Mathias Soeken and
Mirco Kuhlmann and
Rolf Drechsler},
editor = {Enrico Macii},
title = {Towards a generic verification methodology for system models},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {1193--1196},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.248},
doi = {10.7873/DATE.2013.248},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/WilleGSKD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/DrechslerS13,
author = {Rolf Drechsler and
Mathias Soeken},
editor = {Luk{\'{a}}s Sekanina and
G{\"{o}}rschwin Fey and
Jaan Raik and
Snorre Aunet and
Richard Ruzicka},
title = {Hardware-Software Co-Visualization: Developing systems in the holodeck},
booktitle = {16th {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2013, Karlovy Vary, Czech Republic,
April 8-10, 2013},
pages = {1--4},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/DDECS.2013.6549775},
doi = {10.1109/DDECS.2013.6549775},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/DrechslerS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/YangWGD13,
author = {Shuo Yang and
Robert Wille and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Minimal Stimuli Generation in Simulation-Based Verification},
booktitle = {2013 Euromicro Conference on Digital System Design, {DSD} 2013, Los
Alamitos, CA, USA, September 4-6, 2013},
pages = {439--444},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/DSD.2013.55},
doi = {10.1109/DSD.2013.55},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/YangWGD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/StoppeWD13,
author = {Jannis Stoppe and
Robert Wille and
Rolf Drechsler},
title = {Cone of Influence Analysis at the Electronic System Level Using Machine
Learning},
booktitle = {2013 Euromicro Conference on Digital System Design, {DSD} 2013, Los
Alamitos, CA, USA, September 4-6, 2013},
pages = {582--587},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/DSD.2013.69},
doi = {10.1109/DSD.2013.69},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/StoppeWD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gi/DrechslerW13,
author = {Rolf Drechsler and
Mathias Soeken and
Robert Wille},
editor = {Matthias Horbach},
title = {Text statt {C++:} Automatisierung des Systementwurfs mit Hilfe nat{\"{u}}rlicher
Sprachverarbeitung},
booktitle = {43. Jahrestagung der Gesellschaft f{\"{u}}r Informatik, Informatik
angepasst an Mensch, Organisation und Umwelt, {INFORMATIK} 2013, Koblenz,
Germany, September 16-20, 2013},
series = {{LNI}},
volume = {{P-220}},
pages = {151},
publisher = {{GI}},
year = {2013},
url = {https://dl.gi.de/handle/20.500.12116/20699},
timestamp = {Tue, 04 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/gi/DrechslerW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/EggersglussWD13,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Robert Wille and
Rolf Drechsler},
editor = {J{\"{o}}rg Henkel},
title = {Improved SAT-based {ATPG:} more constraints, better compaction},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
ICCAD'13, San Jose, CA, USA, November 18-21, 2013},
pages = {85--90},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ICCAD.2013.6691102},
doi = {10.1109/ICCAD.2013.6691102},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/EggersglussWD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icse/DiepenbeckSGD13,
author = {Melanie Diepenbeck and
Mathias Soeken and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Hong Zhu and
Henry Muccini and
Zhenyu Chen},
title = {Towards automatic scenario generation from coverage information},
booktitle = {8th International Workshop on Automation of Software Test, {AST} 2013,
San Francisco, CA, USA, May 18-19, 2013},
pages = {82--88},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/IWAST.2013.6595796},
doi = {10.1109/IWAST.2013.6595796},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icse/DiepenbeckSGD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/idt/DattaSRD13,
author = {Kamalika Datta and
Indranil Sengupta and
Hafizur Rahaman and
Rolf Drechsler},
title = {An evolutionary approach to reversible logic synthesis using output
permutation},
booktitle = {8th International Design and Test Symposium, {IDT} 2013, Marrakesh,
Morocco, 16-18 December, 2013},
pages = {1--6},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/IDT.2013.6727117},
doi = {10.1109/IDT.2013.6727117},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/idt/DattaSRD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/idt/SoekenD13,
author = {Mathias Soeken and
Rolf Drechsler},
title = {Grammar-based program generation based on model finding},
booktitle = {8th International Design and Test Symposium, {IDT} 2013, Marrakesh,
Morocco, 16-18 December, 2013},
pages = {1--5},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/IDT.2013.6727084},
doi = {10.1109/IDT.2013.6727084},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/idt/SoekenD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ijcci/DrechslerSD13,
author = {Nicole Drechsler and
Andr{\'{e}} S{\"{u}}lflow and
Rolf Drechsler},
editor = {Agostinho C. Rosa and
Ant{\'{o}}nio Dourado and
Kurosh Madani Correia and
Joaquim Filipe and
Janusz Kacprzyk},
title = {Incorporating User Preferences in Many-Objective Optimization using
Relation Epsilon-Preferred},
booktitle = {{IJCCI} 2013 - Proceedings of the 5th International Joint Conference
on Computational Intelligence, Vilamoura, Algarve, Portugal, 20-22
September, 2013},
pages = {67--74},
publisher = {SciTePress},
year = {2013},
url = {https://doi.org/10.5220/0004496000670074},
doi = {10.5220/0004496000670074},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ijcci/DrechslerSD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/WilleZD13,
author = {Robert Wille and
Hongyan Zhang and
Rolf Drechsler},
title = {Fault Ordering for Automatic Test Pattern Generation of Reversible
Circuits},
booktitle = {43rd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2013, Toyama, Japan, May 22-24, 2013},
pages = {29--34},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ISMVL.2013.28},
doi = {10.1109/ISMVL.2013.28},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/WilleZD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/TagueSMD13,
author = {Laura Tague and
Mathias Soeken and
Shin{-}ichi Minato and
Rolf Drechsler},
title = {Debugging of Reversible Circuits Using pDDs},
booktitle = {43rd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2013, Toyama, Japan, May 22-24, 2013},
pages = {316--321},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ISMVL.2013.22},
doi = {10.1109/ISMVL.2013.22},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/TagueSMD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/AbdessaiedSWD13,
author = {Nabila Abdessaied and
Mathias Soeken and
Robert Wille and
Rolf Drechsler},
title = {Exact Template Matching Using Boolean Satisfiability},
booktitle = {43rd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2013, Toyama, Japan, May 22-24, 2013},
pages = {328--333},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ISMVL.2013.26},
doi = {10.1109/ISMVL.2013.26},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/AbdessaiedSWD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/StoppeWD13,
author = {Jannis Stoppe and
Robert Wille and
Rolf Drechsler},
title = {Data extraction from SystemC designs using debug symbols and the SystemC
{API}},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2013, Natal,
Brazil, August 5-7, 2013},
pages = {26--31},
publisher = {{IEEE} Computer Socity},
year = {2013},
url = {https://doi.org/10.1109/ISVLSI.2013.6654618},
doi = {10.1109/ISVLSI.2013.6654618},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/StoppeWD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/DrechslerDEW13,
author = {Rolf Drechsler and
Melanie Diepenbeck and
Stephan Eggersgl{\"{u}}{\ss} and
Robert Wille},
title = {{PASSAT} 2.0: {A} multi-functional SAT-based testing framework},
booktitle = {14th Latin American Test Workshop, {LATW} 2013, Cordoba, Argentina,
3-5 April, 2013},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/LATW.2013.6562675},
doi = {10.1109/LATW.2013.6562675},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/latw/DrechslerDEW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/SoekenWKD13,
author = {Mathias Soeken and
Robert Wille and
Eugen Kuksa and
Rolf Drechsler},
editor = {Christian Haubelt and
Dirk Timmermann},
title = {Generierung von OCL-Ausdr{\"{u}}cken aus nat{\"{u}}rlichsprachlichen
Beschreibungen},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Warnem{\"{u}}nde, Germany,
March 12-14, 2013},
pages = {99--103},
publisher = {Institut f{\"{u}}r Angewandte Mikroelektronik und Datentechnik,
Fakult{\"{a}}t f{\"{u}}r Informatik und Elektrotechnik,
Universit{\"{a}}t Rostock},
year = {2013},
timestamp = {Mon, 18 Mar 2013 20:33:43 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/SoekenWKD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/WilleD13,
author = {Robert Wille and
Rolf Drechsler},
title = {The SyReC hardware description language: Enabling scalable synthesis
of reversible circuits},
booktitle = {{IEEE} 56th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2013, Columbus, OH, USA, August 4-7, 2013},
pages = {1063--1066},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/MWSCAS.2013.6674836},
doi = {10.1109/MWSCAS.2013.6674836},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/WilleD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/NiemannWD13,
author = {Philipp Niemann and
Robert Wille and
Rolf Drechsler},
editor = {Gerhard W. Dueck and
D. Michael Miller},
title = {On the "Q" in QMDDs: Efficient Representation of Quantum
Functionality in the {QMDD} Data-Structure},
booktitle = {Reversible Computation - 5th International Conference, {RC} 2013,
Victoria, BC, Canada, July 4-5, 2013. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7948},
pages = {125--140},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-642-38986-3\_11},
doi = {10.1007/978-3-642-38986-3\_11},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rc/NiemannWD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/DebDRBWD13,
author = {Arighna Deb and
Debesh K. Das and
Hafizur Rahaman and
Bhargab B. Bhattacharya and
Robert Wille and
Rolf Drechsler},
editor = {Gerhard W. Dueck and
D. Michael Miller},
title = {Reversible Circuit Synthesis of Symmetric Functions Using a Simple
Regular Structure},
booktitle = {Reversible Computation - 5th International Conference, {RC} 2013,
Victoria, BC, Canada, July 4-5, 2013. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7948},
pages = {182--195},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-642-38986-3\_15},
doi = {10.1007/978-3-642-38986-3\_15},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/DebDRBWD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/DattaRWSRD13,
author = {Kamalika Datta and
Gaurav Rathi and
Robert Wille and
Indranil Sengupta and
Hafizur Rahaman and
Rolf Drechsler},
editor = {Gerhard W. Dueck and
D. Michael Miller},
title = {Exploiting Negative Control Lines in the Optimization of Reversible
Circuits},
booktitle = {Reversible Computation - 5th International Conference, {RC} 2013,
Victoria, BC, Canada, July 4-5, 2013. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7948},
pages = {209--220},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-642-38986-3\_17},
doi = {10.1007/978-3-642-38986-3\_17},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/DattaRWSRD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/AbdessaiedWSD13,
author = {Nabila Abdessaied and
Robert Wille and
Mathias Soeken and
Rolf Drechsler},
editor = {Gerhard W. Dueck and
D. Michael Miller},
title = {Reducing the Depth of Quantum Circuits Using Additional Circuit Lines},
booktitle = {Reversible Computation - 5th International Conference, {RC} 2013,
Victoria, BC, Canada, July 4-5, 2013. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7948},
pages = {221--233},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-642-38986-3\_18},
doi = {10.1007/978-3-642-38986-3\_18},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/AbdessaiedWSD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/SoekenMD13,
author = {Mathias Soeken and
D. Michael Miller and
Rolf Drechsler},
title = {On quantum circuits employing roots of the Pauli matrices},
journal = {CoRR},
volume = {abs/1308.2493},
year = {2013},
url = {http://arxiv.org/abs/1308.2493},
eprinttype = {arXiv},
eprint = {1308.2493},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/SoekenMD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0029051,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {High Quality Test Pattern Generation and Boolean Satisfiability},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-1-4419-9976-4},
doi = {10.1007/978-1-4419-9976-4},
isbn = {978-1-4419-9975-7},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0029051.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/EggersglussD12,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {A Highly Fault-Efficient SAT-Based {ATPG} Flow},
journal = {{IEEE} Des. Test Comput.},
volume = {29},
number = {4},
pages = {63--70},
year = {2012},
url = {https://doi.org/10.1109/MDT.2012.2205479},
doi = {10.1109/MDT.2012.2205479},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/EggersglussD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/DrechslerUW12,
author = {Rolf Drechsler and
Irek Ulidowski and
Robert Wille},
title = {Foreword: Special Issue on Reversible Computation},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {18},
number = {1},
pages = {1--3},
year = {2012},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-18-number-1-2012/mvlsc-18-1-p-1-3/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/DrechslerUW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/SoekenFWD12,
author = {Mathias Soeken and
Stefan Frehse and
Robert Wille and
Rolf Drechsler},
title = {RevKit: {A} Toolkit for Reversible Circuit Design},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {18},
number = {1},
pages = {55--65},
year = {2012},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-18-number-1-2012/mvlsc-18-1-p-55-65/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/SoekenFWD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/MillerWD12,
author = {D. Michael Miller and
Robert Wille and
Rolf Drechsler},
title = {Reducing Reversible Circuit Cost by Adding Lines},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {19},
number = {1-3},
pages = {185--201},
year = {2012},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-19-number-1-3-2012/mvlsc-19-1-3-p-185-201/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/MillerWD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/WilleGMD12,
author = {Robert Wille and
Daniel Gro{\ss}e and
D. Michael Miller and
Rolf Drechsler},
title = {Equivalence Checking of Reversible Circuits},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {19},
number = {4},
pages = {361--378},
year = {2012},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-19-number-4-2012/mvlsc-19-4-p-361-378/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/WilleGMD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeGD12,
author = {Hoang Minh Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Automatic {TLM} Fault Localization for SystemC},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1249--1262},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2188800},
doi = {10.1109/TCAD.2012.2188800},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeGD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SoekenWHPD12,
author = {Mathias Soeken and
Robert Wille and
Christoph Hilken and
Nils Przigoda and
Rolf Drechsler},
title = {Synthesis of reversible circuits with minimal lines for large functions},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {85--92},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6165069},
doi = {10.1109/ASPDAC.2012.6165069},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/SoekenWHPD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/OliveiraKLGH0DEE12,
author = {Marcio F. da S. Oliveira and
Christoph Kuznik and
Hoang Minh Le and
Daniel Gro{\ss}e and
Finn Haedicke and
Wolfgang M{\"{u}}ller and
Rolf Drechsler and
Wolfgang Ecker and
Volkan Esen},
editor = {Ahmed Jerraya and
Luca P. Carloni and
Naehyuck Chang and
Franco Fummi},
title = {The system verification methodology for advanced {TLM} verification},
booktitle = {Proceedings of the 10th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2012, part of ESWeek '12
Eighth Embedded Systems Week, Tampere, Finland, October 7-12, 2012},
pages = {313--322},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2380445.2380497},
doi = {10.1145/2380445.2380497},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/codes/OliveiraKLGH0DEE12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HaedickeGD12,
author = {Finn Haedicke and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {A guiding coverage metric for formal verification},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {617--622},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176546},
doi = {10.1109/DATE.2012.6176546},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/HaedickeGD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WilleDOO12,
author = {Robert Wille and
Rolf Drechsler and
Christof Osewold and
Alberto Garc{\'{\i}}a Ortiz},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {Automatic design of low-power encoders using reversible circuit synthesis},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {1036--1041},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176648},
doi = {10.1109/DATE.2012.6176648},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/WilleDOO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WilleSD12,
author = {Robert Wille and
Mathias Soeken and
Rolf Drechsler},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {Debugging of inconsistent {UML/OCL} models},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {1078--1083},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176655},
doi = {10.1109/DATE.2012.6176655},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/WilleSD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SoekenWD12,
author = {Mathias Soeken and
Robert Wille and
Rolf Drechsler},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {Eliminating invariants in {UML/OCL} models},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {1142--1145},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176669},
doi = {10.1109/DATE.2012.6176669},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/SoekenWD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/EggersglussKGHD12,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Rene Krenz{-}Baath and
Andreas Glowatz and
Friedrich Hapke and
Rolf Drechsler},
editor = {Jaan Raik and
Viera Stopjakov{\'{a}} and
Heinrich Theodor Vierhaus and
Witold A. Pleskacz and
Raimund Ubar and
Helena Kruus and
Maksim Jenihhin},
title = {A new SAT-based {ATPG} for generating highly compacted test sets},
booktitle = {{IEEE} 15th International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2012, Tallinn, Estonia, April 18-20,
2012},
pages = {230--235},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DDECS.2012.6219063},
doi = {10.1109/DDECS.2012.6219063},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/EggersglussKGHD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/YangWGD12,
author = {Shuo Yang and
Robert Wille and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Coverage-Driven Stimuli Generation},
booktitle = {15th Euromicro Conference on Digital System Design, {DSD} 2012, Cesme,
Izmir, Turkey, September 5-8, 2012},
pages = {525--528},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/DSD.2012.37},
doi = {10.1109/DSD.2012.37},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/YangWGD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/DrechslerSW12a,
author = {Rolf Drechsler and
Mathias Soeken and
Robert Wille},
editor = {Jan Haase},
title = {Formal Specification Level},
booktitle = {Models, Methods, and Tools for Complex Chip Design - Selected Contributions
from {FDL} 2012},
series = {Lecture Notes in Electrical Engineering},
volume = {265},
pages = {37--52},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-319-01418-0\_3},
doi = {10.1007/978-3-319-01418-0\_3},
timestamp = {Sun, 02 Oct 2022 16:01:15 +0200},
biburl = {https://dblp.org/rec/conf/fdl/DrechslerSW12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/DrechslerSW12,
author = {Rolf Drechsler and
Mathias Soeken and
Robert Wille},
title = {Formal Specification Level: Towards verification-driven design based
on natural language processing},
booktitle = {Proceeding of the 2012 Forum on Specification and Design Languages,
Vienna, Austria, September 18-20, 2012},
pages = {53--58},
publisher = {{IEEE}},
year = {2012},
url = {https://ieeexplore.ieee.org/document/6336984/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/DrechslerSW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/MichaelGD12,
author = {Marc Michael and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Localizing features of {ESL} models for design understanding},
booktitle = {Proceeding of the 2012 Forum on Specification and Design Languages,
Vienna, Austria, September 18-20, 2012},
pages = {120--125},
publisher = {{IEEE}},
year = {2012},
url = {https://ieeexplore.ieee.org/document/6336996/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/MichaelGD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/FrehseFAYD12,
author = {Stefan Frehse and
G{\"{o}}rschwin Fey and
Eli Arbel and
Karen Yorav and
Rolf Drechsler},
editor = {Gianpiero Cabodi and
Satnam Singh},
title = {Complete and effective robustness checking by means of interpolation},
booktitle = {Formal Methods in Computer-Aided Design, {FMCAD} 2012, Cambridge,
UK, October 22-25, 2012},
pages = {82--90},
publisher = {{IEEE}},
year = {2012},
url = {https://ieeexplore.ieee.org/document/6462559/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fmcad/FrehseFAYD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gg/DrechslerDGKLSSW12,
author = {Rolf Drechsler and
Melanie Diepenbeck and
Daniel Gro{\ss}e and
Ulrich K{\"{u}}hne and
Hoang Minh Le and
Julia Seiter and
Mathias Soeken and
Robert Wille},
editor = {Hartmut Ehrig and
Gregor Engels and
Hans{-}J{\"{o}}rg Kreowski and
Grzegorz Rozenberg},
title = {Completeness-Driven Development},
booktitle = {Graph Transformations - 6th International Conference, {ICGT} 2012,
Bremen, Germany, September 24-29, 2012. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7562},
pages = {38--50},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-33654-6\_3},
doi = {10.1007/978-3-642-33654-6\_3},
timestamp = {Tue, 15 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/gg/DrechslerDGKLSSW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/DiepenbeckSGD12,
author = {Melanie Diepenbeck and
Mathias Soeken and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Behavior Driven Development for circuit design and verification},
booktitle = {2012 {IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2012, Huntington Beach, CA, USA, November 9-10, 2012},
pages = {9--16},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/HLDVT.2012.6418237},
doi = {10.1109/HLDVT.2012.6418237},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/DiepenbeckSGD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/DrechslerHW12,
author = {Rolf Drechsler and
Ian G. Harris and
Robert Wille},
title = {Generating formal system models from natural language descriptions},
booktitle = {2012 {IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2012, Huntington Beach, CA, USA, November 9-10, 2012},
pages = {164--165},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/HLDVT.2012.6418259},
doi = {10.1109/HLDVT.2012.6418259},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/DrechslerHW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hvc/BloemDFFHKRRS12,
author = {Roderick Bloem and
Rolf Drechsler and
G{\"{o}}rschwin Fey and
Alexander Finder and
Georg Hofferek and
Robert K{\"{o}}nighofer and
Jaan Raik and
Urmas Repinski and
Andr{\'{e}} S{\"{u}}lflow},
editor = {Armin Biere and
Amir Nahir and
Tanja E. J. Vos},
title = {FoREnSiC- An Automatic Debugging Environment for {C} Programs},
booktitle = {Hardware and Software: Verification and Testing - 8th International
Haifa Verification Conference, {HVC} 2012, Haifa, Israel, November
6-8, 2012. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {7857},
pages = {260--265},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-39611-3\_24},
doi = {10.1007/978-3-642-39611-3\_24},
timestamp = {Tue, 14 May 2019 10:00:42 +0200},
biburl = {https://dblp.org/rec/conf/hvc/BloemDFFHKRRS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/DrechslerW12,
author = {Rolf Drechsler and
Robert Wille},
title = {Synthesis of Reversible Circuits Using Decision Diagrams},
booktitle = {International Symposium on Electronic System Design, ISEDs 2012, Kolkata,
India, December 19-22, 2012},
pages = {1--5},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISED.2012.37},
doi = {10.1109/ISED.2012.37},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/ised/DrechslerW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/LeGD12,
author = {Hoang M. Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {From Requirements and Scenarios to {ESL} Design in SystemC},
booktitle = {International Symposium on Electronic System Design, ISEDs 2012, Kolkata,
India, December 19-22, 2012},
pages = {183--187},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISED.2012.36},
doi = {10.1109/ISED.2012.36},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ised/LeGD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/WilleSPD12,
author = {Robert Wille and
Mathias Soeken and
Nils Przigoda and
Rolf Drechsler},
editor = {D. Michael Miller and
Vincent C. Gaudet},
title = {Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines},
booktitle = {42nd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2012, Victoria, BC, Canada, May 14-16, 2012},
pages = {69--74},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISMVL.2012.71},
doi = {10.1109/ISMVL.2012.71},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/WilleSPD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/SoekenSWMD12,
author = {Mathias Soeken and
Zahra Sasanian and
Robert Wille and
D. Michael Miller and
Rolf Drechsler},
editor = {D. Michael Miller and
Vincent C. Gaudet},
title = {Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum
Gate Circuits},
booktitle = {42nd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2012, Victoria, BC, Canada, May 14-16, 2012},
pages = {173--178},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISMVL.2012.64},
doi = {10.1109/ISMVL.2012.64},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/SoekenSWMD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/SoekenWOD12,
author = {Mathias Soeken and
Robert Wille and
Christian Otterstedt and
Rolf Drechsler},
editor = {D. Michael Miller and
Vincent C. Gaudet},
title = {A Synthesis Flow for Sequential Reversible Circuits},
booktitle = {42nd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2012, Victoria, BC, Canada, May 14-16, 2012},
pages = {299--304},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISMVL.2012.72},
doi = {10.1109/ISMVL.2012.72},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/SoekenWOD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/issoc/HaedickeLGD12,
author = {Finn Haedicke and
Hoang Minh Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {{CRAVE:} An advanced constrained random verification environment for
SystemC},
booktitle = {2012 International Symposium on System on Chip, ISSoC 2012, Tampere,
Finland, October 10-12, 2012},
pages = {1--7},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSoC.2012.6376356},
doi = {10.1109/ISSOC.2012.6376356},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/issoc/HaedickeLGD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/WilleSSD12,
author = {Robert Wille and
Mathias Soeken and
Eleonora Sch{\"{o}}nborn and
Rolf Drechsler},
title = {Circuit Line Minimization in the HDL-Based Synthesis of Reversible
Logic},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2012, Amherst,
MA, USA, August 19-21, 2012},
pages = {213--218},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISVLSI.2012.43},
doi = {10.1109/ISVLSI.2012.43},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/WilleSSD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/HaedickeLGD12,
author = {Finn Haedicke and
Hoang Minh Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Jens Brandt and
Klaus Schneider},
title = {{CRAVE:} An Advanced Constrained RAndom Verification Environment for
SystemC},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, March
5-7, 2012},
series = {Forschungsergebnisse zur Informatik},
volume = {68},
pages = {37--48},
publisher = {Verlag Dr. Kovac},
year = {2012},
timestamp = {Tue, 19 May 2020 12:57:43 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/HaedickeLGD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/SeiterSWD12,
author = {Julia Seiter and
Mathias Soeken and
Robert Wille and
Rolf Drechsler},
editor = {Robert Gl{\"{u}}ck and
Tetsuo Yokoyama},
title = {Property Checking of Quantum Circuits Using Quantum Multiple-Valued
Decision Diagrams},
booktitle = {Reversible Computation, 4th International Workshop, {RC} 2012, Copenhagen,
Denmark, July 2-3, 2012. Revised Papers},
series = {Lecture Notes in Computer Science},
volume = {7581},
pages = {183--196},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-36315-3\_15},
doi = {10.1007/978-3-642-36315-3\_15},
timestamp = {Tue, 15 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/SeiterSWD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/SoekenWMD12,
author = {Mathias Soeken and
Robert Wille and
Shin{-}ichi Minato and
Rolf Drechsler},
editor = {Robert Gl{\"{u}}ck and
Tetsuo Yokoyama},
title = {Using \emph{{\(\pi\)}}DDs in the Design of Reversible Circuits},
booktitle = {Reversible Computation, 4th International Workshop, {RC} 2012, Copenhagen,
Denmark, July 2-3, 2012. Revised Papers},
series = {Lecture Notes in Computer Science},
volume = {7581},
pages = {197--203},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-36315-3\_16},
doi = {10.1007/978-3-642-36315-3\_16},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/SoekenWMD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tools/SoekenWD12,
author = {Mathias Soeken and
Robert Wille and
Rolf Drechsler},
editor = {Carlo A. Furia and
Sebastian Nanz},
title = {Assisted Behavior Driven Development Using Natural Language Processing},
booktitle = {Objects, Models, Components, Patterns - 50th International Conference,
{TOOLS} 2012, Prague, Czech Republic, May 29-31, 2012. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7304},
pages = {269--287},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-30561-0\_19},
doi = {10.1007/978-3-642-30561-0\_19},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/tools/SoekenWD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DrechslerW12,
author = {Rolf Drechsler and
Robert Wille},
editor = {Hafizur Rahaman and
Sanatan Chattopadhyay and
Santanu Chattopadhyay},
title = {Reversible Circuits: Recent Accomplishments and Future Challenges
for an Emerging Technology - (Invited Paper)},
booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
{VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7373},
pages = {383--392},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-31494-0\_53},
doi = {10.1007/978-3-642-31494-0\_53},
timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
biburl = {https://dblp.org/rec/conf/vdat/DrechslerW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/evoW/2012a,
editor = {Cecilia Di Chio and
Alexandros Agapitos and
Stefano Cagnoni and
Carlos Cotta and
Francisco Fern{\'{a}}ndez de Vega and
Gianni A. Di Caro and
Rolf Drechsler and
Anik{\'{o}} Ek{\'{a}}rt and
Anna Isabel Esparcia{-}Alc{\'{a}}zar and
Muddassar Farooq and
William B. Langdon and
Juan Juli{\'{a}}n Merelo Guerv{\'{o}}s and
Mike Preuss and
Hendrik Richter and
Sara Silva and
Anabela Sim{\~{o}}es and
Giovanni Squillero and
Ernesto Tarantino and
Andrea Tettamanzi and
Julian Togelius and
Neil Urquhart and
Sima Uyar and
Georgios N. Yannakakis},
title = {Applications of Evolutionary Computation - EvoApplications 2012: EvoCOMNET,
EvoCOMPLEX, EvoFIN, EvoGAMES, EvoHOT, EvoIASP, EvoNUM, EvoPAR, EvoRISK,
EvoSTIM, and EvoSTOC, M{\'{a}}laga, Spain, April 11-13, 2012,
Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7248},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-29178-4},
doi = {10.1007/978-3-642-29178-4},
isbn = {978-3-642-29177-7},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/evoW/2012a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WilleGFDD11,
author = {Robert Wille and
Daniel Gro{\ss}e and
Stefan Frehse and
Gerhard W. Dueck and
Rolf Drechsler},
title = {Debugging reversible circuits},
journal = {Integr.},
volume = {44},
number = {1},
pages = {51--61},
year = {2011},
url = {https://doi.org/10.1016/j.vlsi.2010.08.002},
doi = {10.1016/J.VLSI.2010.08.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WilleGFDD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/qip/SaeediWD11,
author = {Mehdi Saeedi and
Robert Wille and
Rolf Drechsler},
title = {Synthesis of quantum circuits for linear nearest neighbor architectures},
journal = {Quantum Inf. Process.},
volume = {10},
number = {3},
pages = {355--377},
year = {2011},
url = {https://doi.org/10.1007/s11128-010-0201-2},
doi = {10.1007/S11128-010-0201-2},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/qip/SaeediWD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FeySFD11,
author = {G{\"{o}}rschwin Fey and
Andr{\'{e}} S{\"{u}}lflow and
Stefan Frehse and
Rolf Drechsler},
title = {Effective Robustness Analysis Using Bounded Model Checking Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1239--1252},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2120950},
doi = {10.1109/TCAD.2011.2120950},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FeySFD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EggersglussD11,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {Efficient Data Structures and Methodologies for SAT-Based {ATPG} Providing
High Fault Coverage in Industrial Application},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1411--1415},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2152450},
doi = {10.1109/TCAD.2011.2152450},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EggersglussD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/africon/ZhangFWD11,
author = {Hongyan Zhang and
Stefan Frehse and
Robert Wille and
Rolf Drechsler},
title = {Determining minimal testsets for reversible circuits using Boolean
satisfiability},
booktitle = {{AFRICON} 2011, Victoria Falls, Livingstone, Zambia, September 13-15,
2011},
pages = {1--6},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/AFRCON.2011.6072128},
doi = {10.1109/AFRCON.2011.6072128},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/africon/ZhangFWD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/ZhangWD11,
author = {Hongyan Zhang and
Robert Wille and
Rolf Drechsler},
title = {Improved Fault Diagnosis for Reversible Circuits},
booktitle = {Proceedings of the 20th {IEEE} Asian Test Symposium, {ATS} 2011, New
Delhi, India, November 20-23, 2011},
pages = {207--212},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ATS.2011.29},
doi = {10.1109/ATS.2011.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/ZhangWD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SoekenWD11,
author = {Mathias Soeken and
Robert Wille and
Rolf Drechsler},
title = {Verifying dynamic aspects of {UML} models},
booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
March 14-18, 2011},
pages = {1077--1082},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/DATE.2011.5763177},
doi = {10.1109/DATE.2011.5763177},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/SoekenWD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WilleKD11,
author = {Robert Wille and
Oliver Kesz{\"{o}}cze and
Rolf Drechsler},
title = {Determining the minimal number of lines for large reversible circuits},
booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
March 14-18, 2011},
pages = {1204--1207},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/DATE.2011.5763314},
doi = {10.1109/DATE.2011.5763314},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/WilleKD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/EggersglusD11,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {As-Robust-As-Possible test generation in the presence of small delay
defects using pseudo-Boolean optimization},
booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
March 14-18, 2011},
pages = {1291--1296},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/DATE.2011.5763207},
doi = {10.1109/DATE.2011.5763207},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/EggersglusD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/SoekenKFFD11,
author = {Mathias Soeken and
Ulrich K{\"{u}}hne and
Martin Freibothe and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
editor = {Rolf Kraemer and
Adam Pawlak and
Andreas Steininger and
Mario Sch{\"{o}}lzel and
Jaan Raik and
Heinrich Theodor Vierhaus},
title = {Automatic property generation for the formal verification of bus bridges},
booktitle = {14th {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2011, Cottbus, Germany, April 13-15,
2011},
pages = {417--422},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/DDECS.2011.5783129},
doi = {10.1109/DDECS.2011.5783129},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/SoekenKFFD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/BawadekjiGD11,
author = {Mohamed Bawadekji and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Rolf Kraemer and
Adam Pawlak and
Andreas Steininger and
Mario Sch{\"{o}}lzel and
Jaan Raik and
Heinrich Theodor Vierhaus},
title = {{TLM} protocol compliance checking at the Electronic System Level},
booktitle = {14th {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2011, Cottbus, Germany, April 13-15,
2011},
pages = {435--440},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/DDECS.2011.5783132},
doi = {10.1109/DDECS.2011.5783132},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/BawadekjiGD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/evoW/DrechslerFW11,
author = {Rolf Drechsler and
Alexander Finder and
Robert Wille},
editor = {Cecilia Di Chio and
Anthony Brabazon and
Gianni A. Di Caro and
Rolf Drechsler and
Muddassar Farooq and
J{\"{o}}rn Grahl and
Gary Greenfield and
Christian Prins and
Juan Romero and
Giovanni Squillero and
Ernesto Tarantino and
Andrea Tettamanzi and
Neil Urquhart and
A. Sima Etaner{-}Uyar},
title = {Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary
Algorithms},
booktitle = {Applications of Evolutionary Computation - EvoApplications 2011: EvoCOMNET,
EvoFIN, EvoHOT, EvoMUSART, EvoSTIM, and EvoTRANSLOG, Torino, Italy,
April 27-29, 2011, Proceedings, Part {II}},
series = {Lecture Notes in Computer Science},
volume = {6625},
pages = {151--161},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-20520-0\_16},
doi = {10.1007/978-3-642-20520-0\_16},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/evoW/DrechslerFW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/MichaelGD11,
author = {Marc Michael and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Analyzing dependability measures at the Electronic System Level},
booktitle = {2011 Forum on Specification {\&} Design Languages, {FDL} 2011,
Oldenburg, Germany, September 13-15, 2011},
pages = {1--8},
publisher = {{IEEE}},
year = {2011},
url = {https://ieeexplore.ieee.org/document/6069490/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/MichaelGD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/OffermannWD11,
author = {Sebastian Offermann and
Robert Wille and
Rolf Drechsler},
title = {Efficient realization of control logic in reversible circuits},
booktitle = {2011 Forum on Specification {\&} Design Languages, {FDL} 2011,
Oldenburg, Germany, September 13-15, 2011},
pages = {1--7},
publisher = {{IEEE}},
year = {2011},
url = {https://ieeexplore.ieee.org/document/6069484/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/OffermannWD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fmcad/HaedickeFFGD11,
author = {Finn Haedicke and
Stefan Frehse and
G{\"{o}}rschwin Fey and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Malay K. Ganai and
Armin Biere},
title = {metaSMT: Focus on Your Application not on Solver Integration},
booktitle = {Proceedings of the First International Workshop on Design and Implementation
of Formal Tools and Systems, Austin, USA, November 3, 2011},
series = {{CEUR} Workshop Proceedings},
volume = {832},
publisher = {CEUR-WS.org},
year = {2011},
url = {https://ceur-ws.org/Vol-832/paper\_5.pdf},
timestamp = {Fri, 10 Mar 2023 16:22:13 +0100},
biburl = {https://dblp.org/rec/conf/fmcad/HaedickeFFGD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GrosseGKD11,
author = {Daniel Gro{\ss}e and
Markus Gro{\ss} and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
editor = {David Atienza and
Yuan Xie and
Jos{\'{e}} L. Ayala and
Ken S. Stevens},
title = {Simulation-based equivalence checking between SystemC models at different
levels of abstraction},
booktitle = {Proceedings of the 21st {ACM} Great Lakes Symposium on {VLSI} 2010,
Lausanne, Switzerland, May 2-6, 2011},
pages = {223--228},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1973009.1973054},
doi = {10.1145/1973009.1973054},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/GrosseGKD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/DrechslerW11,
author = {Rolf Drechsler and
Robert Wille},
editor = {Jaakko Astola and
Radomir S. Stankovic},
title = {From Truth Tables to Programming Languages: Progress in the Design
of Reversible Circuits},
booktitle = {41st {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2011, Tuusula, Finland, May 23-25, 2011},
pages = {78--85},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISMVL.2011.40},
doi = {10.1109/ISMVL.2011.40},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/DrechslerW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/WilleSGSD11,
author = {Robert Wille and
Mathias Soeken and
Daniel Gro{\ss}e and
Eleonora Sch{\"{o}}nborn and
Rolf Drechsler},
editor = {Jaakko Astola and
Radomir S. Stankovic},
title = {Designing a {RISC} {CPU} in Reversible Logic},
booktitle = {41st {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2011, Tuusula, Finland, May 23-25, 2011},
pages = {170--175},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISMVL.2011.39},
doi = {10.1109/ISMVL.2011.39},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/WilleSGSD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isorc/GruttnerHKGRND11,
author = {Kim Gr{\"{u}}ttner and
Andreas Herrholz and
Ulrich K{\"{u}}hne and
Daniel Gro{\ss}e and
Achim Rettberg and
Wolfgang Nebel and
Rolf Drechsler},
title = {Towards Dependability-Aware Design of Hardware Systems Using Extended
Program State Machines},
booktitle = {14th {IEEE} International Symposium on Object/Component/Service-Oriented
Real-Time Distributed Computing Workshops, {ISORC} Workshops 2011,
Newport Beach, CA, USA, March 28-31, 2011},
pages = {181--188},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISORCW.2011.27},
doi = {10.1109/ISORCW.2011.27},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isorc/GruttnerHKGRND11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/WilleZD11,
author = {Robert Wille and
Hongyan Zhang and
Rolf Drechsler},
title = {{ATPG} for Reversible Circuits Using Simulation, Boolean Satisfiability,
and Pseudo Boolean Optimization},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2011, 4-6
July 2011, Chennai, India},
pages = {120--125},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISVLSI.2011.77},
doi = {10.1109/ISVLSI.2011.77},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/WilleZD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/SoekenKFFD11,
author = {Mathias Soeken and
Ulrich K{\"{u}}hne and
Martin Freibothe and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
editor = {Frank Oppenheimer},
title = {Towards Automatic Property Generation for the Formal Verification
of Bus Bridges},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Oldenburg, Germany, February
21-23, 2011},
pages = {183--192},
publisher = {OFFIS-Institut f{\"{u}}r Informatik},
year = {2011},
timestamp = {Wed, 27 Jun 2012 22:40:36 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/SoekenKFFD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/WilleSGSD11,
author = {Robert Wille and
Mathias Soeken and
Daniel Gro{\ss}e and
Eleonora Sch{\"{o}}nborn and
Rolf Drechsler},
editor = {Frank Oppenheimer},
title = {Designing a {RISC} {CPU} in Reversible Logic},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Oldenburg, Germany, February
21-23, 2011},
pages = {249--258},
publisher = {OFFIS-Institut f{\"{u}}r Informatik},
year = {2011},
timestamp = {Wed, 27 Jun 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/WilleSGSD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/GrosseGKD11,
author = {Daniel Gro{\ss}e and
Markus Gro{\ss} and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
editor = {Frank Oppenheimer},
title = {Simulation-based Equivalence Checking between SystemC Models at Different
Levels of Abstraction},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Oldenburg, Germany, February
21-23, 2011},
pages = {269--278},
publisher = {OFFIS-Institut f{\"{u}}r Informatik},
year = {2011},
timestamp = {Wed, 27 Jun 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/GrosseGKD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/models/SoekenWD11,
author = {Mathias Soeken and
Robert Wille and
Rolf Drechsler},
editor = {Stephan Wei{\ss}leder and
Levi L{\'{u}}cio and
Harald Cichos and
Fr{\'{e}}d{\'{e}}ric Fondement},
title = {Towards automatic determination of problem bounds for object instantiation
in static model verification},
booktitle = {Proceedings of the 8th International Workshop on Model-Driven Engineering,
Verification and Validation, MoDeVVa, Wellington, New Zealand, October
17, 2011},
pages = {2:1--2:4},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2095654.2095657},
doi = {10.1145/2095654.2095657},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/models/SoekenWD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/SoekenFWD11,
author = {Mathias Soeken and
Stefan Frehse and
Robert Wille and
Rolf Drechsler},
editor = {Alexis De Vos and
Robert Wille},
title = {RevKit: An Open Source Toolkit for the Design of Reversible Circuits},
booktitle = {Reversible Computation - Third International Workshop, {RC} 2011,
Gent, Belgium, July 4-5, 2011. Revised Papers},
series = {Lecture Notes in Computer Science},
volume = {7165},
pages = {64--76},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-29517-1\_6},
doi = {10.1007/978-3-642-29517-1\_6},
timestamp = {Sun, 02 Jun 2019 21:17:32 +0200},
biburl = {https://dblp.org/rec/conf/rc/SoekenFWD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tap/SoekenWD11,
author = {Mathias Soeken and
Robert Wille and
Rolf Drechsler},
editor = {Martin Gogolla and
Burkhart Wolff},
title = {Encoding {OCL} Data Types for SAT-Based Verification of {UML/OCL}
Models},
booktitle = {Tests and Proofs - 5th International Conference, TAP@TOOLS 2011, Zurich,
Switzerland, June 30 - July 1, 2011. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {6706},
pages = {152--170},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-21768-5\_12},
doi = {10.1007/978-3-642-21768-5\_12},
timestamp = {Tue, 23 Jun 2020 17:37:39 +0200},
biburl = {https://dblp.org/rec/conf/tap/SoekenWD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/evoW/2011a2,
editor = {Cecilia Di Chio and
Anthony Brabazon and
Gianni A. Di Caro and
Rolf Drechsler and
Muddassar Farooq and
J{\"{o}}rn Grahl and
Gary Greenfield and
Christian Prins and
Juan Romero and
Giovanni Squillero and
Ernesto Tarantino and
Andrea Tettamanzi and
Neil Urquhart and
A. Sima Etaner{-}Uyar},
title = {Applications of Evolutionary Computation - EvoApplications 2011: EvoCOMNET,
EvoFIN, EvoHOT, EvoMUSART, EvoSTIM, and EvoTRANSLOG, Torino, Italy,
April 27-29, 2011, Proceedings, Part {II}},
series = {Lecture Notes in Computer Science},
volume = {6625},
publisher = {Springer},
year = {2011},
url = {https://doi.org/10.1007/978-3-642-20520-0},
doi = {10.1007/978-3-642-20520-0},
isbn = {978-3-642-20519-4},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/evoW/2011a2.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/SaeediWD11,
author = {Mehdi Saeedi and
Robert Wille and
Rolf Drechsler},
title = {Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures},
journal = {CoRR},
volume = {abs/1110.6412},
year = {2011},
url = {http://arxiv.org/abs/1110.6412},
eprinttype = {arXiv},
eprint = {1110.6412},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/SaeediWD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0025733,
author = {Robert Wille and
Rolf Drechsler},
title = {Towards a Design Flow for Reversible Logic},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-90-481-9579-4},
doi = {10.1007/978-90-481-9579-4},
isbn = {978-90-481-9578-7},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0025733.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0024866,
author = {Frank Rogin and
Rolf Drechsler},
title = {Debugging at the Electronic System Level},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-90-481-9255-7},
doi = {10.1007/978-90-481-9255-7},
isbn = {978-90-481-9254-0},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0024866.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/sp/Grosse10,
author = {Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Quality-Driven SystemC Design},
publisher = {Springer},
year = {2010},
url = {http://www.springerlink.com/content/978-90-481-3631-5},
isbn = {978-90-481-3630-8},
timestamp = {Tue, 25 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/books/sp/Grosse10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/KuhneGD10,
author = {Ulrich K{\"{u}}hne and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Towards Fully Automatic Synthesis of Embedded Software},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {2},
number = {3},
pages = {53--57},
year = {2010},
url = {https://doi.org/10.1109/LES.2010.2049983},
doi = {10.1109/LES.2010.2049983},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/KuhneGD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/EggersglussFGHSD10,
author = {Stephan Eggersgl{\"{u}}{\ss} and
G{\"{o}}rschwin Fey and
Andreas Glowatz and
Friedrich Hapke and
J{\"{u}}rgen Schl{\"{o}}ffel and
Rolf Drechsler},
title = {{MONSOON:} SAT-Based {ATPG} for Path Delay Faults Using Multiple-Valued
Logics},
journal = {J. Electron. Test.},
volume = {26},
number = {3},
pages = {307--322},
year = {2010},
url = {https://doi.org/10.1007/s10836-010-5146-y},
doi = {10.1007/S10836-010-5146-Y},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/EggersglussFGHSD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijamc-igi/WilleD10,
author = {Robert Wille and
Rolf Drechsler},
title = {BDD-Based Synthesis of Reversible Logic},
journal = {Int. J. Appl. Metaheuristic Comput.},
volume = {1},
number = {4},
pages = {25--41},
year = {2010},
url = {https://doi.org/10.4018/jamc.2010100102},
doi = {10.4018/JAMC.2010100102},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijamc-igi/WilleD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/it/WilleD10,
author = {Robert Wille and
Rolf Drechsler},
title = {Synthese reversibler Logik (Synthesizing Reversible Logic)},
journal = {it Inf. Technol.},
volume = {52},
number = {1},
pages = {30--38},
year = {2010},
url = {https://doi.org/10.1524/itit.2010.0568},
doi = {10.1524/ITIT.2010.0568},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/it/WilleD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/it/FeySFD10,
author = {G{\"{o}}rschwin Fey and
Andr{\'{e}} S{\"{u}}lflow and
Stefan Frehse and
Rolf Drechsler},
title = {Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen
(Automated Formal Verification of Fault Tolerance for Circuits)},
journal = {it Inf. Technol.},
volume = {52},
number = {4},
pages = {216--223},
year = {2010},
url = {https://doi.org/10.1524/itit.2010.0594},
doi = {10.1524/ITIT.2010.0594},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/it/FeySFD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TilleED10,
author = {Daniel Tille and
Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {Incremental Solving Techniques for SAT-based {ATPG}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1125--1130},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2044673},
doi = {10.1109/TCAD.2010.2044673},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TilleED10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WilleSD10,
author = {Robert Wille and
Mathias Soeken and
Rolf Drechsler},
editor = {Sachin S. Sapatnekar},
title = {Reducing the number of lines in reversible circuits},
booktitle = {Proceedings of the 47th Design Automation Conference, {DAC} 2010,
Anaheim, California, USA, July 13-18, 2010},
pages = {647--652},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1837274.1837439},
doi = {10.1145/1837274.1837439},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/WilleSD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SoekenWKGD10,
author = {Mathias Soeken and
Robert Wille and
Mirco Kuhlmann and
Martin Gogolla and
Rolf Drechsler},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {Verifying {UML/OCL} models using Boolean satisfiability},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {1341--1344},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5457017},
doi = {10.1109/DATE.2010.5457017},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/SoekenWKGD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/DrechslerF10,
author = {Rolf Drechsler and
G{\"{o}}rschwin Fey},
editor = {Elena Gramatov{\'{a}} and
Zdenek Kot{\'{a}}sek and
Andreas Steininger and
Heinrich Theodor Vierhaus and
Horst Zimmermann},
title = {Formal verification meets robustness checking - Techniques and challenges},
booktitle = {13th {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, {DDECS} 2010, Vienna, Austria, April 14-16,
2010},
pages = {4},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DDECS.2010.5491833},
doi = {10.1109/DDECS.2010.5491833},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/DrechslerF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/FrehseFD10,
author = {Stefan Frehse and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
editor = {Elena Gramatov{\'{a}} and
Zdenek Kot{\'{a}}sek and
Andreas Steininger and
Heinrich Theodor Vierhaus and
Horst Zimmermann},
title = {A better-than-worst-case robustness measure},
booktitle = {13th {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, {DDECS} 2010, Vienna, Austria, April 14-16,
2010},
pages = {78--83},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DDECS.2010.5491812},
doi = {10.1109/DDECS.2010.5491812},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/FrehseFD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/OffermannWDD10,
author = {Sebastian Offermann and
Robert Wille and
Gerhard W. Dueck and
Rolf Drechsler},
editor = {Elena Gramatov{\'{a}} and
Zdenek Kot{\'{a}}sek and
Andreas Steininger and
Heinrich Theodor Vierhaus and
Horst Zimmermann},
title = {Synthesizing multiplier in reversible logic},
booktitle = {13th {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, {DDECS} 2010, Vienna, Austria, April 14-16,
2010},
pages = {335--340},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DDECS.2010.5491757},
doi = {10.1109/DDECS.2010.5491757},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/OffermannWDD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/SoekenWDD10,
author = {Mathias Soeken and
Robert Wille and
Gerhard W. Dueck and
Rolf Drechsler},
editor = {Elena Gramatov{\'{a}} and
Zdenek Kot{\'{a}}sek and
Andreas Steininger and
Heinrich Theodor Vierhaus and
Horst Zimmermann},
title = {Window optimization of reversible and quantum circuits},
booktitle = {13th {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits and Systems, {DDECS} 2010, Vienna, Austria, April 14-16,
2010},
pages = {341--345},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DDECS.2010.5491754},
doi = {10.1109/DDECS.2010.5491754},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/SoekenWDD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/FrehseFSD10,
author = {Stefan Frehse and
G{\"{o}}rschwin Fey and
Andr{\'{e}} S{\"{u}}lflow and
Rolf Drechsler},
editor = {Sebasti{\'{a}}n L{\'{o}}pez},
title = {RobuCheck: {A} Robustness Checker for Digital Circuits},
booktitle = {13th Euromicro Conference on Digital System Design, Architectures,
Methods and Tools, {DSD} 2010, 1-3 September 2010, Lille, France},
pages = {226--231},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DSD.2010.91},
doi = {10.1109/DSD.2010.91},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/FrehseFSD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/edcc/FrehseFSD10,
author = {Stefan Frehse and
G{\"{o}}rschwin Fey and
Andr{\'{e}} S{\"{u}}lflow and
Rolf Drechsler},
editor = {Arndt Bode},
title = {RobuCheck: a robustness checker for digital circuits},
booktitle = {Proceedings of the First Workshop on DYnamic Aspects in DEpendability
Models for Fault-Tolerant Systems, {DYADEM-FTS} '10, Valencia, Spain,
April 27, 2010},
pages = {37--38},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1772630.1772641},
doi = {10.1145/1772630.1772641},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/edcc/FrehseFSD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/TilleEKSD10,
author = {Daniel Tille and
Stephan Eggersgl{\"{u}}{\ss} and
Rene Krenz{-}Baath and
J{\"{u}}rgen Schl{\"{o}}ffel and
Rolf Drechsler},
title = {Improving {CNF} representations in SAT-based {ATPG} for industrial
circuits using BDDs},
booktitle = {15th European Test Symposium, {ETS} 2010, Prague, Czech Republic,
May 24-28, 2010},
pages = {176--181},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ETSYM.2010.5512763},
doi = {10.1109/ETSYM.2010.5512763},
timestamp = {Tue, 28 Apr 2020 11:43:44 +0200},
biburl = {https://dblp.org/rec/conf/ets/TilleEKSD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/WilleOD10,
author = {Robert Wille and
Sebastian Offermann and
Rolf Drechsler},
editor = {Adam Morawiec and
Jinnie Hinderscheit},
title = {SyReC: {A} Programming Language for Synthesis of Reversible Circuits},
booktitle = {Proceedings of the 2010 Forum on specification {\&} Design Languages,
{FDL} 2010, September 14-16, 2010, Southampton, {UK}},
pages = {184--189},
publisher = {ECSI, Electronic Chips {\&} Systems design Initiative},
year = {2010},
timestamp = {Fri, 25 Feb 2011 17:44:56 +0100},
biburl = {https://dblp.org/rec/conf/fdl/WilleOD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/forms/SulflowD10,
author = {Andr{\'{e}} S{\"{u}}lflow and
Rolf Drechsler},
editor = {Eckehard Schnieder and
G{\'{e}}za Tarnai},
title = {Automatic Fault Localization for Programmable Logic Controllers},
booktitle = {{FORMS/FORMAT} 2010 - Formal Methods for Automation and Safety in
Railway and Automotive Systems [8th Symposium on Formal Methods for
Automation and Safety in Railway and Automotive Systems, Braunschweig,
Germany, December 2-3, 2010},
pages = {247--256},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-14261-1\_25},
doi = {10.1007/978-3-642-14261-1\_25},
timestamp = {Thu, 25 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/forms/SulflowD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/JungFWD10,
author = {Jean Christoph Jung and
Stefan Frehse and
Robert Wille and
Rolf Drechsler},
editor = {R. Iris Bahar and
Fabrizio Lombardi and
David Atienza and
Erik Brunvand},
title = {Enhancing debugging of multiple missing control errors in reversible
logic},
booktitle = {Proceedings of the 20th {ACM} Great Lakes Symposium on {VLSI} 2009,
Providence, Rhode Island, USA, May 16-18 2010},
pages = {465--470},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1785481.1785588},
doi = {10.1145/1785481.1785588},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/JungFWD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/LeGD10,
author = {Hoang Minh Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Towards analyzing functional coverage in SystemC {TLM} property checking},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {67--74},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496658},
doi = {10.1109/HLDVT.2010.5496658},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/LeGD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HaedickeAFFD10,
author = {Finn Haedicke and
Bijan Alizadeh and
G{\"{o}}rschwin Fey and
Masahiro Fujita and
Rolf Drechsler},
editor = {Louis Scheffer and
Joel R. Phillips and
Alan J. Hu},
title = {Polynomial datapath optimization using constraint solving and formal
modelling},
booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010,
San Jose, CA, USA, November 7-11, 2010},
pages = {756--761},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICCAD.2010.5654279},
doi = {10.1109/ICCAD.2010.5654279},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HaedickeAFFD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/idt/SoekenWD10,
author = {Mathias Soeken and
Robert Wille and
Rolf Drechsler},
editor = {Yervant Zorian and
Imtinan Elahi and
Andr{\'{e}} Ivanov and
Ashraf Salem},
title = {Hierarchical synthesis of reversible circuits using positive and negative
Davio decomposition},
booktitle = {5th International Design and Test Workshop, {IDT} 2010, Abu Dhabi,
UAE, 14-15 December 2010},
pages = {143--148},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/IDT.2010.5724427},
doi = {10.1109/IDT.2010.5724427},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/idt/SoekenWD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/idt/ZhangWD10,
author = {Hongyan Zhang and
Robert Wille and
Rolf Drechsler},
editor = {Yervant Zorian and
Imtinan Elahi and
Andr{\'{e}} Ivanov and
Ashraf Salem},
title = {SAT-based {ATPG} for reversible circuits},
booktitle = {5th International Design and Test Workshop, {IDT} 2010, Abu Dhabi,
UAE, 14-15 December 2010},
pages = {149--154},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/IDT.2010.5724428},
doi = {10.1109/IDT.2010.5724428},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/idt/ZhangWD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SulflowFD10,
author = {Andr{\'{e}} S{\"{u}}lflow and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {Using {QBF} to increase accuracy of SAT-based debugging},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {641--644},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537506},
doi = {10.1109/ISCAS.2010.5537506},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SulflowFD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/EggersglussTD10,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Daniel Tille and
Rolf Drechsler},
title = {Efficient test generation with maximal crosstalk-induced noise using
unconstrained aggressor excitation},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {649--652},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537503},
doi = {10.1109/ISCAS.2010.5537503},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/EggersglussTD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/FinderD10,
author = {Alexander Finder and
Rolf Drechsler},
title = {An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions},
booktitle = {40th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2010, Barcelona, Spain, 26-28 May 2010},
pages = {150--155},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ISMVL.2010.36},
doi = {10.1109/ISMVL.2010.36},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/FinderD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/FrehseWD10,
author = {Stefan Frehse and
Robert Wille and
Rolf Drechsler},
title = {Efficient Simulation-Based Debugging of Reversible Logic},
booktitle = {40th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2010, Barcelona, Spain, 26-28 May 2010},
pages = {156--161},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ISMVL.2010.37},
doi = {10.1109/ISMVL.2010.37},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/FrehseWD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/MillerWD10,
author = {D. Michael Miller and
Robert Wille and
Rolf Drechsler},
title = {Reducing Reversible Circuit Cost by Adding Lines},
booktitle = {40th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2010, Barcelona, Spain, 26-28 May 2010},
pages = {217--222},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ISMVL.2010.48},
doi = {10.1109/ISMVL.2010.48},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/MillerWD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/WilleOD10,
author = {Robert Wille and
Sebastian Offermann and
Rolf Drechsler},
editor = {Manfred Dietrich},
title = {SyReC: {A} Programming Language for Synthesis of Reversible Circuits},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Dresden, Germany, February 22-24,
2010},
pages = {21--30},
publisher = {Fraunhofer Verlag},
year = {2010},
timestamp = {Thu, 28 Jun 2012 08:20:28 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/WilleOD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/SoekenWKGD10,
author = {Mathias Soeken and
Robert Wille and
Mirco Kuhlmann and
Martin Gogolla and
Rolf Drechsler},
editor = {Manfred Dietrich},
title = {Verifying {UML/OCL} Models Using Boolean Satisfiability},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Dresden, Germany, February 22-24,
2010},
pages = {57--66},
publisher = {Fraunhofer Verlag},
year = {2010},
timestamp = {Thu, 28 Jun 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/SoekenWKGD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/GrosseLD10,
author = {Daniel Gro{\ss}e and
Hoang Minh Le and
Rolf Drechsler},
title = {Proving transaction and system-level properties of untimed SystemC
{TLM} designs},
booktitle = {8th {ACM/IEEE} International Conference on Formal Methods and Models
for Codesign {(MEMOCODE} 2010), Grenoble, France, 26-28 July 2010},
pages = {113--122},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/MEMCOD.2010.5558643},
doi = {10.1109/MEMCOD.2010.5558643},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/memocode/GrosseLD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/FeySD10,
author = {G{\"{o}}rschwin Fey and
Andr{\'{e}} S{\"{u}}lflow and
Rolf Drechsler},
editor = {Magdy S. Abadir and
Jay Bhadra and
Li{-}C. Wang},
title = {Towards Unifying Localization and Explanation for Automated Debugging},
booktitle = {11th International Workshop on Microprocessor Test and Verification,
{MTV} 2010, Austin, TX, USA, December 13-15, 2010},
pages = {3--8},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/MTV.2010.10},
doi = {10.1109/MTV.2010.10},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/FeySD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/LeGD10,
author = {Hoang Minh Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Magdy S. Abadir and
Jay Bhadra and
Li{-}C. Wang},
title = {Automatic Fault Localization for SystemC {TLM} Designs},
booktitle = {11th International Workshop on Microprocessor Test and Verification,
{MTV} 2010, Austin, TX, USA, December 13-15, 2010},
pages = {35--40},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/MTV.2010.15},
doi = {10.1109/MTV.2010.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/LeGD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0023207,
author = {Rolf Drechsler and
Stephan Eggersgl{\"{u}}{\ss} and
G{\"{o}}rschwin Fey and
Daniel Tille},
title = {Test Pattern Generation using Boolean Proof Engines},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-90-481-2360-5},
doi = {10.1007/978-90-481-2360-5},
isbn = {978-90-481-2359-9},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0023207.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ai/EbendtD09,
author = {R{\"{u}}diger Ebendt and
Rolf Drechsler},
title = {Weighted A\({}^{\mbox{*}}\) search - unifying view and application},
journal = {Artif. Intell.},
volume = {173},
number = {14},
pages = {1310--1342},
year = {2009},
url = {https://doi.org/10.1016/j.artint.2009.06.004},
doi = {10.1016/J.ARTINT.2009.06.004},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ai/EbendtD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/RoginKFDR09,
author = {Frank Rogin and
Thomas Klotz and
G{\"{o}}rschwin Fey and
Rolf Drechsler and
Steffen R{\"{u}}lke},
title = {Advanced verification by automatic property generation},
journal = {{IET} Comput. Digit. Tech.},
volume = {3},
number = {4},
pages = {338--353},
year = {2009},
url = {https://doi.org/10.1049/iet-cdt.2008.0110},
doi = {10.1049/IET-CDT.2008.0110},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/RoginKFDR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/it/DrechslerEFST09,
author = {Rolf Drechsler and
Stephan Eggersgl{\"{u}}{\ss} and
G{\"{o}}rschwin Fey and
J{\"{u}}rgen Schl{\"{o}}ffel and
Daniel Tille},
title = {Effiziente Erf{\"{u}}llbarkeitsalgorithmen f{\"{u}}r die
Generierung von Testmustern (Efficient Satisfiability Solving Algorithms
for Test Pattern Generation)},
journal = {it Inf. Technol.},
volume = {51},
number = {2},
pages = {102--111},
year = {2009},
url = {https://doi.org/10.1524/itit.2009.0529},
doi = {10.1524/ITIT.2009.0529},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/it/DrechslerEFST09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/GrosseWDD09,
author = {Daniel Gro{\ss}e and
Robert Wille and
Gerhard W. Dueck and
Rolf Drechsler},
title = {Exact Synthesis of Elementary Quantum Gate Circuits},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {15},
number = {4},
pages = {283--300},
year = {2009},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-15-number-4-2009/mvlsc-15-4-p-283-300/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/GrosseWDD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GrosseWDD09,
author = {Daniel Gro{\ss}e and
Robert Wille and
Gerhard W. Dueck and
Rolf Drechsler},
title = {Exact Multiple-Control Toffoli Network Synthesis With {SAT} Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {5},
pages = {703--715},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2017215},
doi = {10.1109/TCAD.2009.2017215},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GrosseWDD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/EggersglussTD09,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Daniel Tille and
Rolf Drechsler},
title = {Speeding up SAT-Based {ATPG} Using Dynamic Clause Activation},
booktitle = {Proceedings of the Eighteentgh Asian Test Symposium, {ATS} 2009, 23-26
November 2009, Taichung, Taiwan},
pages = {177--182},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ATS.2009.26},
doi = {10.1109/ATS.2009.26},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/EggersglussTD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/FeySD09,
author = {G{\"{o}}rschwin Fey and
Andr{\'{e}} S{\"{u}}lflow and
Rolf Drechsler},
title = {Computing bounds for fault tolerance using formal techniques},
booktitle = {Proceedings of the 46th Design Automation Conference, {DAC} 2009,
San Francisco, CA, USA, July 26-31, 2009},
pages = {190--195},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629911.1629963},
doi = {10.1145/1629911.1629963},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/FeySD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WilleD09,
author = {Robert Wille and
Rolf Drechsler},
title = {BDD-based synthesis of reversible logic for large functions},
booktitle = {Proceedings of the 46th Design Automation Conference, {DAC} 2009,
San Francisco, CA, USA, July 26-31, 2009},
pages = {270--275},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629911.1629984},
doi = {10.1145/1629911.1629984},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/WilleD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GenzD09,
author = {Christian Genz and
Rolf Drechsler},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {Overcoming limitations of the SystemC data introspection},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {590--593},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090734},
doi = {10.1109/DATE.2009.5090734},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/GenzD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KuhneGD09,
author = {Ulrich K{\"{u}}hne and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {Property analysis and design understanding},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {1246--1249},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090855},
doi = {10.1109/DATE.2009.5090855},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/KuhneGD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WilleGFDD09,
author = {Robert Wille and
Daniel Gro{\ss}e and
Stefan Frehse and
Gerhard W. Dueck and
Rolf Drechsler},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {Debugging of Toffoli networks},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {1284--1289},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090863},
doi = {10.1109/DATE.2009.5090863},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/WilleGFDD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SulflowFBKD09,
author = {Andr{\'{e}} S{\"{u}}lflow and
G{\"{o}}rschwin Fey and
C{\'{e}}cile Braunstein and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {Increasing the accuracy of SAT-based debugging},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {1326--1331},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090870},
doi = {10.1109/DATE.2009.5090870},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/SulflowFBKD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/TilleD09,
author = {Daniel Tille and
Rolf Drechsler},
title = {A fast untestability proof for SAT-based {ATPG}},
booktitle = {Proceedings of the 2009 {IEEE} Symposium on Design and Diagnostics
of Electronic Circuits and Systems, {DDECS} 2009, April 15-17, 2009,
Liberec, Czech Republic},
pages = {38--43},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/DDECS.2009.5012096},
doi = {10.1109/DDECS.2009.5012096},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/TilleD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/FrehseFSD09,
author = {Stefan Frehse and
G{\"{o}}rschwin Fey and
Andr{\'{e}} S{\"{u}}lflow and
Rolf Drechsler},
editor = {Antonio N{\'{u}}{\~{n}}ez and
Pedro P. Carballo},
title = {Robustness Check for Multiple Faults Using Formal Techniques},
booktitle = {12th Euromicro Conference on Digital System Design, Architectures,
Methods and Tools, {DSD} 2009, 27-29 August 2009, Patras, Greece},
pages = {85--90},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/DSD.2009.218},
doi = {10.1109/DSD.2009.218},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/FrehseFSD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/EggersglussD09,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {Increasing Robustness of SAT-based Delay Test Generation Using Efficient
Dynamic Learning Techniques},
booktitle = {14th {IEEE} European Test Symposium, {ETS} 2009, Sevilla, Spain, May
25-29, 2009},
pages = {81--86},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ETS.2009.13},
doi = {10.1109/ETS.2009.13},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/EggersglussD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/WilleGHD09,
author = {Robert Wille and
Daniel Gro{\ss}e and
Finn Haedicke and
Rolf Drechsler},
title = {SMT-based stimuli generation in the SystemC Verification library},
booktitle = {Forum on specification and Design Languages, {FDL} 2009, September
22-24, 2009, Sophia Antipolis, France, Proceedings},
pages = {1--6},
publisher = {{IEEE}},
year = {2009},
url = {https://ieeexplore.ieee.org/document/5404070/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/WilleGHD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GrosseWKD09,
author = {Daniel Gro{\ss}e and
Robert Wille and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
editor = {Fabrizio Lombardi and
Sanjukta Bhanja and
Yehia Massoud and
R. Iris Bahar},
title = {Contradictory antecedent debugging in bounded model checking},
booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
Boston Area, MA, USA, May 10-12 2009},
pages = {173--176},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1531542.1531586},
doi = {10.1145/1531542.1531586},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/GrosseWKD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PallaBEAD09,
author = {Murthy Palla and
Jens Bargfrede and
Stephan Eggersgl{\"{u}}{\ss} and
Walter Anheier and
Rolf Drechsler},
editor = {Jaijeet S. Roychowdhury},
title = {Timing Arc based logic analysis for false noise reduction},
booktitle = {2009 International Conference on Computer-Aided Design, {ICCAD} 2009,
San Jose, CA, USA, November 2-5, 2009},
pages = {225--230},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1687399.1687440},
doi = {10.1145/1687399.1687440},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/PallaBEAD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/EbendtD09,
author = {R{\"{u}}diger Ebendt and
Rolf Drechsler},
title = {Approximate {BDD} Minimization by Weighted {A}},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2009), 24-17
May 2009, Taipei, Taiwan},
pages = {2974--2977},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISCAS.2009.5118427},
doi = {10.1109/ISCAS.2009.5118427},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/EbendtD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/SulflowWFD09,
author = {Andr{\'{e}} S{\"{u}}lflow and
Robert Wille and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {Evaluation of Cardinality Constraints on SMT-Based Debugging},
booktitle = {{ISMVL} 2009, 39th International Symposium on Multiple-Valued Logic,
21-23 May 2009, Naha, Okinawaw, Japan},
pages = {298--303},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISMVL.2009.28},
doi = {10.1109/ISMVL.2009.28},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/SulflowWFD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/WilleGMD09,
author = {Robert Wille and
Daniel Gro{\ss}e and
D. Michael Miller and
Rolf Drechsler},
title = {Equivalence Checking of Reversible Circuits},
booktitle = {{ISMVL} 2009, 39th International Symposium on Multiple-Valued Logic,
21-23 May 2009, Naha, Okinawaw, Japan},
pages = {324--330},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISMVL.2009.19},
doi = {10.1109/ISMVL.2009.19},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/WilleGMD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/MessingGHD09,
author = {Marc Messing and
Andreas Glowatz and
Friedrich Hapke and
Rolf Drechsler},
title = {Using a two-dimensional fault list for compact Automatic Test Pattern
Generation},
booktitle = {10th Latin American Test Workshop, {LATW} 2009, Rio de Janeiro, Brazil,
March 2-5, 2009},
pages = {1--6},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/LATW.2009.4813791},
doi = {10.1109/LATW.2009.4813791},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/latw/MessingGHD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/SulflowFBKD09,
author = {Andr{\'{e}} S{\"{u}}lflow and
G{\"{o}}rschwin Fey and
C{\'{e}}cile Braunstein and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
editor = {Carsten Gremzow and
Nico Moser},
title = {Increasing the Accuracy of SAT-based Debugging},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Berlin, Germany, March 2-4, 2009},
pages = {47--56},
publisher = {Universit{\"{a}}tsbibliothek Berlin, Germany},
year = {2009},
timestamp = {Thu, 28 Jun 2012 08:33:25 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/SulflowFBKD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/WilleGMD09,
author = {Robert Wille and
Daniel Gro{\ss}e and
D. Michael Miller and
Rolf Drechsler},
editor = {Carsten Gremzow and
Nico Moser},
title = {Equivalence Checking of Reversible Circuits},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Berlin, Germany, March 2-4, 2009},
pages = {67--76},
publisher = {Universit{\"{a}}tsbibliothek Berlin, Germany},
year = {2009},
timestamp = {Thu, 28 Jun 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/WilleGMD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/GrosseLD09,
author = {Daniel Gro{\ss}e and
Hoang Minh Le and
Rolf Drechsler},
title = {Induction-Based Formal Verification of SystemC {TLM} Designs},
booktitle = {10th International Workshop on Microprocessor Test and Verification,
{MTV} 2009, Austin, Texas, USA, 7-9 December 2009},
pages = {101--106},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/MTV.2009.16},
doi = {10.1109/MTV.2009.16},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/GrosseLD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/SulflowKFGD09,
author = {Andr{\'{e}} S{\"{u}}lflow and
Ulrich K{\"{u}}hne and
G{\"{o}}rschwin Fey and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {WoLFram- {A} Word Level Framework for Formal Verification},
booktitle = {Proceedings of the Twentienth {IEEE/IFIP} International Symposium
on Rapid System Prototyping, Shortening the Path from Specification
to Prototype, {RSP} 2009, Paris, France, 23-26 June 2009},
pages = {11--17},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/RSP.2009.21},
doi = {10.1109/RSP.2009.21},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rsp/SulflowKFGD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/RoginDR09,
author = {Frank Rogin and
Rolf Drechsler and
Steffen R{\"{u}}lke},
title = {Automatic debugging of System-on-a-Chip designs},
booktitle = {Annual {IEEE} International SoC Conference, SoCC 2009, September 9-11,
2009, Belfast, Northern Ireland, UK, Proceedings},
pages = {333--336},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/SOCCON.2009.5398027},
doi = {10.1109/SOCCON.2009.5398027},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/RoginDR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/WilleGDD09,
author = {Robert Wille and
Daniel Gro{\ss}e and
Gerhard W. Dueck and
Rolf Drechsler},
title = {Reversible Logic Synthesis with Output Permutation},
booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction,
The 22nd International Conference on {VLSI} Design, New Delhi, India,
5-9 January 2009},
pages = {189--194},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/VLSI.Design.2009.40},
doi = {10.1109/VLSI.DESIGN.2009.40},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/WilleGDD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:journals/entcs/WilleD10,
author = {Robert Wille and
Rolf Drechsler},
editor = {Irek Ulidowski},
title = {Effect of {BDD} Optimization on Synthesis of Reversible and Quantum
Logic},
booktitle = {Proceedings of the Workshop on Reversible Computation, RC@ETAPS 2009,
York, UK, March 22, 2009},
series = {Electronic Notes in Theoretical Computer Science},
volume = {253},
number = {6},
pages = {57--70},
publisher = {Elsevier},
year = {2009},
url = {https://doi.org/10.1016/j.entcs.2010.02.006},
doi = {10.1016/J.ENTCS.2010.02.006},
timestamp = {Fri, 24 Feb 2023 15:38:09 +0100},
biburl = {https://dblp.org/rec/journals/entcs/WilleD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:series/faia/DrechslerJN09,
author = {Rolf Drechsler and
Tommi A. Junttila and
Ilkka Niemel{\"{a}}},
editor = {Armin Biere and
Marijn Heule and
Hans van Maaren and
Toby Walsh},
title = {Non-Clausal {SAT} and {ATPG}},
booktitle = {Handbook of Satisfiability},
series = {Frontiers in Artificial Intelligence and Applications},
volume = {185},
pages = {655--693},
publisher = {{IOS} Press},
year = {2009},
url = {https://doi.org/10.3233/978-1-58603-929-5-655},
doi = {10.3233/978-1-58603-929-5-655},
timestamp = {Fri, 06 May 2022 08:00:40 +0200},
biburl = {https://dblp.org/rec/series/faia/DrechslerJN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dagstuhl/2009P9461,
editor = {Bernd Becker and
V. Bertacoo and
Rolf Drechsler and
Masahiro Fujita},
title = {Algorithms and Applications for Next Generation {SAT} Solvers, 08.11.
- 13.11.2009},
series = {Dagstuhl Seminar Proceedings},
volume = {09461},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik, Germany},
year = {2009},
url = {http://drops.dagstuhl.de/portals/09461/},
timestamp = {Thu, 10 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dagstuhl/2009P9461.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dagstuhl/BeckerBDF09,
author = {Bernd Becker and
Valeria Bertacco and
Rolf Drechsler and
Masahiro Fujita},
editor = {Bernd Becker and
V. Bertacoo and
Rolf Drechsler and
Masahiro Fujita},
title = {09461 Abstracts Collection - Algorithms and Applications for Next
Generation {SAT} Solvers},
booktitle = {Algorithms and Applications for Next Generation {SAT} Solvers, 08.11.
- 13.11.2009},
series = {Dagstuhl Seminar Proceedings},
volume = {09461},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik, Germany},
year = {2009},
url = {http://drops.dagstuhl.de/opus/volltexte/2010/2511/},
timestamp = {Thu, 10 Jun 2021 13:02:06 +0200},
biburl = {https://dblp.org/rec/conf/dagstuhl/BeckerBDF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dagstuhl/GrosseLD09,
author = {Daniel Gro{\ss}e and
Hoang Minh Le and
Rolf Drechsler},
editor = {Bernd Becker and
V. Bertacoo and
Rolf Drechsler and
Masahiro Fujita},
title = {Formal Verification of Abstract SystemC Models},
booktitle = {Algorithms and Applications for Next Generation {SAT} Solvers, 08.11.
- 13.11.2009},
series = {Dagstuhl Seminar Proceedings},
volume = {09461},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik, Germany},
year = {2009},
url = {http://drops.dagstuhl.de/opus/volltexte/2010/2510/},
timestamp = {Thu, 23 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dagstuhl/GrosseLD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dagstuhl/WilleJSD09,
author = {Robert Wille and
Jean Christoph Jung and
Andr{\'{e}} S{\"{u}}lflow and
Rolf Drechsler},
editor = {Bernd Becker and
V. Bertacoo and
Rolf Drechsler and
Masahiro Fujita},
title = {{SWORD} - Module-based {SAT} Solving},
booktitle = {Algorithms and Applications for Next Generation {SAT} Solvers, 08.11.
- 13.11.2009},
series = {Dagstuhl Seminar Proceedings},
volume = {09461},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik, Germany},
year = {2009},
url = {http://drops.dagstuhl.de/opus/volltexte/2010/2506/},
timestamp = {Thu, 21 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dagstuhl/WilleJSD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0019815,
author = {G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {Robustness and usability in modern design flows},
publisher = {Springer},
year = {2008},
isbn = {978-1-4020-6535-4},
timestamp = {Thu, 10 Feb 2011 00:00:00 +0100},
biburl = {https://dblp.org/rec/books/daglib/0019815.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsat/SafarpourVD08,
author = {Sean Safarpour and
Andreas G. Veneris and
Rolf Drechsler},
title = {Improved SAT-based Reachability Analysis with Observability Don't
Cares},
journal = {J. Satisf. Boolean Model. Comput.},
volume = {5},
number = {1-4},
pages = {1--25},
year = {2008},
url = {https://doi.org/10.3233/sat190050},
doi = {10.3233/SAT190050},
timestamp = {Mon, 17 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsat/SafarpourVD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/FeyBCD08,
author = {G{\"{o}}rschwin Fey and
Anna Bernasconi and
Valentina Ciriani and
Rolf Drechsler},
title = {On the construction of small fully testable circuits with low depth},
journal = {Microprocess. Microsystems},
volume = {32},
number = {5-6},
pages = {263--269},
year = {2008},
url = {https://doi.org/10.1016/j.micpro.2008.03.005},
doi = {10.1016/J.MICPRO.2008.03.005},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/FeyBCD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sttt/KinderD08,
author = {Sebastian Kinder and
Rolf Drechsler},
title = {Modeling and proving functional completeness in formal verification
of counting heads},
journal = {Int. J. Softw. Tools Technol. Transf.},
volume = {10},
number = {6},
pages = {521--534},
year = {2008},
url = {https://doi.org/10.1007/s10009-008-0084-z},
doi = {10.1007/S10009-008-0084-Z},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sttt/KinderD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FeySBD08,
author = {G{\"{o}}rschwin Fey and
Stefan Staber and
Roderick Bloem and
Rolf Drechsler},
title = {Automatic Fault Localization for Property Checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {1138--1149},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923234},
doi = {10.1109/TCAD.2008.923234},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/FeySBD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BernasconiCDV08,
author = {Anna Bernasconi and
Valentina Ciriani and
Rolf Drechsler and
Tiziano Villa},
title = {Logic Minimization and Testability of 2-SPP Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1190--1202},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923072},
doi = {10.1109/TCAD.2008.923072},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BernasconiCDV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GrosseKD08,
author = {Daniel Gro{\ss}e and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
title = {Analyzing Functional Coverage in Bounded Model Checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1305--1314},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925790},
doi = {10.1109/TCAD.2008.925790},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GrosseKD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerEFGHST08,
author = {Rolf Drechsler and
Stephan Eggersgl{\"{u}}{\ss} and
G{\"{o}}rschwin Fey and
Andreas Glowatz and
Friedrich Hapke and
J{\"{u}}rgen Schl{\"{o}}ffel and
Daniel Tille},
title = {On Acceleration of SAT-Based {ATPG} for Industrial Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {7},
pages = {1329--1333},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923107},
doi = {10.1109/TCAD.2008.923107},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerEFGHST08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/PandeyD08,
author = {Sujan Pandey and
Rolf Drechsler},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Robust on-chip bus architecture synthesis for MPSoCs under random
tasks arrival},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {601--606},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4484022},
doi = {10.1109/ASPDAC.2008.4484022},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/PandeyD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PandeyD08,
author = {Sujan Pandey and
Rolf Drechsler},
editor = {Donatella Sciuto},
title = {Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory
Architectures for MPSoCs},
booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany,
March 10-14, 2008},
pages = {206--211},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1109/DATE.2008.4484687},
doi = {10.1109/DATE.2008.4484687},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PandeyD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RoginKFDR08,
author = {Frank Rogin and
Thomas Klotz and
G{\"{o}}rschwin Fey and
Rolf Drechsler and
Steffen R{\"{u}}lke},
editor = {Donatella Sciuto},
title = {Automatic Generation of Complex Properties for Hardware Designs},
booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany,
March 10-14, 2008},
pages = {545--548},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1109/DATE.2008.4484908},
doi = {10.1109/DATE.2008.4484908},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/RoginKFDR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/TilleD08,
author = {Daniel Tille and
Rolf Drechsler},
editor = {Bernd Straube and
Milos Drutarovsk{\'{y}} and
Michel Renovell and
Peter Gramata and
M{\'{a}}ria Fischerov{\'{a}}},
title = {Incremental {SAT} Instance Generation for SAT-based {ATPG}},
booktitle = {Proceedings of the 11th {IEEE} Workshop on Design {\&} Diagnostics
of Electronic Circuits {\&} Systems {(DDECS} 2008), Bratislava,
Slovakia, April 16-18, 2008},
pages = {68--73},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/DDECS.2008.4538759},
doi = {10.1109/DDECS.2008.4538759},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/TilleD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/WilleFMALD08,
author = {Robert Wille and
G{\"{o}}rschwin Fey and
Marc Messing and
Gerhard Angst and
Lothar Linhard and
Rolf Drechsler},
editor = {Luca Fanucci},
title = {Identifying a Subset of System Verilog Assertions for Efficient Bounded
Model Checking},
booktitle = {11th Euromicro Conference on Digital System Design: Architectures,
Methods and Tools, {DSD} 2008, Parma, Italy, September 3-5, 2008},
pages = {542--549},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/DSD.2008.53},
doi = {10.1109/DSD.2008.53},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/WilleFMALD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/GrosseWSD08,
author = {Daniel Gro{\ss}e and
Robert Wille and
Robert Siegmund and
Rolf Drechsler},
title = {Contradiction Analysis for Constraint-based Random Simulation},
booktitle = {Forum on specification and Design Languages, {FDL} 2008, September
23-25, 2008, Stuttgart, Germany, Proceedings},
pages = {130--135},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FDL.2008.4641434},
doi = {10.1109/FDL.2008.4641434},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/fdl/GrosseWSD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/GrosseWSD08a,
author = {Daniel Gro{\ss}e and
Robert Wille and
Robert Siegmund and
Rolf Drechsler},
editor = {Martin Radetzki},
title = {Debugging Contradictory Constraints in Constraint-Based Random Simulation},
booktitle = {Languages for Embedded Systems and their Applications - Selected Contributions
on Specification, Design, and Verification from FDL'08, September
23-25, 2008, Stuttgart, Germany},
series = {Lecture Notes in Electrical Engineering},
volume = {36},
pages = {273--290},
year = {2008},
url = {https://doi.org/10.1007/978-1-4020-9714-0\_18},
doi = {10.1007/978-1-4020-9714-0\_18},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fdl/GrosseWSD08a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SulflowFBD08,
author = {Andr{\'{e}} S{\"{u}}lflow and
G{\"{o}}rschwin Fey and
Roderick Bloem and
Rolf Drechsler},
editor = {Vijaykrishnan Narayanan and
Zhiyuan Yan and
Enrico Macii and
Sanjukta Bhanja},
title = {Using unsatisfiable cores to debug multiple design errors},
booktitle = {Proceedings of the 18th {ACM} Great Lakes Symposium on {VLSI} 2008,
Orlando, Florida, USA, May 4-6, 2008},
pages = {77--82},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1366110.1366131},
doi = {10.1145/1366110.1366131},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/SulflowFBD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/PandeyDMG08,
author = {Sujan Pandey and
Rolf Drechsler and
Tudor Murgan and
Manfred Glesner},
title = {Process variations aware robust on-chip bus architecture synthesis
for MPSoCs},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
pages = {2989--2992},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISCAS.2008.4542086},
doi = {10.1109/ISCAS.2008.4542086},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/PandeyDMG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/LogofatuD08,
author = {Doina Logofatu and
Rolf Drechsler},
title = {Comparative Study by Solving the Test Compaction Problem},
booktitle = {38th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2008), 22-23 May 2008, Dallas, Texas, {USA}},
pages = {44--49},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISMVL.2008.17},
doi = {10.1109/ISMVL.2008.17},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/LogofatuD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/EggersglussD08,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {On the Influence of Boolean Encodings in SAT-Based {ATPG} for Path
Delay Faults},
booktitle = {38th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2008), 22-23 May 2008, Dallas, Texas, {USA}},
pages = {94--99},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISMVL.2008.19},
doi = {10.1109/ISMVL.2008.19},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/EggersglussD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/GrosseWDD08,
author = {Daniel Gro{\ss}e and
Robert Wille and
Gerhard W. Dueck and
Rolf Drechsler},
title = {Exact Synthesis of Elementary Quantum Gate Circuits for Reversible
Functions with Don't Cares},
booktitle = {38th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2008), 22-23 May 2008, Dallas, Texas, {USA}},
pages = {214--219},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISMVL.2008.42},
doi = {10.1109/ISMVL.2008.42},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/GrosseWDD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/WilleGTDD08,
author = {Robert Wille and
Daniel Gro{\ss}e and
Lisa Teuber and
Gerhard W. Dueck and
Rolf Drechsler},
title = {RevLib: An Online Resource for Reversible Functions and Reversible
Circuits},
booktitle = {38th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2008), 22-23 May 2008, Dallas, Texas, {USA}},
pages = {220--225},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISMVL.2008.43},
doi = {10.1109/ISMVL.2008.43},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/WilleGTDD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/PallaBKAD08,
author = {Murthy Palla and
Jens Bargfrede and
Klaus Koch and
Walter Anheier and
Rolf Drechsler},
title = {Adaptive Branch and Bound Using {SAT} to Estimate False Crosstalk},
booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
2008), 17-19 March 2008, San Jose, CA, {USA}},
pages = {508--513},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISQED.2008.4479787},
doi = {10.1109/ISQED.2008.4479787},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/PallaBKAD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/FeyD08,
author = {G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {A Basis for Formal Robustness Checking},
booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
2008), 17-19 March 2008, San Jose, CA, {USA}},
pages = {784--789},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISQED.2008.4479838},
doi = {10.1109/ISQED.2008.4479838},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/FeyD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/WilleGSD08,
author = {Robert Wille and
Daniel Gro{\ss}e and
Mathias Soeken and
Rolf Drechsler},
title = {Using Higher Levels of Abstraction for Solving Optimization Problems
by Boolean Satisfiability},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2008, 7-9
April 2008, Montpellier, France},
pages = {411--416},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISVLSI.2008.82},
doi = {10.1109/ISVLSI.2008.82},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/WilleGSD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/SulflowFBD08,
author = {Andr{\'{e}} S{\"{u}}lflow and
G{\"{o}}rschwin Fey and
Roderick Bloem and
Rolf Drechsler},
editor = {Christoph Scholl and
Stefan Disch},
title = {Debugging Design Errors by Using Unsatisfiable Cores},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Freiburg, Germany, March 3-5,
2008},
pages = {159--168},
publisher = {Shaker},
year = {2008},
timestamp = {Wed, 03 Aug 2022 12:31:57 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/SulflowFBD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/GrosseWKD08,
author = {Daniel Gro{\ss}e and
Robert Wille and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
editor = {Christoph Scholl and
Stefan Disch},
title = {Using Contradiction Analysis for Antecedent Debugging in Bounded Model
Checking},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Freiburg, Germany, March 3-5,
2008},
pages = {169--178},
publisher = {Shaker},
year = {2008},
timestamp = {Thu, 28 Jun 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/GrosseWKD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/KuhneGD08,
author = {Ulrich K{\"{u}}hne and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Property Analysis and Design Understanding in a Quality-Driven Bounded
Model Checking Flow},
booktitle = {Ninth International Workshop on Microprocessor Test and Verification,
{MTV} 2008, Austin, Texas, USA, 8-10 December 2008},
pages = {88--93},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/MTV.2008.17},
doi = {10.1109/MTV.2008.17},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/KuhneGD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/evoW/2008,
editor = {Mario Giacobini and
Anthony Brabazon and
Stefano Cagnoni and
Gianni Di Caro and
Rolf Drechsler and
Anik{\'{o}} Ek{\'{a}}rt and
Anna Esparcia{-}Alc{\'{a}}zar and
Muddassar Farooq and
Andreas Fink and
Jon McCormack and
Michael O'Neill and
Juan Romero and
Franz Rothlauf and
Giovanni Squillero and
Sima Uyar and
Shengxiang Yang},
title = {Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET,
EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog,
Naples, Italy, March 26-28, 2008. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4974},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-78761-7},
doi = {10.1007/978-3-540-78761-7},
isbn = {978-3-540-78760-0},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/evoW/2008.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dagstuhl/DrechslerEFT08,
author = {Rolf Drechsler and
Stephan Eggersgl{\"{u}}{\ss} and
G{\"{o}}rschwin Fey and
Daniel Tille},
editor = {Holger Schlingloff and
Tanja E. J. Vos and
Joachim Wegener},
title = {SAT-based Automatic Test Pattern Generation},
booktitle = {Evolutionary Test Generation, 24.08. - 29.08.2008},
series = {Dagstuhl Seminar Proceedings},
volume = {08351},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik, Germany},
year = {2008},
url = {http://drops.dagstuhl.de/opus/volltexte/2009/2015/},
timestamp = {Thu, 10 Jun 2021 13:02:07 +0200},
biburl = {https://dblp.org/rec/conf/dagstuhl/DrechslerEFT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/it/MurankoD07,
author = {Beate Muranko and
Rolf Drechsler},
title = {Technische Dokumentation von Soft- und Hardware in Eingebetteten Systemen
(Technical Documentation of Soft- and Hardware in Embedded Systems)},
journal = {it Inf. Technol.},
volume = {49},
number = {2},
pages = {110},
year = {2007},
url = {https://doi.org/10.1524/itit.2007.49.2.110},
doi = {10.1524/ITIT.2007.49.2.110},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/it/MurankoD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/EggersglussD07,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {Improving Test Pattern Compactness in SAT-based {ATPG}},
booktitle = {16th Asian Test Symposium, {ATS} 2007, Beijing, China, October 8-11,
2007},
pages = {445--452},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ATS.2007.14},
doi = {10.1109/ATS.2007.14},
timestamp = {Wed, 09 Nov 2022 21:30:34 +0100},
biburl = {https://dblp.org/rec/conf/ats/EggersglussD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GrosseKD07,
author = {Daniel Gro{\ss}e and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
editor = {Rudy Lauwereins and
Jan Madsen},
title = {Estimating functional coverage in bounded model checking},
booktitle = {2007 Design, Automation and Test in Europe Conference and Exposition,
{DATE} 2007, Nice, France, April 16-20, 2007},
pages = {1176--1181},
publisher = {{EDA} Consortium, San Jose, CA, {USA}},
year = {2007},
url = {https://dl.acm.org/citation.cfm?id=1266620},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/GrosseKD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/TilleFD07,
author = {Daniel Tille and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
editor = {Patrick Girard and
Andrzej Krasniewski and
Elena Gramatov{\'{a}} and
Adam Pawlak and
Tomasz Garbolino},
title = {Instance Generation for SAT-based {ATPG}},
booktitle = {Proceedings of the 10th {IEEE} Workshop on Design {\&} Diagnostics
of Electronic Circuits {\&} Systems {(DDECS} 2007), Krak{\'{o}}w,
Poland, April 11-13, 2007},
pages = {153--156},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/DDECS.2007.4295272},
doi = {10.1109/DDECS.2007.4295272},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/TilleFD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/KinderD07,
author = {Sebastian Kinder and
Rolf Drechsler},
title = {Proving Completeness of Properties in Formal Verification of Counting
Heads for Railways},
booktitle = {Tenth Euromicro Conference on Digital System Design: Architectures,
Methods and Tools {(DSD} 2007), 29-31 August 2007, L{\"{u}}beck,
Germany},
pages = {396--403},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/DSD.2007.4341498},
doi = {10.1109/DSD.2007.4341498},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/dsd/KinderD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/FeyBCD07,
author = {G{\"{o}}rschwin Fey and
Anna Bernasconi and
Valentina Ciriani and
Rolf Drechsler},
title = {On the Construction of Small Fully Testable Circuits with Low Depth},
booktitle = {Tenth Euromicro Conference on Digital System Design: Architectures,
Methods and Tools {(DSD} 2007), 29-31 August 2007, L{\"{u}}beck,
Germany},
pages = {563--569},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/DSD.2007.4341525},
doi = {10.1109/DSD.2007.4341525},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dsd/FeyBCD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/emo/SulflowDD06,
author = {Andr{\'{e}} S{\"{u}}lflow and
Nicole Drechsler and
Rolf Drechsler},
editor = {Shigeru Obayashi and
Kalyanmoy Deb and
Carlo Poloni and
Tomoyuki Hiroyasu and
Tadahiko Murata},
title = {Robust Multi-Objective Optimization in High Dimensional Spaces},
booktitle = {Evolutionary Multi-Criterion Optimization, 4th International Conference,
{EMO} 2007, Matsushima, Japan, March 5-8, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4403},
pages = {715--726},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-70928-2\_54},
doi = {10.1007/978-3-540-70928-2\_54},
timestamp = {Thu, 30 Jun 2022 16:13:16 +0200},
biburl = {https://dblp.org/rec/conf/emo/SulflowDD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/RoginGDR07,
author = {Frank Rogin and
Christian Genz and
Rolf Drechsler and
Steffen R{\"{u}}lke},
title = {An Integrated SystemC Debugging Environment},
booktitle = {Forum on specification and Design Languages, {FDL} 2007, September
18-20, 2007, Barcelona, Spain, Proceedings},
pages = {140--145},
publisher = {{ECSI}},
year = {2007},
url = {http://www.ecsi-association.org/ecsi/main.asp?l1=library\&\#38;fn=def\&\#38;id=248},
timestamp = {Thu, 03 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fdl/RoginGDR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/GrossePKD07,
author = {Daniel Gro{\ss}e and
Hernan Peraza and
Wolfgang Klingauf and
Rolf Drechsler},
title = {Measuring the Quality of a SystemC Testbench by using Code Coverage
Techniques},
booktitle = {Forum on specification and Design Languages, {FDL} 2007, September
18-20, 2007, Barcelona, Spain, Proceedings},
pages = {146--151},
publisher = {{ECSI}},
year = {2007},
url = {http://www.ecsi-association.org/ecsi/main.asp?l1=library\&\#38;fn=def\&\#38;id=249},
timestamp = {Thu, 03 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fdl/GrossePKD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GrosseCDD07,
author = {Daniel Gro{\ss}e and
Xiaobo Chen and
Gerhard W. Dueck and
Rolf Drechsler},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Exact sat-based toffoli network synthesis},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {96--101},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228812},
doi = {10.1145/1228784.1228812},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/GrosseCDD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GrosseED07,
author = {Daniel Gro{\ss}e and
R{\"{u}}diger Ebendt and
Rolf Drechsler},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Improvements for constraint solving in the systemc verification library},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {493--496},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228901},
doi = {10.1145/1228784.1228901},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/GrosseED07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icsoft/DrechslerB07,
author = {Rolf Drechsler and
Andreas Breiter},
editor = {Joaquim Filipe and
Boris Shishkov and
Markus Helfert},
title = {Hardware Project Management - What we Can Learn from the Software
Development Process for Hardware Design?},
booktitle = {{ICSOFT} 2007, Proceedings of the Second International Conference
on Software and Data Technologies, Volume SE, Barcelona, Spain, July
22-25, 2007},
pages = {409--416},
publisher = {{INSTICC} Press},
year = {2007},
timestamp = {Tue, 24 Feb 2009 15:20:59 +0100},
biburl = {https://dblp.org/rec/conf/icsoft/DrechslerB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GenzDAL07,
author = {Christian Genz and
Rolf Drechsler and
Gerhard Angst and
Lothar Linhard},
title = {Visualization of SystemC Designs},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {413--416},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378551},
doi = {10.1109/ISCAS.2007.378551},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GenzDAL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/EggersglussFD07,
author = {Stephan Eggersgl{\"{u}}{\ss} and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {SAT-based {ATPG} for Path Delay Faults in Sequential Circuits},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {3671--3674},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378639},
doi = {10.1109/ISCAS.2007.378639},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/EggersglussFD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/EggersglussTFDGHS07,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Daniel Tille and
G{\"{o}}rschwin Fey and
Rolf Drechsler and
Andreas Glowatz and
Friedrich Hapke and
J{\"{u}}rgen Schl{\"{o}}ffel},
title = {Experimental Studies on SAT-Based {ATPG} for Gate Delay Faults},
booktitle = {37th International Symposium on Multiple-Valued Logic, {ISMVL} 2007,
13-16 May 2007, Oslo, Norway},
pages = {6},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISMVL.2007.21},
doi = {10.1109/ISMVL.2007.21},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/EggersglussTFDGHS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/SulflowD07,
author = {Andr{\'{e}} S{\"{u}}lflow and
Rolf Drechsler},
title = {Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p{\^{}}\{m\})
in SystemC},
booktitle = {37th International Symposium on Multiple-Valued Logic, {ISMVL} 2007,
13-16 May 2007, Oslo, Norway},
pages = {42},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISMVL.2007.34},
doi = {10.1109/ISMVL.2007.34},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/SulflowD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/AmouiGTD07,
author = {Mahsan Amoui and
Daniel Gro{\ss}e and
Mitchell A. Thornton and
Rolf Drechsler},
title = {Evaluation of Toggle Coverage for {MVL} Circuits Specified in the
SystemVerilog {HDL}},
booktitle = {37th International Symposium on Multiple-Valued Logic, {ISMVL} 2007,
13-16 May 2007, Oslo, Norway},
pages = {50},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISMVL.2007.19},
doi = {10.1109/ISMVL.2007.19},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/AmouiGTD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/KuhneGD07,
author = {Ulrich K{\"{u}}hne and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Improving the Quality of Bounded Model Checking by Means of Coverage
Estimation},
booktitle = {2007 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2007), May 9-11, 2007, Porto Alegre, Brazil},
pages = {165--170},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISVLSI.2007.57},
doi = {10.1109/ISVLSI.2007.57},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/KuhneGD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/FeyGEWD07,
author = {G{\"{o}}rschwin Fey and
Daniel Gro{\ss}e and
Stephan Eggersgl{\"{u}}{\ss} and
Robert Wille and
Rolf Drechsler},
editor = {Christian Haubelt and
J{\"{u}}rgen Teich},
title = {Formal Verification on the Word Level using SAT-like Proof Techniques},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Erlangen, Germany, March 5-7,
2007},
series = {Berichte aus der Informatik},
pages = {81--90},
publisher = {Shaker},
year = {2007},
timestamp = {Thu, 11 Jul 2019 13:18:08 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/FeyGEWD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/SulflowFD07,
author = {Andr{\'{e}} S{\"{u}}lflow and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
editor = {Christian Haubelt and
J{\"{u}}rgen Teich},
title = {Verbesserte {SAT} basierte Fehlerdiagnose durch Widerspruchanalyse},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Erlangen, Germany, March 5-7,
2007},
series = {Berichte aus der Informatik},
pages = {101--110},
publisher = {Shaker},
year = {2007},
timestamp = {Thu, 28 Jun 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/SulflowFD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/EggersglussFDGHS07,
author = {Stephan Eggersgl{\"{u}}{\ss} and
G{\"{o}}rschwin Fey and
Rolf Drechsler and
Andreas Glowatz and
Friedrich Hapke and
J{\"{u}}rgen Schl{\"{o}}ffel},
title = {Combining Multi-Valued Logics in SAT-based {ATPG} for Path Delay Faults},
booktitle = {5th {ACM} {\&} {IEEE} International Conference on Formal Methods
and Models for Co-Design {(MEMOCODE} 2007), May 30 - June 1st, Nice,
France},
pages = {181--187},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/MEMCOD.2007.371226},
doi = {10.1109/MEMCOD.2007.371226},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/memocode/EggersglussFDGHS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WilleFGGED07,
author = {Robert Wille and
G{\"{o}}rschwin Fey and
Daniel Gro{\ss}e and
Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {{SWORD:} {A} {SAT} like Prover Using Word Level Information},
booktitle = {VLSI-SoC: Advanced Topics on Systems on a Chip - {A} Selection of
Extended Versions of the Best Papers of the Fourteenth International
Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2007),
October 15-17, 2007, Atlanta, {USA}},
series = {{IFIP}},
volume = {291},
pages = {1--17},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-0-387-89558-1\_10},
doi = {10.1007/978-0-387-89558-1\_10},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WilleFGGED07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WilleFGED07,
author = {Robert Wille and
G{\"{o}}rschwin Fey and
Daniel Gro{\ss}e and
Stephan Eggersgl{\"{u}}{\ss} and
Rolf Drechsler},
title = {{SWORD:} {A} {SAT} like prover using word level information},
booktitle = {{IFIP} VLSI-SoC 2007, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA,
15-17 October 2007},
pages = {88--93},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/VLSISOC.2007.4402478},
doi = {10.1109/VLSISOC.2007.4402478},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WilleFGED07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PandeyGD07,
author = {Sujan Pandey and
Christian Genz and
Rolf Drechsler},
title = {Co-synthesis of custom on-chip bus and memory for MPSoC architectures},
booktitle = {{IFIP} VLSI-SoC 2007, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA,
15-17 October 2007},
pages = {304--307},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/VLSISOC.2007.4402518},
doi = {10.1109/VLSISOC.2007.4402518},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/PandeyGD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/FeyWD07,
author = {G{\"{o}}rschwin Fey and
Tim Warode and
Rolf Drechsler},
title = {Reusing Learned Information in SAT-based {ATPG}},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {69--76},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.137},
doi = {10.1109/VLSID.2007.137},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/FeyWD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:journals/entcs/GlesnerKD07,
author = {Sabine Glesner and
Jens Knoop and
Rolf Drechsler},
editor = {Sabine Glesner and
Jens Knoop and
Rolf Drechsler},
title = {Preface},
booktitle = {Proceedings of the Workshop on Compiler Optimization meets Compiler
Verification, COCV@ETAPS 2007, Braga, Portugal, March 25, 2007},
series = {Electronic Notes in Theoretical Computer Science},
volume = {190},
number = {4},
pages = {1--2},
publisher = {Elsevier},
year = {2007},
url = {https://doi.org/10.1016/j.entcs.2007.09.003},
doi = {10.1016/J.ENTCS.2007.09.003},
timestamp = {Tue, 31 Jan 2023 16:00:46 +0100},
biburl = {https://dblp.org/rec/journals/entcs/GlesnerKD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/cocv/2007,
editor = {Sabine Glesner and
Jens Knoop and
Rolf Drechsler},
title = {Proceedings of the Workshop on Compiler Optimization meets Compiler
Verification, COCV@ETAPS 2007, Braga, Portugal, March 25, 2007},
series = {Electronic Notes in Theoretical Computer Science},
volume = {190},
number = {4},
publisher = {Elsevier},
year = {2007},
url = {https://www.sciencedirect.com/journal/electronic-notes-in-theoretical-computer-science/vol/190/issue/4},
timestamp = {Tue, 31 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cocv/2007.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/evoW/2007,
editor = {Mario Giacobini and
Anthony Brabazon and
Stefano Cagnoni and
Gianni Di Caro and
Rolf Drechsler and
Muddassar Farooq and
Andreas Fink and
Evelyne Lutton and
Penousal Machado and
Stefan Minner and
Michael O'Neill and
Juan Romero and
Franz Rothlauf and
Giovanni Squillero and
Hideyuki Takagi and
Sima Uyar and
Shengxiang Yang},
title = {Applications of Evolutinary Computing, EvoWorkshops 2007: EvoCoMnet,
EvoFIN, EvoIASP,EvoINTERACTION, EvoMUSART, EvoSTOC and EvoTransLog,
Valencia, Spain, April11-13, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4448},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-71805-5},
doi = {10.1007/978-3-540-71805-5},
isbn = {978-3-540-71804-8},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/evoW/2007.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FeyD06,
author = {G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {Minimizing the number of paths in BDDs: Theory and algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {1},
pages = {4--11},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.852662},
doi = {10.1109/TCAD.2005.852662},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FeyD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EbendtD06,
author = {R{\"{u}}diger Ebendt and
Rolf Drechsler},
title = {Effect of improved lower bounds in dynamic {BDD} reordering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {902--909},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854632},
doi = {10.1109/TCAD.2005.854632},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EbendtD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CirianiBD06,
author = {Valentina Ciriani and
Anna Bernasconi and
Rolf Drechsler},
title = {Testability of {SPP} Three-Level Logic Networks in Static Fault Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2241--2248},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.862746},
doi = {10.1109/TCAD.2005.862746},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CirianiBD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/FeySVD06,
author = {G{\"{o}}rschwin Fey and
Sean Safarpour and
Andreas G. Veneris and
Rolf Drechsler},
editor = {Georges G. E. Gielen},
title = {On the relation between simulation-based and SAT-based diagnosis},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {1139--1144},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.243999},
doi = {10.1109/DATE.2006.243999},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/FeySVD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/FeyGD06,
author = {G{\"{o}}rschwin Fey and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Georges G. E. Gielen},
title = {Avoiding false negatives in formal verification for protocol-driven
blocks},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {1225--1226},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.244074},
doi = {10.1109/DATE.2006.244074},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/FeyGD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BernasconiCDV06,
author = {Anna Bernasconi and
Valentina Ciriani and
Rolf Drechsler and
Tiziano Villa},
editor = {Georges G. E. Gielen},
title = {Efficient minimization of fully testable 2-SPP networks},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {1300--1305},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.244121},
doi = {10.1109/DATE.2006.244121},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/BernasconiCDV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/evoW/LogofatuD06,
author = {Doina Logofatu and
Rolf Drechsler},
editor = {Franz Rothlauf and
J{\"{u}}rgen Branke and
Stefano Cagnoni and
Ernesto Costa and
Carlos Cotta and
Rolf Drechsler and
Evelyne Lutton and
Penousal Machado and
Jason H. Moore and
Juan Romero and
George D. Smith and
Giovanni Squillero and
Hideyuki Takagi},
title = {Efficient Evolutionary Approaches for the Data Ordering Problem with
Inversion},
booktitle = {Applications of Evolutionary Computing, EvoWorkshops 2006: EvoBIO,
EvoCOMNET, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, and EvoSTOC,
Budapest, Hungary, April 10-12, 2006, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3907},
pages = {320--331},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11732242\_29},
doi = {10.1007/11732242\_29},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/evoW/LogofatuD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GrosseKD06,
author = {Daniel Gro{\ss}e and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
editor = {Gang Qu and
Yehea I. Ismail and
Narayanan Vijaykrishnan and
Hai Zhou},
title = {{HW/SW} co-verification of embedded systems using bounded model checking},
booktitle = {Proceedings of the 16th {ACM} Great Lakes Symposium on {VLSI} 2006,
Philadelphia, PA, USA, April 30 - May 1, 2006},
pages = {43--48},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1127908.1127920},
doi = {10.1145/1127908.1127920},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/GrosseKD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hvc/StaberFBD06,
author = {Stefan Staber and
G{\"{o}}rschwin Fey and
Roderick Bloem and
Rolf Drechsler},
editor = {Eyal Bin and
Avi Ziv and
Shmuel Ur},
title = {Automatic Fault Localization for Property Checking},
booktitle = {Hardware and Software, Verification and Testing, Second International
Haifa Verification Conference, {HVC} 2006, Haifa, Israel, October
23-26, 2006. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {4383},
pages = {50--64},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/978-3-540-70889-6\_4},
doi = {10.1007/978-3-540-70889-6\_4},
timestamp = {Tue, 14 May 2019 10:00:42 +0200},
biburl = {https://dblp.org/rec/conf/hvc/StaberFBD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/EbendtD06,
author = {R{\"{u}}diger Ebendt and
Rolf Drechsler},
title = {On the sensitivity of BDDs with respect to path-related objective
functions},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1693784},
doi = {10.1109/ISCAS.2006.1693784},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/EbendtD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SafarpourVD06,
author = {Sean Safarpour and
Andreas G. Veneris and
Rolf Drechsler},
title = {Integrating observability don't cares in all-solution {SAT} solvers},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692903},
doi = {10.1109/ISCAS.2006.1692903},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SafarpourVD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/FeySD06,
author = {G{\"{o}}rschwin Fey and
Junhao Shi and
Rolf Drechsler},
title = {Efficiency of Multi-Valued Encoding in SAT-based {ATPG}},
booktitle = {36th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2006), 17-20 May 2006, Singapore},
pages = {25},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISMVL.2006.19},
doi = {10.1109/ISMVL.2006.19},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/FeySD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/GenzD06,
author = {Christian Genz and
Rolf Drechsler},
title = {System Exploration of SystemC Designs},
booktitle = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2006), 2-3 March 2006, Karlsruhe, Germany},
pages = {335--342},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISVLSI.2006.87},
doi = {10.1109/ISVLSI.2006.87},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/GenzD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ki/EbendtD06,
author = {R{\"{u}}diger Ebendt and
Rolf Drechsler},
editor = {Christian Freksa and
Michael Kohlhase and
Kerstin Schill},
title = {A Framework for Quasi-exact Optimization Using Relaxed Best-First
Search},
booktitle = {{KI} 2006: Advances in Artificial Intelligence, 29th Annual German
Conference on AI, {KI} 2006, Bremen, Germany, June 14-17, 2006, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4314},
pages = {331--345},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/978-3-540-69912-5\_25},
doi = {10.1007/978-3-540-69912-5\_25},
timestamp = {Tue, 14 May 2019 10:00:49 +0200},
biburl = {https://dblp.org/rec/conf/ki/EbendtD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/FeyD06,
author = {G{\"{o}}rschwin Fey and
Rolf Drechsler},
editor = {Bernd Straube and
Martin Freibothe},
title = {SAT-based Calculation of Source Code Coverage for {BMC}},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Dresden, Germany, February 20-22,
2006},
pages = {163--170},
publisher = {Fraunhofer Institut f{\"{u}}r Integrierte Schaltungen},
year = {2006},
timestamp = {Thu, 28 Jun 2012 09:12:11 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/FeyD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/MurankoD06,
author = {Beate Muranko and
Rolf Drechsler},
editor = {Bernd Straube and
Martin Freibothe},
title = {Technische Dokumentation von Soft- und Hardware-Systemen: Die vergessene
Welt},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Dresden, Germany, February 20-22,
2006},
pages = {227--231},
publisher = {Fraunhofer Institut f{\"{u}}r Integrierte Schaltungen},
year = {2006},
timestamp = {Thu, 28 Jun 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/MurankoD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sfm/DrechslerF06,
author = {Rolf Drechsler and
G{\"{o}}rschwin Fey},
editor = {Marco Bernardo and
Alessandro Cimatti},
title = {Automatic Test Pattern Generation},
booktitle = {Formal Methods for Hardware Verification, 6th International School
on Formal Methods for the Design of Computer, Communication, and Software
Systems, {SFM} 2006, Bertinoro, Italy, May 22-27, 2006, Advanced Lectures},
series = {Lecture Notes in Computer Science},
volume = {3965},
pages = {30--55},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11757283\_2},
doi = {10.1007/11757283\_2},
timestamp = {Tue, 14 May 2019 10:00:44 +0200},
biburl = {https://dblp.org/rec/conf/sfm/DrechslerF06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MurankoD06,
author = {Beate Muranko and
Rolf Drechsler},
title = {Technical Documentation of Software and Hardware in Embedded Systems},
booktitle = {{IFIP} VLSI-SoC 2006, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Nice, France, 16-18
October 2006},
pages = {261--266},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/VLSISOC.2006.313244},
doi = {10.1109/VLSISOC.2006.313244},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/MurankoD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/DrechslerFK06,
author = {Rolf Drechsler and
G{\"{o}}rschwin Fey and
Sebastian Kinder},
title = {An Integrated Approach for Combining {BDD} and {SAT} Provers},
booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),
3-7 January 2006, Hyderabad, India},
pages = {237--242},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VLSID.2006.44},
doi = {10.1109/VLSID.2006.44},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/DrechslerFK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/evoW/2006,
editor = {Franz Rothlauf and
J{\"{u}}rgen Branke and
Stefano Cagnoni and
Ernesto Costa and
Carlos Cotta and
Rolf Drechsler and
Evelyne Lutton and
Penousal Machado and
Jason H. Moore and
Juan Romero and
George D. Smith and
Giovanni Squillero and
Hideyuki Takagi},
title = {Applications of Evolutionary Computing, EvoWorkshops 2006: EvoBIO,
EvoCOMNET, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, and EvoSTOC,
Budapest, Hungary, April 10-12, 2006, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3907},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11732242},
doi = {10.1007/11732242},
isbn = {3-540-33237-5},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/evoW/2006.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0012343,
author = {Bernd Becker and
Rolf Drechsler and
Paul Molitor},
title = {Technische Informatik - eine Einf{\"{u}}hrung},
series = {Pearson Studium},
publisher = {Pearson Education},
year = {2005},
isbn = {978-3-8273-7092-1},
timestamp = {Mon, 15 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0012343.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0016232,
author = {R{\"{u}}diger Ebendt and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {Advanced {BDD} optimization},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/b107399},
doi = {10.1007/B107399},
isbn = {978-0-387-25453-1},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0016232.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/DrechslerJS05,
author = {Rolf Drechsler and
Dragan Jankovic and
Radomir S. Stankovic},
title = {Generic Implementation of Multi-Valued Logic Decision Diagram Packages},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {11},
number = {1-2},
pages = {1--18},
year = {2005},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-11-number-1-2-2005/mvlsc-11-1-2-p-1-18/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/DrechslerJS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EbendtGD05,
author = {R{\"{u}}diger Ebendt and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Combining ordered best-first search with branch and bound for exact
{BDD} minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {10},
pages = {1515--1529},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2005.852053},
doi = {10.1109/TCAD.2005.852053},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EbendtGD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ShiFD05,
author = {Junhao Shi and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
editor = {Tingao Tang},
title = {Bridging fault testability of {BDD} circuits},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {188--191},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120801},
doi = {10.1145/1120725.1120801},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ShiFD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/EbendtD05,
author = {R{\"{u}}diger Ebendt and
Rolf Drechsler},
editor = {Tingao Tang},
title = {Lower bounds for dynamic {BDD} reordering},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {579--582},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120966},
doi = {10.1145/1120725.1120966},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/EbendtD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/charme/GrosseD05,
author = {Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Dominique Borrione and
Wolfgang J. Paul},
title = {Acceleration of SAT-Based Iterative Property Checking},
booktitle = {Correct Hardware Design and Verification Methods, 13th {IFIP} {WG}
10.5 Advanced Research Working Conference, {CHARME} 2005, Saarbr{\"{u}}cken,
Germany, October 3-6, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3725},
pages = {349--353},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11560548\_29},
doi = {10.1007/11560548\_29},
timestamp = {Tue, 14 May 2019 10:00:39 +0200},
biburl = {https://dblp.org/rec/conf/charme/GrosseD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gi/GrosseKD05,
author = {Daniel Gro{\ss}e and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
editor = {Armin B. Cremers and
Rainer Manthey and
Peter Martini and
Volker Steinhage},
title = {Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors},
booktitle = {35. Jahrestagung der Gesellschaft f{\"{u}}r Informatik, Informatik
LIVE!, {INFORMATIK} 2005, Bonn, Germany, September 19-22, 2005, Band
1},
series = {{LNI}},
volume = {{P-67}},
pages = {308--312},
publisher = {{GI}},
year = {2005},
url = {https://dl.gi.de/handle/20.500.12116/28048},
timestamp = {Tue, 04 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/gi/GrosseKD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SafarpourFVD05,
author = {Sean Safarpour and
G{\"{o}}rschwin Fey and
Andreas G. Veneris and
Rolf Drechsler},
editor = {John C. Lach and
Gang Qu and
Yehea I. Ismail},
title = {Utilizing don't care states in SAT-based bounded sequential problems},
booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
Chicago, Illinois, USA, April 17-19, 2005},
pages = {264--269},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1057661.1057725},
doi = {10.1145/1057661.1057725},
timestamp = {Wed, 15 Dec 2021 17:59:57 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/SafarpourFVD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/AliSVAD05,
author = {Moayad Fahim Ali and
Sean Safarpour and
Andreas G. Veneris and
Magdy S. Abadir and
Rolf Drechsler},
title = {Post-verification debugging of hierarchical designs},
booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
San Jose, CA, USA, November 6-10, 2005},
pages = {871--876},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCAD.2005.1560184},
doi = {10.1109/ICCAD.2005.1560184},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/AliSVAD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GrosseD05,
author = {Daniel Gro{\ss}e and
Rolf Drechsler},
title = {CheckSyC: an efficient property checker for {RTL} SystemC designs},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {4167--4170},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465549},
doi = {10.1109/ISCAS.2005.1465549},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GrosseD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/KinderFD05,
author = {Sebastian Kinder and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {Controlling the Memory During Manipulation of Word-Level Decision
Diagrams},
booktitle = {35th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2005), 18-21 May 2005, Calgary, Canada},
pages = {250--255},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISMVL.2005.15},
doi = {10.1109/ISMVL.2005.15},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/KinderFD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/EbendtD05,
author = {R{\"{u}}diger Ebendt and
Rolf Drechsler},
title = {Quasi-Exact {BDD} Minimization Using Relaxed Best-First Search},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {59--64},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.59},
doi = {10.1109/ISVLSI.2005.59},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/EbendtD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ShiFDGHS05,
author = {Junhao Shi and
G{\"{o}}rschwin Fey and
Rolf Drechsler and
Andreas Glowatz and
Friedrich Hapke and
J{\"{u}}rgen Schl{\"{o}}ffel},
title = {{PASSAT:} Efficient SAT-Based Test Pattern Generation for Industrial
Circuits},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {212--217},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.55},
doi = {10.1109/ISVLSI.2005.55},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ShiFDGHS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/AliSVAD05,
author = {Moayad Fahim Ali and
Sean Safarpour and
Andreas G. Veneris and
Magdy S. Abadir and
Rolf Drechsler},
editor = {Magdy S. Abadir and
Li{-}C. Wang},
title = {Post-Verification Debugging of Hierarchical Designs},
booktitle = {Sixth International Workshop on Microprocessor Test and Verification
{(MTV} 2005), Common Challenges and Solutions, 3-4 November 2005,
Austin, Texas, {USA}},
pages = {42--47},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTV.2005.18},
doi = {10.1109/MTV.2005.18},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/AliSVAD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/GrosseKD05,
author = {Daniel Gro{\ss}e and
Ulrich K{\"{u}}hne and
Rolf Drechsler},
editor = {Magdy S. Abadir and
Li{-}C. Wang},
title = {{HW/SW} Co-Verification of a {RISC} {CPU} using Bounded Model Checking},
booktitle = {Sixth International Workshop on Microprocessor Test and Verification
{(MTV} 2005), Common Challenges and Solutions, 3-4 November 2005,
Austin, Texas, {USA}},
pages = {133--137},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTV.2005.12},
doi = {10.1109/MTV.2005.12},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/GrosseKD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/KostarasV05,
author = {Rolf Drechsler and
G{\"{o}}rschwin Fey and
Christian Genz and
Daniel Gro{\ss}e},
title = {SyCE: An Integrated Environment for System Design in SystemC},
booktitle = {16th {IEEE} International Workshop on Rapid System Prototyping {(RSP}
2005), 8-10 June 2005, Montreal, Canada},
pages = {258--260},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/RSP.2005.46},
doi = {10.1109/RSP.2005.46},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rsp/KostarasV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/EbendtD05,
author = {R{\"{u}}diger Ebendt and
Rolf Drechsler},
editor = {Ricardo Augusto da Luz Reis and
Adam Osseiran and
Hans{-}J{\"{o}}rg Pfleiderer},
title = {Exact {BDD} Minimization for Path-Related Objective Functions},
booktitle = {VLSI-SoC: From Systems To Silicon, Proceedings of {IFIP} {TC} 10,
{WG} 10.5, Thirteenth International Conference on Very Large Scale
Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005,
Perth, Australia},
series = {{IFIP}},
volume = {240},
pages = {299--315},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/978-0-387-73661-7\_19},
doi = {10.1007/978-0-387-73661-7\_19},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/EbendtD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/evoW/2005,
editor = {Franz Rothlauf and
J{\"{u}}rgen Branke and
Stefano Cagnoni and
David W. Corne and
Rolf Drechsler and
Yaochu Jin and
Penousal Machado and
Elena Marchiori and
Juan Romero and
George D. Smith and
Giovanni Squillero},
title = {Applications of Evolutionary Computing, EvoWorkshops 2005: EvoBIO,
EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Lausanne, Switzerland,
March 30 - April 1, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3449},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/b106856},
doi = {10.1007/B106856},
isbn = {3-540-25396-3},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/evoW/2005.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/JankovicD04,
author = {Dragan Jankovic and
Rolf Drechsler},
title = {Method for Construction of Recursive Algorithms for Reed- Muller-Fourier
Polarity Matrices Calculation},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {10},
number = {1},
pages = {29--50},
year = {2004},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-10-number-1-2004/mvlsc-10-1-p-29-50/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/JankovicD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerSF04,
author = {Rolf Drechsler and
Junhao Shi and
G{\"{o}}rschwin Fey},
title = {Synthesis of fully testable circuits from BDDs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {23},
number = {3},
pages = {440--443},
year = {2004},
url = {https://doi.org/10.1109/TCAD.2004.823342},
doi = {10.1109/TCAD.2004.823342},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerSF04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/FeyD04,
author = {G{\"{o}}rschwin Fey and
Rolf Drechsler},
editor = {Masaharu Imai},
title = {Improving simulation-based verification by means of formal methods},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {640--643},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.116},
doi = {10.1109/ASPDAC.2004.116},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/FeyD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/EbendtGD04,
author = {R{\"{u}}diger Ebendt and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
editor = {Masaharu Imai},
title = {Minimization of the expected path length in BDDs based on local changes},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {865--870},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.135},
doi = {10.1109/ASPDAC.2004.135},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/EbendtGD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/EbendtGD04a,
author = {R{\"{u}}diger Ebendt and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
editor = {Masaharu Imai},
title = {Combining ordered best-first search with branch and bound for exact
{BDD} minimization},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {875--878},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.69},
doi = {10.1109/ASPDAC.2004.69},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/EbendtGD04a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SafarpourVDL04,
author = {Sean Safarpour and
Andreas G. Veneris and
Rolf Drechsler and
Joanne Lee},
title = {Managing Don't Cares in Boolean Satisfiability},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2004), 16-20 February 2004, Paris, France},
pages = {260--265},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DATE.2004.1268858},
doi = {10.1109/DATE.2004.1268858},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/SafarpourVDL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/FeySD04,
author = {G{\"{o}}rschwin Fey and
Junhao Shi and
Rolf Drechsler},
title = {{BDD} Circuit Optimization for Path Delay Fault Testability},
booktitle = {2004 Euromicro Symposium on Digital Systems Design {(DSD} 2004), Architectures,
Methods and Tools, 31 August - 3 September 2004, Rennes, France},
pages = {168--172},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DSD.2004.1333273},
doi = {10.1109/DSD.2004.1333273},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/FeySD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/evoW/DrechslerHFD04,
author = {Nicole Drechsler and
Mario Hilgemeier and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
editor = {G{\"{u}}nther R. Raidl and
Stefano Cagnoni and
J{\"{u}}rgen Branke and
David Corne and
Rolf Drechsler and
Yaochu Jin and
Colin G. Johnson and
Penousal Machado and
Elena Marchiori and
Franz Rothlauf and
George D. Smith and
Giovanni Squillero},
title = {Disjoint Sum of Product Minimization by Evolutionary Algorithms},
booktitle = {Applications of Evolutionary Computing, EvoWorkshops 2004: EvoBIO,
EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Coimbra, Portugal,
April 5-7, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3005},
pages = {198--207},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-24653-4\_21},
doi = {10.1007/978-3-540-24653-4\_21},
timestamp = {Tue, 14 May 2019 10:00:37 +0200},
biburl = {https://dblp.org/rec/conf/evoW/DrechslerHFD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/AliVSSDA04,
author = {Moayad Fahim Ali and
Andreas G. Veneris and
Alexander Smith and
Sean Safarpour and
Rolf Drechsler and
Magdy S. Abadir},
title = {Debugging sequential circuits using Boolean satisfiability},
booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004,
San Jose, CA, USA, November 7-11, 2004},
pages = {204--209},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2004},
url = {https://doi.org/10.1109/ICCAD.2004.1382572},
doi = {10.1109/ICCAD.2004.1382572},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/AliVSSDA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/EschbachDB04,
author = {Thomas Eschbach and
Rolf Drechsler and
Bernd Becker},
title = {Placement and routing optimization for circuits derived from BDDs},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {229--232},
publisher = {{IEEE}},
year = {2004},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/EschbachDB04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/JankovicSD04,
author = {Dragan Jankovic and
Radomir S. Stankovic and
Rolf Drechsler},
title = {Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Propertie},
booktitle = {34th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2004), 19-22 May 2004, Toronto, Canada},
pages = {223--228},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISMVL.2004.1319945},
doi = {10.1109/ISMVL.2004.1319945},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/JankovicSD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/FeyDC04,
author = {G{\"{o}}rschwin Fey and
Rolf Drechsler and
Maciej J. Ciesielski},
title = {Algorithms for Taylor Expansion Diagrams},
booktitle = {34th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2004), 19-22 May 2004, Toronto, Canada},
pages = {235--240},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISMVL.2004.1319947},
doi = {10.1109/ISMVL.2004.1319947},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/FeyDC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/Drechsler04,
author = {Rolf Drechsler},
editor = {Dominik Stoffel and
Wolfgang Kunz},
title = {Using Synthesis Techniques in {SAT} Solvers},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February
24-25, 2004},
pages = {165--173},
publisher = {Shaker},
year = {2004},
timestamp = {Thu, 28 Jun 2012 09:44:44 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/Drechsler04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/EbendtD04,
author = {R{\"{u}}diger Ebendt and
Rolf Drechsler},
editor = {Dominik Stoffel and
Wolfgang Kunz},
title = {A Tight Lower Bound for Dynamic {BDD} Reordering},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February
24-25, 2004},
pages = {233--242},
publisher = {Shaker},
year = {2004},
timestamp = {Thu, 28 Jun 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/EbendtD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/DrechslerGS04,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Burkhard Stubert},
editor = {Dominik Stoffel and
Wolfgang Kunz},
title = {Efficient (Non-)Reachability Analysis of Counterexamples},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February
24-25, 2004},
pages = {250--259},
publisher = {Shaker},
year = {2004},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/DrechslerGS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/GrosseD04,
author = {Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Checkers for SystemC designs},
booktitle = {2nd {ACM} {\&} {IEEE} International Conference on Formal Methods
and Models for Co-Design {(MEMOCODE} 2004), 23-25 June 2004, San Diego,
California, USA, Proceedings},
pages = {171--178},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/MEMCOD.2004.1459851},
doi = {10.1109/MEMCOD.2004.1459851},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/memocode/GrosseD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/AliVSASDS04,
author = {Moayad Fahim Ali and
Andreas G. Veneris and
Sean Safarpour and
Magdy S. Abadir and
Rolf Drechsler and
Alexander Smith},
title = {Debugging Sequential Circuits Using Boolean Satisfiability},
booktitle = {Fifth International Workshop on Microprocessor Test and Verification
{(MTV} 2004), Common Challenges and Solutions, 08-10 September 2004,
Austin, Texas, {USA}},
pages = {44--49},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/MTV.2004.7},
doi = {10.1109/MTV.2004.7},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/AliVSASDS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/Drechsler04,
author = {Rolf Drechsler},
title = {Towards Formal Verification on the System Level},
booktitle = {15th {IEEE} International Workshop on Rapid System Prototyping {(RSP}
2004), 28-30 June 2004, Geneva, Switzerland},
pages = {2--5},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/RSP.2004.43},
doi = {10.1109/RSP.2004.43},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rsp/Drechsler04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/evoW/2004,
editor = {G{\"{u}}nther R. Raidl and
Stefano Cagnoni and
J{\"{u}}rgen Branke and
David Corne and
Rolf Drechsler and
Yaochu Jin and
Colin G. Johnson and
Penousal Machado and
Elena Marchiori and
Franz Rothlauf and
George D. Smith and
Giovanni Squillero},
title = {Applications of Evolutionary Computing, EvoWorkshops 2004: EvoBIO,
EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Coimbra, Portugal,
April 5-7, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3005},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/b96500},
doi = {10.1007/B96500},
isbn = {3-540-21378-3},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/evoW/2004.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/fmsd/KeimDBMM03,
author = {Martin Keim and
Rolf Drechsler and
Bernd Becker and
Michael Martin and
Paul Molitor},
title = {Polynomial Formal Verification of Multipliers},
journal = {Formal Methods Syst. Des.},
volume = {22},
number = {1},
pages = {39--58},
year = {2003},
url = {https://doi.org/10.1023/A:1021752130394},
doi = {10.1023/A:1021752130394},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/fmsd/KeimDBMM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/it/GrosseD03,
author = {Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen
in SystemC},
journal = {it Inf. Technol.},
volume = {45},
number = {4},
pages = {219--226},
year = {2003},
url = {https://doi.org/10.1524/itit.45.4.219.22731},
doi = {10.1524/ITIT.45.4.219.22731},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/it/GrosseD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/DrechslerGELA03,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Thomas Eschbach and
Lothar Linhard and
Gerhard Angst},
title = {Recursive bi-partitioning of netlists for large number of partitions},
journal = {J. Syst. Archit.},
volume = {49},
number = {12-15},
pages = {521--528},
year = {2003},
url = {https://doi.org/10.1016/S1383-7621(03)00093-6},
doi = {10.1016/S1383-7621(03)00093-6},
timestamp = {Tue, 19 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/DrechslerGELA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/SchmiedleDB03,
author = {Frank Schmiedle and
Rolf Drechsler and
Bernd Becker},
title = {Exact Routing with Search Space Reduction},
journal = {{IEEE} Trans. Computers},
volume = {52},
number = {6},
pages = {815--825},
year = {2003},
url = {https://doi.org/10.1109/TC.2003.1204836},
doi = {10.1109/TC.2003.1204836},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/SchmiedleDB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/GuntherD03,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Efficient Minimization and Manipulation of Linearly Transformed Binary
Decision Diagrams},
journal = {{IEEE} Trans. Computers},
volume = {52},
number = {9},
pages = {1196--1209},
year = {2003},
url = {https://doi.org/10.1109/TC.2003.1228514},
doi = {10.1109/TC.2003.1228514},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/GuntherD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EbendtGD03,
author = {R{\"{u}}diger Ebendt and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {An improved branch and bound algorithm for exact {BDD} minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {12},
pages = {1657--1663},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.819427},
doi = {10.1109/TCAD.2003.819427},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EbendtGD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/appinf/DrechslerD03,
author = {Rolf Drechsler and
Nicole Drechsler},
editor = {M. H. Hamza},
title = {Minimization of Transitions by Complementation and Resequencing using
Evolutionary Algorithms},
booktitle = {The 21st {IASTED} International Multi-Conference on Applied Informatics
{(AI} 2003), February 10-13, 2003, Innsbruck, Austria},
pages = {109--114},
publisher = {{IASTED/ACTA} Press},
year = {2003},
timestamp = {Tue, 15 Jul 2003 16:03:54 +0200},
biburl = {https://dblp.org/rec/conf/appinf/DrechslerD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/ShiFD03,
author = {Junhao Shi and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {{BDD} Based Synthesis of Symmetric Functions with Full Path-Delay
Fault Testability},
booktitle = {12th Asian Test Symposium {(ATS} 2003), 17-19 November 2003, Xian,
China},
pages = {290--293},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ATS.2003.1250825},
doi = {10.1109/ATS.2003.1250825},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/ShiFD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cec/HilgemeierDD03,
author = {Mario Hilgemeier and
Nicole Drechsler and
Rolf Drechsler},
title = {Minimizing the number of one-paths in BDDs by an evolutionary algorithm},
booktitle = {Proceedings of the {IEEE} Congress on Evolutionary Computation, {CEC}
2003, Canberra, Australia, December 8-12, 2003},
pages = {1724--1731},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/CEC.2003.1299881},
doi = {10.1109/CEC.2003.1299881},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cec/HilgemeierDD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/EbendtGD03,
author = {R{\"{u}}diger Ebendt and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Combination of Lower Bounds in Exact {BDD} Minimization},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {10758--10763},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10040},
doi = {10.1109/DATE.2003.10040},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/EbendtGD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/HilgemeierDD03,
author = {Mario Hilgemeier and
Nicole Drechsler and
Rolf Drechsler},
title = {Fast Heuristics for the Edge Coloring of Large Graphs},
booktitle = {2003 Euromicro Symposium on Digital Systems Design {(DSD} 2003), Architectures,
Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey},
pages = {230--239},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/DSD.2003.1231932},
doi = {10.1109/DSD.2003.1231932},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/HilgemeierDD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/evoW/DrechslerD03,
author = {Rolf Drechsler and
Nicole Drechsler},
editor = {G{\"{u}}nther R. Raidl and
Jean{-}Arcady Meyer and
Martin Middendorf and
Stefano Cagnoni and
Juan J. Romero Cardalda and
David Corne and
Jens Gottlieb and
Agn{\`{e}}s Guillot and
Emma Hart and
Colin G. Johnson and
Elena Marchiori},
title = {{GAME-HDL:} Implementation of Evolutionary Algorithms Using Hardware
Description Languages},
booktitle = {Applications of Evolutionary Computing, EvoWorkshop 2003: EvoBIO,
EvoCOP, EvoIASP, EvoMUSART, EvoROB, and EvoSTIM, Essex, UK, April
14-16, 2003, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2611},
pages = {378--387},
publisher = {Springer},
year = {2003},
url = {https://doi.org/10.1007/3-540-36605-9\_35},
doi = {10.1007/3-540-36605-9\_35},
timestamp = {Tue, 14 May 2019 10:00:37 +0200},
biburl = {https://dblp.org/rec/conf/evoW/DrechslerD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/GrosseDLA03,
author = {Daniel Gro{\ss}e and
Rolf Drechsler and
Lothar Linhard and
Gerhard Angst},
title = {Efficient Automatic Visualization of SystemC Designs},
booktitle = {Forum on specification and Design Languages, {FDL} 2003, September
23-26, 2003, Frankfurt, Germany, Proceedings},
pages = {646--658},
publisher = {{ECSI}},
year = {2003},
url = {http://www.ecsi-association.org/ecsi/main.asp?l1=library\&\#38;fn=def\&\#38;id=786},
timestamp = {Thu, 03 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fdl/GrosseDLA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/DrechslerSF03,
author = {Rolf Drechsler and
Junhao Shi and
G{\"{o}}rschwin Fey},
editor = {Mircea R. Stan and
David Garrett and
Kazuo Nakajima},
title = {MuTaTe: an efficient design for testability technique for multiplexor
based circuits},
booktitle = {Proceedings of the 13th {ACM} Great Lakes Symposium on {VLSI} 2003,
Washington, DC, USA, April 28-29, 2003},
pages = {80--83},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/764808.764830},
doi = {10.1145/764808.764830},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/DrechslerSF03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/GrosseD03,
author = {Daniel Gro{\ss}e and
Rolf Drechsler},
title = {BDD-based verification of scalable designs},
booktitle = {Eighth {IEEE} International High-Level Design Validation and Test
Workshop 2003, San Francisco, CA, USA, November 12-14, 2003},
pages = {123--128},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/HLDVT.2003.1252485},
doi = {10.1109/HLDVT.2003.1252485},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/GrosseD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GrosseD03,
author = {Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Formal verification of {LTL} formulas for SystemC designs},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {245--248},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1206243},
doi = {10.1109/ISCAS.2003.1206243},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GrosseD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/Drechsler03,
author = {Rolf Drechsler},
title = {Synthesizing checkers for on-line verification of System-on-Chip designs},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {748--751},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1206281},
doi = {10.1109/ISCAS.2003.1206281},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/Drechsler03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/PopelD03,
author = {Denis V. Popel and
Rolf Drechsler},
title = {Efficient Minimization of Multiple-valued Decision Diagrams for Incompletely
Specified Functions},
booktitle = {33rd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2003), 16-19 May 2003, Tokyo, Japan},
pages = {241--246},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ISMVL.2003.1201412},
doi = {10.1109/ISMVL.2003.1201412},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/PopelD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/GrosseFD03,
author = {Daniel Gro{\ss}e and
G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {Modeling Multi-Valued Circuits in SystemC},
booktitle = {33rd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2003), 16-19 May 2003, Tokyo, Japan},
pages = {281--286},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ISMVL.2003.1201418},
doi = {10.1109/ISMVL.2003.1201418},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/GrosseFD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/FeyKD03,
author = {G{\"{o}}rschwin Fey and
Sebastian Kinder and
Rolf Drechsler},
title = {Using Games for Benchmarking and Representing the Complete Solution
Space using Symbolic Techniques},
booktitle = {33rd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2003), 16-19 May 2003, Tokyo, Japan},
pages = {361--366},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ISMVL.2003.1201429},
doi = {10.1109/ISMVL.2003.1201429},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/FeyKD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/MillerD03a,
author = {D. Michael Miller and
Rolf Drechsler},
title = {Augmented Sifting of Multiple-Valued Decision Diagrams},
booktitle = {33rd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2003), 16-19 May 2003, Tokyo, Japan},
pages = {375--382},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ISMVL.2003.1201431},
doi = {10.1109/ISMVL.2003.1201431},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/MillerD03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/GrosseD03,
author = {Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Rolf Drechsler},
title = {Formale Verifikation von LTL-Formeln f{\"{u}}r SystemC-Beschreibungen},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25,
2003},
pages = {229--238},
publisher = {Shaker},
year = {2003},
timestamp = {Thu, 28 Jun 2012 12:33:11 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/GrosseD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/FeyD03,
author = {G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {Finding Good Counter-Examples to Aid Design Verification},
booktitle = {1st {ACM} {\&} {IEEE} International Conference on Formal Methods
and Models for Co-Design {(MEMOCODE} 2003), 24-26 June 2003, Mont
Saint-Michel, France, Proceedings},
pages = {51},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MEMCOD.2003.1210088},
doi = {10.1109/MEMCOD.2003.1210088},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/memocode/FeyD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DrechslerD03a,
author = {Nicole Drechsler and
Rolf Drechsler},
editor = {Manfred Glesner and
Ricardo Augusto da Luz Reis and
Leandro Soares Indrusiak and
Vincent John Mooney III and
Hans Eveking},
title = {Exploration of Sequential Depth by Evolutionary Algorithms},
booktitle = {{VLSI-SOC:} From Systems to Chips - {IFIP} {TC} 10/ {WG} 10.5 Twelfth
International Conference on Very Large Scale Integration of System
on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany},
series = {{IFIP}},
volume = {200},
pages = {73--83},
publisher = {Springer},
year = {2003},
url = {https://doi.org/10.1007/0-387-33403-3\_5},
doi = {10.1007/0-387-33403-3\_5},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DrechslerD03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/DrechslerD03,
author = {Nicole Drechsler and
Rolf Drechsler},
editor = {Manfred Glesner and
Ricardo Augusto da Luz Reis and
Hans Eveking and
Vincent John Mooney III and
Leandro Soares Indrusiak and
Peter Zipf},
title = {Exploration of Sequential Depth by Evolutionary Algorithms},
booktitle = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Darmstadt, Germany,
1-3 December 2003},
pages = {81--85},
publisher = {Technische Universit{\"{a}}t Darmstadt, Insitute of Microelectronic
Systems},
year = {2003},
timestamp = {Thu, 07 Oct 2004 09:29:26 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/DrechslerD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CirianiBD03a,
author = {Valentina Ciriani and
Anna Bernasconi and
Rolf Drechsler},
editor = {Manfred Glesner and
Ricardo Augusto da Luz Reis and
Leandro Soares Indrusiak and
Vincent John Mooney III and
Hans Eveking},
title = {Stuck-At-Fault Testability of {SPP} Three-Level Logic Forms},
booktitle = {{VLSI-SOC:} From Systems to Chips - {IFIP} {TC} 10/ {WG} 10.5 Twelfth
International Conference on Very Large Scale Integration of System
on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany},
series = {{IFIP}},
volume = {200},
pages = {299--313},
publisher = {Springer},
year = {2003},
url = {https://doi.org/10.1007/0-387-33403-3\_19},
doi = {10.1007/0-387-33403-3\_19},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CirianiBD03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CirianiBD03,
author = {Valentina Ciriani and
Anna Bernasconi and
Rolf Drechsler},
editor = {Manfred Glesner and
Ricardo Augusto da Luz Reis and
Hans Eveking and
Vincent John Mooney III and
Leandro Soares Indrusiak and
Peter Zipf},
title = {Testability of {SPP} Three-Level Logic Networks},
booktitle = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Darmstadt, Germany,
1-3 December 2003},
pages = {331--336},
publisher = {Technische Universit{\"{a}}t Darmstadt, Insitute of Microelectronic
Systems},
year = {2003},
timestamp = {Sat, 23 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/CirianiBD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mbmv/2003,
editor = {Rolf Drechsler},
title = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25,
2003},
publisher = {Shaker},
year = {2003},
timestamp = {Thu, 28 Jun 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/2003.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/gpem/SchmiedleDGD02,
author = {Frank Schmiedle and
Nicole Drechsler and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Heuristic Learning Based on Genetic Programming},
journal = {Genet. Program. Evolvable Mach.},
volume = {3},
number = {4},
pages = {363--388},
year = {2002},
url = {https://doi.org/10.1023/A:1020988925923},
doi = {10.1023/A:1020988925923},
timestamp = {Tue, 01 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/gpem/SchmiedleDGD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/JungLPD02,
author = {Migyoung Jung and
Gueesang Lee and
Sungju Park and
Rolf Drechsler},
title = {A Genetic Algorithm for the Minimization of OPKFDDs},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {85-A},
number = {12},
pages = {2943--2945},
year = {2002},
url = {http://search.ieice.org/bin/summary.php?id=e85-a\_12\_2943},
timestamp = {Wed, 09 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/JungLPD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuntherD02,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Minimization of free BDDs},
journal = {Integr.},
volume = {32},
number = {1-2},
pages = {41--59},
year = {2002},
url = {https://doi.org/10.1016/S0167-9260(02)00041-X},
doi = {10.1016/S0167-9260(02)00041-X},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GuntherD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Drechsler02,
author = {Rolf Drechsler},
title = {Verifying integrity of decision diagrams},
journal = {Integr.},
volume = {32},
number = {1-2},
pages = {61--75},
year = {2002},
url = {https://doi.org/10.1016/S0167-9260(02)00042-1},
doi = {10.1016/S0167-9260(02)00042-1},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Drechsler02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DrechslerGH02,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Stefan H{\"{o}}reth},
title = {Minimization of Word-Level Decision Diagrams},
journal = {Integr.},
volume = {33},
number = {1-2},
pages = {39--70},
year = {2002},
url = {https://doi.org/10.1016/S0167-9260(02)00047-0},
doi = {10.1016/S0167-9260(02)00047-0},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DrechslerGH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/PerkowskiFCD02,
author = {Marek A. Perkowski and
Bogdan J. Falkowski and
Malgorzata Chrzanowska{-}Jeske and
Rolf Drechsler},
title = {Efficient Algorithms for Creation of Linearly-independent Decision
Diagrams and their Mapping to Regular Layouts},
journal = {{VLSI} Design},
volume = {14},
number = {1},
pages = {35--52},
year = {2002},
url = {https://doi.org/10.1080/10655140290009792},
doi = {10.1080/10655140290009792},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/PerkowskiFCD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ThorntonDG02,
author = {Mitchell A. Thornton and
Rolf Drechsler and
Wolfgang G{\"{u}}nther},
title = {Logic Circuit Equivalence Checking Using Haar Spectral Coefficients
and Partial BDDs},
journal = {{VLSI} Design},
volume = {14},
number = {1},
pages = {53--64},
year = {2002},
url = {https://doi.org/10.1080/10655140290009800},
doi = {10.1080/10655140290009800},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ThorntonDG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/DrechslerGELA02,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Thomas Eschbach and
Lothar Linhard and
Gerhard Angst},
title = {Recursive Bi-Partitioning of Netlists for Large Number of Partitions},
booktitle = {2002 Euromicro Symposium on Digital Systems Design {(DSD} 2002), Systems-on-Chip,
4-6 September 2002, Dortmund, Germany},
pages = {38--44},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DSD.2002.1115349},
doi = {10.1109/DSD.2002.1115349},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/DrechslerGELA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/JankovicSD02,
author = {Dragan Jankovic and
Radomir S. Stankovic and
Rolf Drechsler},
title = {Decision Diagram Optimization Using Copy Properties},
booktitle = {2002 Euromicro Symposium on Digital Systems Design {(DSD} 2002), Systems-on-Chip,
4-6 September 2002, Dortmund, Germany},
pages = {236--243},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DSD.2002.1115374},
doi = {10.1109/DSD.2002.1115374},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/JankovicSD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/DrechslerG02,
author = {Rolf Drechsler and
Daniel Gro{\ss}e},
title = {Reachability Analysis for Formal Verification of SystemC},
booktitle = {2002 Euromicro Symposium on Digital Systems Design {(DSD} 2002), Systems-on-Chip,
4-6 September 2002, Dortmund, Germany},
pages = {337--340},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DSD.2002.1115387},
doi = {10.1109/DSD.2002.1115387},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/DrechslerG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gd/EschbachGDB02,
author = {Thomas Eschbach and
Wolfgang G{\"{u}}nther and
Rolf Drechsler and
Bernd Becker},
editor = {Stephen G. Kobourov and
Michael T. Goodrich},
title = {Crossing Reduction by Windows Optimization},
booktitle = {Graph Drawing, 10th International Symposium, {GD} 2002, Irvine, CA,
USA, August 26-28, 2002, Revised Papers},
series = {Lecture Notes in Computer Science},
volume = {2528},
pages = {285--294},
publisher = {Springer},
year = {2002},
url = {https://doi.org/10.1007/3-540-36151-0\_27},
doi = {10.1007/3-540-36151-0\_27},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/gd/EschbachGDB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/TownsendTDM02,
author = {Whitney J. Townsend and
Mitchell A. Thornton and
Rolf Drechsler and
D. Michael Miller},
editor = {Kanad Ghose and
Patrick H. Madden and
Vivek De and
Peter M. Kogge},
title = {Computing walsh, arithmetic, and reed-muller spectral decision diagrams
using graph transformations},
booktitle = {Proceedings of the 12th {ACM} Great Lakes Symposium on {VLSI} 2002,
New York, NY, USA, April 18-19, 2002},
pages = {178--183},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505306.505344},
doi = {10.1145/505306.505344},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/TownsendTDM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KerttuLTD02,
author = {Mikael Kerttu and
Per Lindgren and
Mitchell A. Thornton and
Rolf Drechsler},
title = {Switching activity estimation of finite state machines for low power
synthesis},
booktitle = {Proceedings of the 2002 International Symposium on Circuits and Systems,
{ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
pages = {65--68},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ISCAS.2002.1010389},
doi = {10.1109/ISCAS.2002.1010389},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KerttuLTD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/MillerD02,
author = {D. Michael Miller and
Rolf Drechsler},
title = {On the Construction of Multiple-Valued Decision Diagrams},
booktitle = {32nd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2002), May 15-18, 2002, Boston, Massachusetts, {USA}},
pages = {245--253},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ISMVL.2002.1011095},
doi = {10.1109/ISMVL.2002.1011095},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/MillerD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/Drechsler02,
author = {Rolf Drechsler},
title = {Evaluation of Static Variable Ordering Heuristics for {MDD} Construction},
booktitle = {32nd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2002), May 15-18, 2002, Boston, Massachusetts, {USA}},
pages = {254--260},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ISMVL.2002.1011096},
doi = {10.1109/ISMVL.2002.1011096},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/Drechsler02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/RedaDO02,
author = {Sherief Reda and
Rolf Drechsler and
Alex Orailoglu},
title = {On the Relation between {SAT} and BDDs for Equivalence Checking},
booktitle = {3rd International Symposium on Quality of Electronic Design, {ISQED}
2002, San Jose, CA, USA, March 18-21, 2002},
pages = {394--399},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ISQED.2002.996778},
doi = {10.1109/ISQED.2002.996778},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/RedaDO02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ThorntonDM02,
author = {Mitchell A. Thornton and
Rolf Drechsler and
D. Michael Miller},
title = {Multi-Output Timed Shannon Circuits},
booktitle = {2002 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2002), 25-26 April 2002, Pittsburgh, PA, {USA}},
pages = {47--52},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ISVLSI.2002.1016873},
doi = {10.1109/ISVLSI.2002.1016873},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ThorntonDM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/KerttuLDT02,
author = {Mikael Kerttu and
Per Lindgren and
Rolf Drechsler and
Mitchell A. Thornton},
title = {Low Power Optimization Techniques for {BDD} Mapped Finite State Machines},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {143--148},
year = {2002},
timestamp = {Sun, 04 Aug 2019 18:01:44 +0200},
biburl = {https://dblp.org/rec/conf/iwls/KerttuLDT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/EnglertBD02,
author = {Klaus{-}J{\"{u}}rgen Englert and
Bernd Becker and
Rolf Drechsler},
editor = {J{\"{u}}rgen Ruf},
title = {Symbolic Simulation of Algorithms Specified in {HDL}},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), T{\"{u}}bingen, Germany,
February 25-27, 2002},
pages = {113--122},
publisher = {Shaker},
year = {2002},
timestamp = {Fri, 20 Jan 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/EnglertBD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/DrechslerR02,
author = {Rolf Drechsler and
Jochen R{\"{o}}mmler},
editor = {J{\"{u}}rgen Ruf},
title = {Implementation and Visualization of a {BDD} Package in {JAVA}},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), T{\"{u}}bingen, Germany,
February 25-27, 2002},
pages = {219--228},
publisher = {Shaker},
year = {2002},
timestamp = {Thu, 28 Jun 2012 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/DrechslerR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/FeyD02,
author = {G{\"{o}}rschwin Fey and
Rolf Drechsler},
title = {Minimizing the Number of Paths in BDDs},
booktitle = {Proceedings of the 15th Annual Symposium on Integrated Circuits and
Systems Design, {SBCCI} 2002, Porto Alegre, Brazil, September 9-14,
2002},
pages = {359--364},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://dl.acm.org/doi/10.5555/827246.827403},
doi = {10.5555/827246.827403},
timestamp = {Fri, 10 Jun 2022 11:12:41 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/FeyD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/BrinkmannD02,
author = {Raik Brinkmann and
Rolf Drechsler},
title = {RTL-Datapath Verification using Integer Linear Programming},
booktitle = {Proceedings of the 7th Asia and South Pacific Design Automation Conference
{(ASP-DAC} 2002), and the 15th International Conference on {VLSI}
Design {(VLSI} Design 2002), Bangalore, India, January 7-11, 2002},
pages = {741--746},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ASPDAC.2002.995022},
doi = {10.1109/ASPDAC.2002.995022},
timestamp = {Mon, 14 Nov 2022 15:28:09 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/BrinkmannD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0006031,
author = {Mitchell Aaron Thornton and
Rolf Drechsler and
D. Michael Miller},
title = {Spectral techniques in {VLSI} {CAD}},
publisher = {Kluwer},
year = {2001},
isbn = {978-0-7923-7433-6},
timestamp = {Fri, 15 Apr 2011 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0006031.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/KeimDDB01,
author = {Martin Keim and
Nicole Drechsler and
Rolf Drechsler and
Bernd Becker},
title = {Combining GAs and Symbolic Methods for High Quality Tests of Sequential
Circuits},
journal = {J. Electron. Test.},
volume = {17},
number = {1},
pages = {37--51},
year = {2001},
url = {https://doi.org/10.1023/A:1011193725824},
doi = {10.1023/A:1011193725824},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/et/KeimDDB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DrechslerG01,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther},
title = {History-based dynamic {BDD} minimization},
journal = {Integr.},
volume = {31},
number = {1},
pages = {51--63},
year = {2001},
url = {https://doi.org/10.1016/S0167-9260(01)00021-9},
doi = {10.1016/S0167-9260(01)00021-9},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DrechslerG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/it/Drechsler01,
author = {Rolf Drechsler},
title = {{\"{A}}quivalenzvergleich digitaler Schaltungen im industriellen
Umfeld (Equivalence Checking of Digital Circuits in an Industrial
Environment)},
journal = {Informationstechnik Tech. Inform.},
volume = {43},
number = {4},
pages = {200--205},
year = {2001},
url = {https://doi.org/10.1524/itit.2001.43.4.200},
doi = {10.1524/ITIT.2001.43.4.200},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/it/Drechsler01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sttt/DrechslerS01,
author = {Rolf Drechsler and
Detlef Sieling},
title = {Binary decision diagrams in theory and practice},
journal = {Int. J. Softw. Tools Technol. Transf.},
volume = {3},
number = {2},
pages = {112--136},
year = {2001},
url = {https://doi.org/10.1007/s100090100056},
doi = {10.1007/S100090100056},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sttt/DrechslerS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/JankovicSD01,
author = {Dragan Jankovic and
Radomir S. Stankovic and
Rolf Drechsler},
title = {Decision Diagram Method for Calculation of Pruned Walsh Transform},
journal = {{IEEE} Trans. Computers},
volume = {50},
number = {2},
pages = {147--157},
year = {2001},
url = {https://doi.org/10.1109/12.908990},
doi = {10.1109/12.908990},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/JankovicSD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerGS01,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Fabio Somenzi},
title = {Using lower bounds during dynamic {BDD} minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {51--57},
year = {2001},
url = {https://doi.org/10.1109/43.905674},
doi = {10.1109/43.905674},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerGS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/acs2/JohannsenD01,
author = {Peer Johannsen and
Rolf Drechsler},
editor = {Jerzy Soldek and
Jerzy Pejas},
title = {Utilizing High-Level Information for Formal Hardware Verification},
booktitle = {Advanced Computer Systems, Eighth International Conference, {ACS}
2001, Mielno, Poland, October 17-19, 2001 Proceedings},
pages = {419--431},
publisher = {Springer},
year = {2001},
url = {https://doi.org/10.1007/978-1-4419-8530-9\_34},
doi = {10.1007/978-1-4419-8530-9\_34},
timestamp = {Thu, 24 Jan 2019 18:01:15 +0100},
biburl = {https://dblp.org/rec/conf/acs2/JohannsenD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/acs2/JankovicSD01,
author = {Dragan Jankovic and
Radomir S. Stankovic and
Rolf Drechsler},
editor = {Jerzy Soldek and
Jerzy Pejas},
title = {Tabular Techniques for {MV} Logic},
booktitle = {Advanced Computer Systems, Eighth International Conference, {ACS}
2001, Mielno, Poland, October 17-19, 2001 Proceedings},
pages = {433--448},
publisher = {Springer},
year = {2001},
url = {https://doi.org/10.1007/978-1-4419-8530-9\_35},
doi = {10.1007/978-1-4419-8530-9\_35},
timestamp = {Thu, 24 Jan 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/acs2/JankovicSD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LindgrenKTD01,
author = {Per Lindgren and
Mikael Kerttu and
Mitchell A. Thornton and
Rolf Drechsler},
editor = {Satoshi Goto},
title = {Low power optimization technique for {BDD} mapped circuits},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {615--621},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370564},
doi = {10.1145/370155.370564},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LindgrenKTD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ThorntonD01,
author = {Mitchell A. Thornton and
Rolf Drechsler},
editor = {Wolfgang Nebel and
Ahmed Jerraya},
title = {Spectral decision diagrams using graph transformations},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2001, Munich, Germany, March 12-16, 2001},
pages = {713--719},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DATE.2001.915106},
doi = {10.1109/DATE.2001.915106},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ThorntonD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/BeckerEDG01,
author = {Bernd Becker and
Thomas Eschbach and
Rolf Drechsler and
Wolfgang G{\"{u}}nther},
title = {Greedy{\_}IIP: Partitioning Large Graphs by Greedy Iterative Improvement},
booktitle = {Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001),
4-6 September 2001, Warsaw, Poland},
pages = {54--61},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DSD.2001.952117},
doi = {10.1109/DSD.2001.952117},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/BeckerEDG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/JungLPD01,
author = {Migyoung Jung and
Gueesang Lee and
Sungju Park and
Rolf Drechsler},
title = {Minimization of OPKFDDs Using Genetic Algorithms},
booktitle = {Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001),
4-6 September 2001, Warsaw, Poland},
pages = {72--78},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DSD.2001.952120},
doi = {10.1109/DSD.2001.952120},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/JungLPD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/DrechslerGLA01,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Lothar Linhard and
Gerhard Angst},
title = {Level Assignment for Displaying Combinational Logic},
booktitle = {Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001),
4-6 September 2001, Warsaw, Poland},
pages = {148--151},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DSD.2001.952262},
doi = {10.1109/DSD.2001.952262},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/DrechslerGLA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/emo/DrechslerDB01,
author = {Nicole Drechsler and
Rolf Drechsler and
Bernd Becker},
editor = {Eckart Zitzler and
Kalyanmoy Deb and
Lothar Thiele and
Carlos A. Coello Coello and
David Corne},
title = {Multi-objective Optimisation Based on Relation \emph{Favour}},
booktitle = {Evolutionary Multi-Criterion Optimization, First International Conference,
{EMO} 2001, Zurich, Switzerland, March 7-9, 2001, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1993},
pages = {154--166},
publisher = {Springer},
year = {2001},
url = {https://doi.org/10.1007/3-540-44719-9\_11},
doi = {10.1007/3-540-44719-9\_11},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/emo/DrechslerDB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurogp/DrechslerSGD01,
author = {Nicole Drechsler and
Frank Schmiedle and
Daniel Gro{\ss}e and
Rolf Drechsler},
editor = {Julian F. Miller and
Marco Tomassini and
Pier Luca Lanzi and
Conor Ryan and
Andrea Tettamanzi and
William B. Langdon},
title = {Heuristic Learning Based on Genetic Programming},
booktitle = {Genetic Programming, 4th European Conference, EuroGP 2001, Lake Como,
Italy, April 18-20, 2001, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2038},
pages = {1--10},
publisher = {Springer},
year = {2001},
url = {https://doi.org/10.1007/3-540-45355-5\_1},
doi = {10.1007/3-540-45355-5\_1},
timestamp = {Tue, 14 May 2019 10:00:50 +0200},
biburl = {https://dblp.org/rec/conf/eurogp/DrechslerSGD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fuzzy/SchmiedleGDB01,
author = {Frank Schmiedle and
Daniel Gro{\ss}e and
Rolf Drechsler and
Bernd Becker},
editor = {Bernd Reusch},
title = {Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning
Heuristics},
booktitle = {Computational Intelligence, Theory and Applications, International
Conference, 7th Fuzzy Days, Dortmund, Germany, October 1-3, 2001,
Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2206},
pages = {479--491},
publisher = {Springer},
year = {2001},
url = {https://doi.org/10.1007/3-540-45493-4\_49},
doi = {10.1007/3-540-45493-4\_49},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fuzzy/SchmiedleGDB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip10-5/JohannsenD01,
author = {Peer Johannsen and
Rolf Drechsler},
editor = {Michel Robert and
Bruno Rouzeyre and
Christian Piguet and
Marie{-}Lise Flottes},
title = {Speeding Up Verification of {RTL} Designs by Computing One-to-one
Abstractions with Reduced Signal Widths},
booktitle = {{SOC} Design Methodologies, {IFIP} {TC10/WG10.5} Eleventh International
Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01),
December 3-5, 2001, Montpellier, France},
series = {{IFIP} Conference Proceedings},
volume = {218},
pages = {361--374},
publisher = {Kluwer},
year = {2001},
timestamp = {Tue, 13 Aug 2002 16:01:37 +0200},
biburl = {https://dblp.org/rec/conf/ifip10-5/JohannsenD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/SchmiedleGD01,
author = {Frank Schmiedle and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Selection of Efficient Re-Ordering Heuristics for {MDD} Construction},
booktitle = {31st {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2001, Warsaw, Poland, May 22-24, 2001, Proceedings},
pages = {299--304},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ISMVL.2001.924587},
doi = {10.1109/ISMVL.2001.924587},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/SchmiedleGD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/Drechsler01,
author = {Rolf Drechsler},
editor = {Dieter Monjau},
title = {GateComp: Equivalence Checking in {CVE}},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Mei{\ss}en, Germany, February
19-21, 2001},
pages = {109--110},
publisher = {MoPress},
year = {2001},
timestamp = {Thu, 28 Jun 2012 13:09:12 +0200},
biburl = {https://dblp.org/rec/conf/mbmv/Drechsler01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GuntherD01,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Implementation of Read- k-times BDDs on Top of Standard {BDD} Packages},
booktitle = {14th International Conference on {VLSI} Design {(VLSI} Design 2001),
3-7 January 2001, Bangalore, India},
pages = {173--178},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICVD.2001.902657},
doi = {10.1109/ICVD.2001.902657},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GuntherD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GuntherD01a,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Performance Driven Optimization for {MUX} based FPGAs},
booktitle = {14th International Conference on {VLSI} Design {(VLSI} Design 2001),
3-7 January 2001, Bangalore, India},
pages = {311--316},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICVD.2001.902678},
doi = {10.1109/ICVD.2001.902678},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GuntherD01a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DrechslerBD00,
author = {Rolf Drechsler and
Bernd Becker and
Nicole Drechsler},
title = {{OKFDD} minimization by genetic algorithms with application to circuit
design},
journal = {Integr.},
volume = {28},
number = {2},
pages = {121--139},
year = {2000},
url = {https://doi.org/10.1016/S0167-9260(99)00017-6},
doi = {10.1016/S0167-9260(99)00017-6},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DrechslerBD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZuzekDT00,
author = {A. Zuzek and
Rolf Drechsler and
Mitchell A. Thornton},
title = {Boolean function representation and spectral characterization using
{AND/OR} graphs},
journal = {Integr.},
volume = {29},
number = {2},
pages = {101--116},
year = {2000},
url = {https://doi.org/10.1016/S0167-9260(00)00003-1},
doi = {10.1016/S0167-9260(00)00003-1},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZuzekDT00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipl/GuntherD00,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {On the computational power of linearly transformed BDDs},
journal = {Inf. Process. Lett.},
volume = {75},
number = {3},
pages = {119--125},
year = {2000},
url = {https://doi.org/10.1016/S0020-0190(00)00083-1},
doi = {10.1016/S0020-0190(00)00083-1},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipl/GuntherD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/GuntherD00,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {ACTion: Combining logic synthesis and technology mapping for MUX-based
FPGAs},
journal = {J. Syst. Archit.},
volume = {46},
number = {14},
pages = {1321--1334},
year = {2000},
url = {https://doi.org/10.1016/S1383-7621(00)00027-8},
doi = {10.1016/S1383-7621(00)00027-8},
timestamp = {Tue, 19 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/GuntherD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerDG00,
author = {Rolf Drechsler and
Nicole Drechsler and
Wolfgang G{\"{u}}nther},
title = {Fast exact minimization of BDD's},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {19},
number = {3},
pages = {384--389},
year = {2000},
url = {https://doi.org/10.1109/43.833206},
doi = {10.1109/43.833206},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerDG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/GuntherDDB00,
author = {Wolfgang G{\"{u}}nther and
Nicole Drechsler and
Rolf Drechsler and
Bernd Becker},
title = {Verification of Designs Containing Black Boxes},
booktitle = {26th {EUROMICRO} 2000 Conference, Informatics: Inventing the Future,
5-7 September 2000, Maastricht, The Netherlands},
pages = {1100--1105},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/EURMIC.2000.874621},
doi = {10.1109/EURMIC.2000.874621},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/GuntherDDB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/GuntherD00,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {ACTion: Combining Logic Synthesis and Technology Mapping for {MUX}
Based FPGAs},
booktitle = {26th {EUROMICRO} 2000 Conference, Informatics: Inventing the Future,
5-7 September 2000, Maastricht, The Netherlands},
pages = {1130--1137},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.ieeecomputersociety.org/10.1109/EUROMICRO.2000.10007},
doi = {10.1109/EUROMICRO.2000.10007},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/GuntherD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/DrechslerGB00,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Bernd Becker},
title = {Testability of Circuits Derived from Lattice Diagrams},
booktitle = {26th {EUROMICRO} 2000 Conference, Informatics: Inventing the Future,
5-7 September 2000, Maastricht, The Netherlands},
pages = {1188--1192},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/EURMIC.2000.874632},
doi = {10.1109/EURMIC.2000.874632},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/DrechslerGB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/DrechslerDMSB00,
author = {Rolf Drechsler and
Nicole Drechsler and
Elke Mackensen and
Tobias Schubert and
Bernd Becker},
title = {Design Reuse by Modularity: {A} Scalable Dynamical (Re)Configurable
Multiprocessor System},
booktitle = {26th {EUROMICRO} 2000 Conference, Informatics: Inventing the Future,
5-7 September 2000, Maastricht, The Netherlands},
pages = {1425},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/EURMIC.2000.874662},
doi = {10.1109/EURMIC.2000.874662},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/DrechslerDMSB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/GuntherD00,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
editor = {L. Darrell Whitley and
David E. Goldberg and
Erick Cant{\'{u}}{-}Paz and
Lee Spector and
Ian C. Parmee and
Hans{-}Georg Beyer},
title = {Improving EAs for Sequencing Problems},
booktitle = {Proceedings of the Genetic and Evolutionary Computation Conference
{(GECCO} '00), Las Vegas, Nevada, USA, July 8-12, 2000},
pages = {175--180},
publisher = {Morgan Kaufmann},
year = {2000},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/gecco/GuntherD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/SchubertMDDB00,
author = {Tobias Schubert and
Elke Mackensen and
Nicole Drechsler and
Rolf Drechsler and
Bernd Becker},
editor = {L. Darrell Whitley and
David E. Goldberg and
Erick Cant{\'{u}}{-}Paz and
Lee Spector and
Ian C. Parmee and
Hans{-}Georg Beyer},
title = {Specialized Hardware for Implementation of Evolutionary Algorithms},
booktitle = {Proceedings of the Genetic and Evolutionary Computation Conference
{(GECCO} '00), Las Vegas, Nevada, USA, July 8-12, 2000},
pages = {369},
publisher = {Morgan Kaufmann},
year = {2000},
timestamp = {Mon, 27 Nov 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/gecco/SchubertMDDB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/gecco/DrechslerG00,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther},
editor = {L. Darrell Whitley and
David E. Goldberg and
Erick Cant{\'{u}}{-}Paz and
Lee Spector and
Ian C. Parmee and
Hans{-}Georg Beyer},
title = {Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints},
booktitle = {Proceedings of the Genetic and Evolutionary Computation Conference
{(GECCO} '00), Las Vegas, Nevada, USA, July 8-12, 2000},
pages = {513--518},
publisher = {Morgan Kaufmann},
year = {2000},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/gecco/DrechslerG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/GuntherDH00,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler and
Stefan H{\"{o}}reth},
title = {Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound
Computation},
booktitle = {Proceedings of the {IEEE} International Conference On Computer Design:
{VLSI} In Computers {\&} Processors, {ICCD} '00, Austin, Texas,
USA, September 17-20, 2000},
pages = {383--388},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCD.2000.878312},
doi = {10.1109/ICCD.2000.878312},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/GuntherDH00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/LindgrenDB00,
author = {Per Lindgren and
Rolf Drechsler and
Bernd Becker},
title = {Minimization of Ordered Pseudo Kronecker Decision Diagrams},
booktitle = {Proceedings of the {IEEE} International Conference On Computer Design:
{VLSI} In Computers {\&} Processors, {ICCD} '00, Austin, Texas,
USA, September 17-20, 2000},
pages = {504--510},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCD.2000.878329},
doi = {10.1109/ICCD.2000.878329},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/LindgrenDB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DrechslerG00,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther},
title = {Optimization of sequential verification by history-based dynamic minimization
of BDDs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
May 2000, Proceedings},
pages = {737--740},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ISCAS.2000.858857},
doi = {10.1109/ISCAS.2000.858857},
timestamp = {Fri, 13 Aug 2021 09:26:01 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DrechslerG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/DrechslerTW00,
author = {Rolf Drechsler and
Mitchell A. Thornton and
David Wessels},
title = {MDD-Based Synthesis of Multi-Valued Logic Networks},
booktitle = {30th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings},
pages = {41--46},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISMVL.2000.848598},
doi = {10.1109/ISMVL.2000.848598},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ismvl/DrechslerTW00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/DrechslerT00,
author = {Rolf Drechsler and
Mitchell A. Thornton},
title = {Computation of Spectral Information from Logic Netlists},
booktitle = {30th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings},
pages = {53--58},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISMVL.2000.848600},
doi = {10.1109/ISMVL.2000.848600},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ismvl/DrechslerT00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/JankovicGD00,
author = {Dragan Jankovic and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Lower Bound Sifting for MDDs},
booktitle = {30th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings},
pages = {193--198},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISMVL.2000.848619},
doi = {10.1109/ISMVL.2000.848619},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ismvl/JankovicGD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/SchmiedleGD00,
author = {Frank Schmiedle and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Dynamic Re-Encoding During {MDD} Minimization},
booktitle = {30th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings},
pages = {239--244},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISMVL.2000.848626},
doi = {10.1109/ISMVL.2000.848626},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/SchmiedleGD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/ThorntonDG00,
author = {Mitchell A. Thornton and
Rolf Drechsler and
Wolfgang G{\"{u}}nther},
title = {A Method for Approximate Equivalence Checking},
booktitle = {30th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings},
pages = {447--452},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISMVL.2000.848656},
doi = {10.1109/ISMVL.2000.848656},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/ThorntonDG00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/Drechsler0000,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Bernd Becker},
title = {Testability of Circuits Derived from Lattice Diagrams},
booktitle = {1st Latin American Test Workshop, {LATW} 2000, Rio de Janeiro, RJ,
Brazil, March 13-15, 2000},
pages = {77--81},
publisher = {{IEEE}},
year = {2000},
timestamp = {Tue, 25 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/latw/Drechsler0000.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/GuntherDDB00,
author = {Wolfgang G{\"{u}}nther and
Nicole Drechsler and
Rolf Drechsler and
Bernd Becker},
editor = {Klaus Waldschmidt and
Christoph Grimm},
title = {Verification of Designs Containing Black Boxes},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February
28 - March 1, 2000},
pages = {19--26},
publisher = {{VDE}},
year = {2000},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/GuntherDDB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/DrechslerHSHB99,
author = {Rolf Drechsler and
Harry Hengster and
Horst Sch{\"{a}}fer and
Joachim Hartmann and
Bernd Becker},
title = {Testability of 2-Level {AND/EXOR} Circuits},
journal = {J. Electron. Test.},
volume = {14},
number = {3},
pages = {219--225},
year = {1999},
url = {https://doi.org/10.1023/A:1008306002882},
doi = {10.1023/A:1008306002882},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/et/DrechslerHSHB99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Drechsler99,
author = {Rolf Drechsler},
title = {Preudo-Kronecker Expressions for Symmetric Functions},
journal = {{IEEE} Trans. Computers},
volume = {48},
number = {9},
pages = {987--990},
year = {1999},
url = {https://doi.org/10.1109/12.795226},
doi = {10.1109/12.795226},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Drechsler99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SchollMMD99,
author = {Christoph Scholl and
Dirk M{\"{o}}ller and
Paul Molitor and
Rolf Drechsler},
title = {{BDD} minimization using symmetries},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {2},
pages = {81--100},
year = {1999},
url = {https://doi.org/10.1109/43.743706},
doi = {10.1109/43.743706},
timestamp = {Wed, 03 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SchollMMD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tec/Drechsler99,
author = {Rolf Drechsler},
title = {Evolutionary Algorithms for {VLSI} {CAD} [book Review]},
journal = {{IEEE} Trans. Evol. Comput.},
volume = {3},
number = {3},
pages = {251--253},
year = {1999},
url = {https://doi.org/10.1109/TEVC.1999.788494},
doi = {10.1109/TEVC.1999.788494},
timestamp = {Tue, 12 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tec/Drechsler99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YeRD99,
author = {Yibin Ye and
Kaushik Roy and
Rolf Drechsler},
title = {Power Consumption in XOR-Based Circuits},
booktitle = {Proceedings of the 1999 Conference on Asia South Pacific Design Automation,
Wanchai, Hong Kong, China, January 18-21, 1999},
pages = {299--302},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ASPDAC.1999.760018},
doi = {10.1109/ASPDAC.1999.760018},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/YeRD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DrechslerD99,
author = {Rolf Drechsler and
Nicole Drechsler},
title = {Exploiting Don't Caers During Data Sequencing using Genetic Algorithms},
booktitle = {Proceedings of the 1999 Conference on Asia South Pacific Design Automation,
Wanchai, Hong Kong, China, January 18-21, 1999},
pages = {303},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ASPDAC.1999.760019},
doi = {10.1109/ASPDAC.1999.760019},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/DrechslerD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GuntherD99,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Minimization of Free BDDs},
booktitle = {Proceedings of the 1999 Conference on Asia South Pacific Design Automation,
Wanchai, Hong Kong, China, January 18-21, 1999},
pages = {323--326},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ASPDAC.1999.760024},
doi = {10.1109/ASPDAC.1999.760024},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/GuntherD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DrechslerG99,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther},
editor = {Mary Jane Irwin},
title = {Using Lower Bounds During Dynamic {BDD} Minimization},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {29--32},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.309858},
doi = {10.1145/309847.309858},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DrechslerG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HorethD99,
author = {Stefan H{\"{o}}reth and
Rolf Drechsler},
title = {Formal Verification of Word-Level Specifications},
booktitle = {1999 Design, Automation and Test in Europe {(DATE} '99), 9-12 March
1999, Munich, Germany},
pages = {52--57},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1999},
url = {https://doi.org/10.1109/DATE.1999.761096},
doi = {10.1109/DATE.1999.761096},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/HorethD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ThorntonWDD99,
author = {Mitchell A. Thornton and
J. P. Williams and
Rolf Drechsler and
Nicole Drechsler},
title = {Variable Reordering for Shared Binary Decision Diagrams Using Output
Probabilities},
booktitle = {1999 Design, Automation and Test in Europe {(DATE} '99), 9-12 March
1999, Munich, Germany},
pages = {758--759},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1999},
url = {https://doi.org/10.1109/DATE.1999.761217},
doi = {10.1109/DATE.1999.761217},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ThorntonWDD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/DrechslerG99,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther},
title = {Generation of Optimal Universal Logic Modules},
booktitle = {25th {EUROMICRO} '99 Conference, Informatics: Theory and Practice
for the New Millenium, 8-10 September 1999, Milan, Italy},
pages = {1080--1085},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/EURMIC.1999.794451},
doi = {10.1109/EURMIC.1999.794451},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/DrechslerG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/DrechslerJS99,
author = {Rolf Drechsler and
Dragan Jankovic and
Radomir S. Stankovic},
title = {Generic Implementation of {DD} Packages in {MVL}},
booktitle = {25th {EUROMICRO} '99 Conference, Informatics: Theory and Practice
for the New Millenium, 8-10 September 1999, Milan, Italy},
pages = {1352--1359},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/EURMIC.1999.794491},
doi = {10.1109/EURMIC.1999.794491},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/DrechslerJS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/Drechsler99,
author = {Rolf Drechsler},
title = {Checking Integrity During Dynamic Reordering in Decision Diagrams},
booktitle = {25th {EUROMICRO} '99 Conference, Informatics: Theory and Practice
for the New Millenium, 8-10 September 1999, Milan, Italy},
pages = {1360--1367},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/EURMIC.1999.794492},
doi = {10.1109/EURMIC.1999.794492},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/Drechsler99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fuzzy/DrechslerGD99,
author = {Nicole Drechsler and
Wolfgang G{\"{u}}nther and
Rolf Drechsler},
editor = {Bernd Reusch},
title = {Efficient Graph Coloring by Evolutionary Algorithms},
booktitle = {Computational Intelligence, Theory and Applications, International
Conference, 6th Fuzzy Days, Dortmund, Germany, May 25-28, 1999, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1625},
pages = {30--39},
publisher = {Springer},
year = {1999},
url = {https://doi.org/10.1007/3-540-48774-3\_4},
doi = {10.1007/3-540-48774-3\_4},
timestamp = {Tue, 14 May 2019 10:00:38 +0200},
biburl = {https://dblp.org/rec/conf/fuzzy/DrechslerGD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fuzzy/DrechslerDB99,
author = {Nicole Drechsler and
Rolf Drechsler and
Bernd Becker},
editor = {Bernd Reusch},
title = {Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability
Classes},
booktitle = {Computational Intelligence, Theory and Applications, International
Conference, 6th Fuzzy Days, Dortmund, Germany, May 25-28, 1999, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1625},
pages = {108--117},
publisher = {Springer},
year = {1999},
url = {https://doi.org/10.1007/3-540-48774-3\_14},
doi = {10.1007/3-540-48774-3\_14},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fuzzy/DrechslerDB99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/GuntherD99,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
editor = {Jacob K. White and
Ellen Sentovich},
title = {Efficient manipulation algorithms for linearly transformed BDDs},
booktitle = {Proceedings of the 1999 {IEEE/ACM} International Conference on Computer-Aided
Design, 1999, San Jose, California, USA, November 7-11, 1999},
pages = {50--54},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCAD.1999.810620},
doi = {10.1109/ICCAD.1999.810620},
timestamp = {Mon, 08 May 2023 21:43:38 +0200},
biburl = {https://dblp.org/rec/conf/iccad/GuntherD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/LindgrenDB99,
author = {Per Lindgren and
Rolf Drechsler and
Bernd Becker},
title = {Synthesis of Pseudo Kronecker Lattice Diagrams},
booktitle = {Proceedings of the {IEEE} International Conference On Computer Design,
{VLSI} in Computers and Processors, {ICCD} '99, Austin, Texas, USA,
October 10-13, 1999},
pages = {307--310},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCD.1999.808556},
doi = {10.1109/ICCD.1999.808556},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/LindgrenDB99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip10-5/DrechslerG99,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther},
editor = {L. Miguel Silveira and
Srinivas Devadas and
Ricardo Augusto da Luz Reis},
title = {History-Based Dynamic Minimization During {BDD} Construction},
booktitle = {{VLSI:} Systems on a Chip, {IFIP} {TC10/WG10.5} Tenth International
Conference on Very Large Scale Integration {(VLSI} '99), December
1-4, 1999, Lisbon, Portugal},
series = {{IFIP} Conference Proceedings},
volume = {162},
pages = {334--345},
publisher = {Kluwer},
year = {1999},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ifip10-5/DrechslerG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GuntherD99,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Minimization of BDDs using linear transformations based on evolutionary
techniques},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {387--390},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.777884},
doi = {10.1109/ISCAS.1999.777884},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GuntherD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SchmiedleDB99,
author = {Frank Schmiedle and
Rolf Drechsler and
Bernd Becker},
title = {Exact channel routing using symbolic representation},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {394--397},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.780178},
doi = {10.1109/ISCAS.1999.780178},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SchmiedleDB99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DrechslerHB99,
author = {Rolf Drechsler and
Marc Herbstritt and
Bernd Becker},
title = {Grouping heuristics for word-level decision diagrams},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {411--414},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.777893},
doi = {10.1109/ISCAS.1999.777893},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DrechslerHB99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/BrglezD99,
author = {Franc Brglez and
Rolf Drechsler},
title = {Design of experiments in {CAD:} context and new data sets for ISCAS'99},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {424--427},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.780185},
doi = {10.1109/ISCAS.1999.780185},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/BrglezD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GuntherD99a,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Creating hard problem instances in logic synthesis using exact minimization},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {436--439},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.780188},
doi = {10.1109/ISCAS.1999.780188},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/GuntherD99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mbmv/DrechslerHB99,
author = {Rolf Drechsler and
Marc Herbstritt and
Bernd Becker},
editor = {Matthias Mutz and
Nikolaus Lange},
title = {Grouping Heuristics for Word-Level Decision Diagrams},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen (MBMV), Braunschweig, Germany, February
22-24, 1999},
pages = {41--50},
publisher = {Shaker},
year = {1999},
timestamp = {Fri, 20 Jan 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mbmv/DrechslerHB99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0091896,
author = {Rolf Drechsler and
Bernd Becker},
title = {Graphenbasierte Funktionsdarstellung - Boolesche und Pseudo-Boolesche
Funktionen},
series = {Leitf{\"{a}}den der Informatik},
publisher = {Teubner},
year = {1998},
isbn = {978-3-519-02149-0},
timestamp = {Fri, 20 Jan 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/books/daglib/0091896.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0029044,
author = {Rolf Drechsler and
Bernd Becker},
title = {Binary Decision Diagrams - Theory and Implementation},
publisher = {Springer},
year = {1998},
url = {http://www.springer.com/engineering/circuits+\%26+systems/book/978-0-7923-8193-8},
isbn = {978-0-7923-8193-8},
timestamp = {Fri, 20 Jan 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/books/daglib/0029044.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/DrechslerBJ98,
author = {Rolf Drechsler and
Bernd Becker and
Andrea Jahnke},
title = {On Variable Ordering and Decomposition Type Choice in OKFDDs},
journal = {{IEEE} Trans. Computers},
volume = {47},
number = {12},
pages = {1398--1403},
year = {1998},
url = {https://doi.org/10.1109/12.737685},
doi = {10.1109/12.737685},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/DrechslerBJ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerSS98,
author = {Rolf Drechsler and
Martin Sauerhoff and
Detlef Sieling},
title = {The complexity of the inclusion operation on OFDD's},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {5},
pages = {457--459},
year = {1998},
url = {https://doi.org/10.1109/43.703943},
doi = {10.1109/43.703943},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerSS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerB98,
author = {Rolf Drechsler and
Bernd Becker},
title = {Ordered Kronecker functional decision diagrams-a data structure for
representation and manipulation of Boolean functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {965--973},
year = {1998},
url = {https://doi.org/10.1109/43.728917},
doi = {10.1109/43.728917},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LeeD98,
author = {Gueesang Lee and
Rolf Drechsler},
title = {ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified
Boolean Functions},
booktitle = {Proceedings of the {ASP-DAC} '98, Asia and South Pacific Design Automation
Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13,
1998},
pages = {75--80},
publisher = {{IEEE}},
year = {1998},
url = {https://doi.org/10.1109/ASPDAC.1998.669407},
doi = {10.1109/ASPDAC.1998.669407},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LeeD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DrechslerH98,
author = {Rolf Drechsler and
Stefan H{\"{o}}reth},
title = {Manipulation of *BMDs},
booktitle = {Proceedings of the {ASP-DAC} '98, Asia and South Pacific Design Automation
Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13,
1998},
pages = {433--438},
publisher = {{IEEE}},
year = {1998},
url = {https://doi.org/10.1109/ASPDAC.1998.669516},
doi = {10.1109/ASPDAC.1998.669516},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/DrechslerH98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DrechslerDG98,
author = {Rolf Drechsler and
Nicole Drechsler and
Wolfgang G{\"{u}}nther},
editor = {Basant R. Chawla and
Randal E. Bryant and
Jan M. Rabaey},
title = {Fast Exact Minimization of BDDs},
booktitle = {Proceedings of the 35th Conference on Design Automation, Moscone center,
San Francico, California, USA, June 15-19, 1998},
pages = {200--205},
publisher = {{ACM} Press},
year = {1998},
url = {https://doi.org/10.1145/277044.277099},
doi = {10.1145/277044.277099},
timestamp = {Mon, 11 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DrechslerDG98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HorethD98,
author = {Stefan H{\"{o}}reth and
Rolf Drechsler},
editor = {Patrick M. Dewilde and
Franz J. Rammig and
Gerry Musgrave},
title = {Dynamic Minimization of Word-Level Decision Diagrams},
booktitle = {1998 Design, Automation and Test in Europe {(DATE} '98), February
23-26, 1998, Le Palais des Congr{\`{e}}s de Paris, Paris, France},
pages = {612--617},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/DATE.1998.655921},
doi = {10.1109/DATE.1998.655921},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/HorethD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/GuntherD98,
author = {Wolfgang G{\"{u}}nther and
Rolf Drechsler},
title = {Linear Transformations and Exact Minimization of BDDs},
booktitle = {8th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '98), 19-21 February
1998, Lafayette, LA, {USA}},
pages = {325--330},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/GLSV.1998.665287},
doi = {10.1109/GLSV.1998.665287},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/GuntherD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/MillerD98,
author = {D. Michael Miller and
Rolf Drechsler},
title = {Implementing a Multiple-Valued Decision Diagram Package},
booktitle = {28th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1998, Fukuoka, Japan, May 27-29, 1998, Proceedings},
pages = {52--57},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ISMVL.1998.679287},
doi = {10.1109/ISMVL.1998.679287},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/MillerD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/LindgrenDB98,
author = {Per Lindgren and
Rolf Drechsler and
Bernd Becker},
title = {Look-up Table {FPGA} Synthesis from Minimized Multi-Valued Pseudo
Kronecker Expressions},
booktitle = {28th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1998, Fukuoka, Japan, May 27-29, 1998, Proceedings},
pages = {95--101},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ISMVL.1998.679310},
doi = {10.1109/ISMVL.1998.679310},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/LindgrenDB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/KeimDDB98,
author = {Martin Keim and
Nicole Drechsler and
Rolf Drechsler and
Bernd Becker},
title = {Test Generation for (Sequential) Multi-Valued Logic Networks based
on Genetic Algorithm},
booktitle = {28th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1998, Fukuoka, Japan, May 27-29, 1998, Proceedings},
pages = {215--221},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ISMVL.1998.679435},
doi = {10.1109/ISMVL.1998.679435},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/KeimDDB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/safecomp/Drechsler98,
author = {Rolf Drechsler},
editor = {Wolfgang D. Ehrenberger},
title = {Verifying Integrity of Decision Diagrams},
booktitle = {Computer Safety, Reliability and Security, 17th International Conference,
SAFECOMP'98, Heidelberg, Germany, October 5-7, 1998, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1516},
pages = {380--389},
publisher = {Springer},
year = {1998},
url = {https://doi.org/10.1007/3-540-49646-7\_30},
doi = {10.1007/3-540-49646-7\_30},
timestamp = {Tue, 14 May 2019 10:00:44 +0200},
biburl = {https://dblp.org/rec/conf/safecomp/Drechsler98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/DrechslerBR97,
author = {Rolf Drechsler and
Bernd Becker and
Stefan Ruppertz},
title = {The K*BMD: {A} Verification Data Structure},
journal = {{IEEE} Des. Test Comput.},
volume = {14},
number = {2},
pages = {51--59},
year = {1997},
url = {https://doi.org/10.1109/54.587742},
doi = {10.1109/54.587742},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/DrechslerBR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/fmsd/BeckerDT97,
author = {Bernd Becker and
Rolf Drechsler and
Michael Theobald},
title = {On the Expressive Power of OKFDDs},
journal = {Formal Methods Syst. Des.},
volume = {11},
number = {1},
pages = {5--21},
year = {1997},
url = {https://doi.org/10.1023/A:1008635324476},
doi = {10.1023/A:1008635324476},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/fmsd/BeckerDT97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerB97,
author = {Rolf Drechsler and
Bernd Becker},
title = {Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions
for symmetric functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {16},
number = {1},
pages = {1--5},
year = {1997},
url = {https://doi.org/10.1109/43.559327},
doi = {10.1109/43.559327},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerB97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/BeckerDE97,
author = {Bernd Becker and
Rolf Drechsler and
Reinhard Enders},
title = {On the representational power of bit-level and word-level decision
diagrams},
booktitle = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
1997},
pages = {461--467},
publisher = {{IEEE}},
year = {1997},
url = {https://doi.org/10.1109/ASPDAC.1997.600304},
doi = {10.1109/ASPDAC.1997.600304},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/BeckerDE97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GockelDB97,
author = {Nicole G{\"{o}}ckel and
Rolf Drechsler and
Bernd Becker},
title = {Learning heuristics for {OKFDD} minimization by evolutionary algorithms},
booktitle = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
1997},
pages = {469--472},
publisher = {{IEEE}},
year = {1997},
url = {https://doi.org/10.1109/ASPDAC.1997.600307},
doi = {10.1109/ASPDAC.1997.600307},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/GockelDB97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HettDB97,
author = {Andreas Hett and
Rolf Drechsler and
Bernd Becker},
title = {Fast and efficient construction of BDDs by reordering based synthesis},
booktitle = {European Design and Test Conference, ED{\&}TC '97, Paris, France,
17-20 March 1997},
pages = {168--175},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/EDTC.1997.582353},
doi = {10.1109/EDTC.1997.582353},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/HettDB97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DrechslerHSHB97,
author = {Rolf Drechsler and
Harry Hengster and
Horst Sch{\"{a}}fer and
Joachim Hartmann and
Bernd Becker},
title = {Testability of 2-level {AND/EXOR} circuits},
booktitle = {European Design and Test Conference, ED{\&}TC '97, Paris, France,
17-20 March 1997},
pages = {548--553},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/EDTC.1997.582415},
doi = {10.1109/EDTC.1997.582415},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/DrechslerHSHB97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SchollDB97,
author = {Christoph Scholl and
Rolf Drechsler and
Bernd Becker},
editor = {Ralph H. J. M. Otten and
Hiroto Yasuura},
title = {Functional simulation using binary decision diagrams},
booktitle = {Proceedings of the 1997 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1997, San Jose, CA, USA, November 9-13, 1997},
pages = {8--12},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1997},
url = {https://doi.org/10.1109/ICCAD.1997.643253},
doi = {10.1109/ICCAD.1997.643253},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SchollDB97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/FilesDP97,
author = {Craig M. Files and
Rolf Drechsler and
Marek A. Perkowski},
title = {Functional Decomposition of {MVL} Functions Using Multi-Valued Decision
Diagrams},
booktitle = {27th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings},
pages = {27--34},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ISMVL.1997.601370},
doi = {10.1109/ISMVL.1997.601370},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/FilesDP97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/DrechslerKB97,
author = {Rolf Drechsler and
Martin Keim and
Bernd Becker},
title = {Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued
Linear Expressions},
booktitle = {27th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings},
pages = {66--74},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ISMVL.1997.601376},
doi = {10.1109/ISMVL.1997.601376},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/DrechslerKB97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/DrechslerKB97a,
author = {Rolf Drechsler and
Martin Keim and
Bernd Becker},
title = {Fault Simulation in Sequential Multi-Valued Logic Networks},
booktitle = {27th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings},
pages = {145--152},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ISMVL.1997.601389},
doi = {10.1109/ISMVL.1997.601389},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/DrechslerKB97a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/StankovicD97,
author = {Radomir S. Stankovic and
Rolf Drechsler},
title = {Circuit Design from Kronecker Galois Field Decision Diagrams for Multiple-Valued
Functions},
booktitle = {27th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings},
pages = {275--280},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ISMVL.1997.601413},
doi = {10.1109/ISMVL.1997.601413},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/StankovicD97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tacas/DrechslerBR97,
author = {Rolf Drechsler and
Bernd Becker and
Stefan Ruppertz},
editor = {Ed Brinksma},
title = {Manipulation Algorithms for K*BMDs},
booktitle = {Tools and Algorithms for Construction and Analysis of Systems, Third
International Workshop, {TACAS} '97, Enschede, The Netherlands, April
2-4, 1997, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1217},
pages = {4--18},
publisher = {Springer},
year = {1997},
url = {https://doi.org/10.1007/BFb0035377},
doi = {10.1007/BFB0035377},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/tacas/DrechslerBR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/BeckerD97,
author = {Bernd Becker and
Rolf Drechsler},
title = {Decision Diagrams in Synthesis - Algorithms, Applications and Extensions},
booktitle = {10th International Conference on {VLSI} Design {(VLSI} Design 1997),
4-7 January 1997, Hyderabad, India},
pages = {46--50},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICVD.1997.567959},
doi = {10.1109/ICVD.1997.567959},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/BeckerD97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/BeckerDR97,
author = {Bernd Becker and
Rolf Drechsler and
Sudhakar M. Reddy},
title = {(Quasi-) Linear Path Delay Fault Tests for Adders},
booktitle = {10th International Conference on {VLSI} Design {(VLSI} Design 1997),
4-7 January 1997, Hyderabad, India},
pages = {101--105},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICVD.1997.567969},
doi = {10.1109/ICVD.1997.567969},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/BeckerDR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/Drechsler97,
author = {Rolf Drechsler},
title = {Pseudo Kronecker Expressions for Symmetric Functions},
booktitle = {10th International Conference on {VLSI} Design {(VLSI} Design 1997),
4-7 January 1997, Hyderabad, India},
pages = {511--513},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICVD.1997.568188},
doi = {10.1109/ICVD.1997.568188},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/Drechsler97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/KeimMBDM97,
author = {Martin Keim and
Michael Martin and
Bernd Becker and
Rolf Drechsler and
Paul Molitor},
title = {Polynomial Formal Verification of Multipliers},
booktitle = {15th {IEEE} {VLSI} Test Symposium (VTS'97), April 27-May 1, 1997,
Monterey, California, {USA}},
pages = {150--157},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/VTEST.1997.599468},
doi = {10.1109/VTEST.1997.599468},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/KeimMBDM97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/dnb/Drechsler96,
author = {Rolf Drechsler},
title = {Ordered Kronecker functional decision diagrams und ihre Anwendung},
school = {Goethe University Frankfurt am Main},
year = {1996},
url = {https://d-nb.info/947408886},
isbn = {3-9805033-0-5},
timestamp = {Sat, 17 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/dnb/Drechsler96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/DrechslerTB96,
author = {Rolf Drechsler and
Michael Theobald and
Bernd Becker},
title = {Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions},
journal = {{IEEE} Trans. Computers},
volume = {45},
number = {11},
pages = {1294--1299},
year = {1996},
url = {https://doi.org/10.1109/12.544485},
doi = {10.1109/12.544485},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/DrechslerTB96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/HengsterDBEP96,
author = {Harry Hengster and
Rolf Drechsler and
Bernd Becker and
Stefan Eckrich and
Tonja Pfeiffer},
title = {{AND/EXOR} based Synthesis of Testable KFDD-Circuits with Small Depth},
booktitle = {5th Asian Test Symposium {(ATS} '96), November 20-22, 1996, Hsinchu,
Taiwan},
pages = {148},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ATS.1996.555152},
doi = {10.1109/ATS.1996.555152},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/HengsterDBEP96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DrechslerBR96,
author = {Rolf Drechsler and
Bernd Becker and
Stefan Ruppertz},
title = {K*BMDs: {A} New Data Structure for Verification},
booktitle = {1996 European Design and Test Conference, ED{\&}TC 1996, Paris,
France, March 11-14, 1996},
pages = {2--8},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/EDTC.1996.494118},
doi = {10.1109/EDTC.1996.494118},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/DrechslerBR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BeckerDKR96,
author = {Bernd Becker and
Rolf Drechsler and
Rolf Krieger and
Sudhakar M. Reddy},
title = {A Fast Optimal Robust Path Delay Fault Testable Adder},
booktitle = {1996 European Design and Test Conference, ED{\&}TC 1996, Paris,
France, March 11-14, 1996},
pages = {491--499},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/EDTC.1996.494346},
doi = {10.1109/EDTC.1996.494346},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/BeckerDKR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/HettBD96,
author = {Andreas Hett and
Bernd Becker and
Rolf Drechsler},
editor = {Graham Symonds and
Wolfgang Nebel},
title = {{MORE:} an alternative implementation of {BDD} packages by multi-operand
synthesis},
booktitle = {Proceedings of the conference on European design automation, {EURO-DAC}
'96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996},
pages = {164--169},
publisher = {{IEEE} Computer Society Press},
year = {1996},
url = {https://doi.org/10.1109/EURDAC.1996.558200},
doi = {10.1109/EURDAC.1996.558200},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/eurodac/HettBD96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/Drechsler96,
author = {Rolf Drechsler},
title = {Verification of Multi-Valued Logic Networks},
booktitle = {26th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings},
pages = {10--15},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ISMVL.1996.508329},
doi = {10.1109/ISMVL.1996.508329},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/Drechsler96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ppsn/DrechslerGB96,
author = {Rolf Drechsler and
Nicole G{\"{o}}ckel and
Bernd Becker},
editor = {Hans{-}Michael Voigt and
Werner Ebeling and
Ingo Rechenberg and
Hans{-}Paul Schwefel},
title = {Learning Heuristics for {OBDD} Minimization by Evolutionary Algorithms},
booktitle = {Parallel Problem Solving from Nature - {PPSN} IV, International Conference
on Evolutionary Computation. The 4th International Conference on Parallel
Problem Solving from Nature, Berlin, Germany, September 22-26, 1996,
Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1141},
pages = {730--739},
publisher = {Springer},
year = {1996},
url = {https://doi.org/10.1007/3-540-61723-X\_1036},
doi = {10.1007/3-540-61723-X\_1036},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ppsn/DrechslerGB96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/HengsterDB95,
author = {Harry Hengster and
Rolf Drechsler and
Bernd Becker},
title = {On local transformations and path delay fault testability},
journal = {J. Electron. Test.},
volume = {7},
number = {3},
pages = {173--191},
year = {1995},
url = {https://doi.org/10.1007/BF00995312},
doi = {10.1007/BF00995312},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/et/HengsterDB95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iandc/BeckerDW95,
author = {Bernd Becker and
Rolf Drechsler and
Ralph Werchner},
title = {On the Relation between BDDs and FDDs},
journal = {Inf. Comput.},
volume = {123},
number = {2},
pages = {185--197},
year = {1995},
url = {https://doi.org/10.1006/inco.1995.1167},
doi = {10.1006/INCO.1995.1167},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iandc/BeckerDW95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijait/DrechslerBGJ95,
author = {Rolf Drechsler and
Bernd Becker and
Nicole G{\"{o}}ckel and
Andrea Jahnke},
title = {A Genetic Algorithm for Decomposition Type Choice in OKFDDs},
journal = {Int. J. Artif. Intell. Tools},
volume = {4},
number = {4},
pages = {525},
year = {1995},
url = {https://doi.org/10.1142/S0218213095000279},
doi = {10.1142/S0218213095000279},
timestamp = {Tue, 12 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijait/DrechslerBGJ95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeckerDM95,
author = {Bernd Becker and
Rolf Drechsler and
Paul Molitor},
title = {On the generation of area-time optimal testable adders},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {14},
number = {9},
pages = {1049--1066},
year = {1995},
url = {https://doi.org/10.1109/43.406707},
doi = {10.1109/43.406707},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/BeckerDM95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DrechslerB95,
author = {Rolf Drechsler and
Bernd Becker},
editor = {Isao Shirakawa},
title = {Learning heuristics by genetic algorithms},
booktitle = {Proceedings of the 1995 Conference on Asia Pacific Design Automation,
Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995},
publisher = {{ACM}},
year = {1995},
url = {https://doi.org/10.1145/224818.224920},
doi = {10.1145/224818.224920},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/DrechslerB95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DrechslerB95,
author = {Rolf Drechsler and
Bernd Becker},
title = {Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions
for symmetric functions},
booktitle = {1995 European Design and Test Conference, ED{\&}TC 1995, Paris,
France, March 6-9, 1995},
pages = {91--99},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/EDTC.1995.470414},
doi = {10.1109/EDTC.1995.470414},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/DrechslerB95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BeckerD95,
author = {Bernd Becker and
Rolf Drechsler},
title = {How many decomposition types do we need? [decision diagrams]},
booktitle = {1995 European Design and Test Conference, ED{\&}TC 1995, Paris,
France, March 6-9, 1995},
pages = {438--443},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/EDTC.1995.470359},
doi = {10.1109/EDTC.1995.470359},
timestamp = {Fri, 20 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/BeckerD95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BeckerD95a,
author = {Bernd Becker and
Rolf Drechsler},
title = {Synthesis for testability: circuits derived from ordered Kronecker
functional decision diagrams},
booktitle = {1995 European Design and Test Conference, ED{\&}TC 1995, Paris,
France, March 6-9, 1995},
pages = {592},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/EDTC.1995.470336},
doi = {10.1109/EDTC.1995.470336},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/BeckerD95a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icalp/BeckerDT95,
author = {Bernd Becker and
Rolf Drechsler and
Michael Theobald},
editor = {Zolt{\'{a}}n F{\"{u}}l{\"{o}}p and
Ferenc G{\'{e}}cseg},
title = {OKFDDs versus OBDDs and OFDDs},
booktitle = {Automata, Languages and Programming, 22nd International Colloquium,
ICALP95, Szeged, Hungary, July 10-14, 1995, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {944},
pages = {475--486},
publisher = {Springer},
year = {1995},
url = {https://doi.org/10.1007/3-540-60084-1\_98},
doi = {10.1007/3-540-60084-1\_98},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icalp/BeckerDT95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icannga/Drechsler0G95,
author = {Rolf Drechsler and
Bernd Becker and
Nicole G{\"{o}}ckel},
editor = {David W. Pearson and
Nigel C. Steele and
Rudolf F. Albrecht},
title = {A Genetic Algorithm for Minimization of Fixed Polarity Reed-Muller
Expressions},
booktitle = {Artificial Neural Nets and Genetic Algorithms, {ICANNGA} 1995, Proceedings
of the International Conference in Al{\`{e}}s, France, 1995},
pages = {393--395},
publisher = {Springer},
year = {1995},
url = {https://doi.org/10.1007/978-3-7091-7535-4\_102},
doi = {10.1007/978-3-7091-7535-4\_102},
timestamp = {Fri, 05 Jul 2019 13:13:56 +0200},
biburl = {https://dblp.org/rec/conf/icannga/Drechsler0G95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/DrechslerB95,
author = {Rolf Drechsler and
Bernd Becker},
title = {Dynamic minimization of OKFDDs},
booktitle = {1995 International Conference on Computer Design {(ICCD} '95), {VLSI}
in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings},
pages = {602--607},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/ICCD.1995.528930},
doi = {10.1109/ICCD.1995.528930},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/DrechslerB95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/DrechslerKB95,
author = {Rolf Drechsler and
Rolf Krieger and
Bernd Becker},
title = {Random Pattern Fault Simulation in Multi-Valued Circuits},
booktitle = {25th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings},
pages = {98--103},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/ISMVL.1995.513516},
doi = {10.1109/ISMVL.1995.513516},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/DrechslerKB95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latin/BeckerDW95,
author = {Bernd Becker and
Rolf Drechsler and
Ralph Werchner},
editor = {Ricardo A. Baeza{-}Yates and
Eric Goles Ch. and
Patricio V. Poblete},
title = {On the Relation Betwen BDDs and FDDs},
booktitle = {{LATIN} '95: Theoretical Informatics, Second Latin American Symposium,
Valpara{\'{\i}}so, Chile, April 3-7, 1995, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {911},
pages = {72--83},
publisher = {Springer},
year = {1995},
url = {https://doi.org/10.1007/3-540-59175-3\_82},
doi = {10.1007/3-540-59175-3\_82},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/latin/BeckerDW95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/HengsterDB95,
author = {Harry Hengster and
Rolf Drechsler and
Bernd Becker},
title = {On the application of local circuit transformations with special emphasis
on path delay fault testability},
booktitle = {13th {IEEE} {VLSI} Test Symposium (VTS'95), April 30 - May 3, 1995,
Princeton, New Jersey, {USA}},
pages = {387--392},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/VTEST.1995.512665},
doi = {10.1109/VTEST.1995.512665},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/HengsterDB95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/DrechslerSTBP94,
author = {Rolf Drechsler and
Andisheh Sarabi and
Michael Theobald and
Bernd Becker and
Marek A. Perkowski},
editor = {Michael J. Lorenzetti},
title = {Efficient Representation and Manipulation of Switching Functions Based
on Ordered Kronecker Functional Decision Diagrams},
booktitle = {Proceedings of the 31st Conference on Design Automation, San Diego,
California, USA, June 6-10, 1994},
pages = {415--419},
publisher = {{ACM} Press},
year = {1994},
url = {https://doi.org/10.1145/196244.196444},
doi = {10.1145/196244.196444},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/DrechslerSTBP94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/DrechslerBT94,
author = {Rolf Drechsler and
Bernd Becker and
Michael Theobald},
editor = {Jean Mermet},
title = {Fast {OFDD} based minimization of fixed polarity Reed-Muller expressions},
booktitle = {Proceedings EURO-DAC'94, European Design Automation Conference, Grenoble,
France, September 19-22, 1994},
pages = {2--7},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {http://dl.acm.org/citation.cfm?id=198179},
timestamp = {Wed, 29 Mar 2017 16:45:25 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/DrechslerBT94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/Drechsler94,
author = {Rolf Drechsler},
editor = {Jean Mermet},
title = {BiTeS: a {BDD} based test pattern generator for strong robust path
delay faults},
booktitle = {Proceedings EURO-DAC'94, European Design Automation Conference, Grenoble,
France, September 19-22, 1994},
pages = {322--327},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {http://dl.acm.org/citation.cfm?id=198276},
timestamp = {Wed, 11 Nov 2015 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/eurodac/Drechsler94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/BeckerD94,
author = {Bernd Becker and
Rolf Drechsler},
editor = {Robert Werner},
title = {Testability of Circuits Derived from Functional Decision Diagrams},
booktitle = {{EDAC} - The European Conference on Design Automation, {ETC} - European
Test Conference, {EUROASIC} - The European Event in {ASIC} Design,
Proceedings, February 28 - March 3, 1994, Paris, France},
pages = {667},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/EDTC.1994.326922},
doi = {10.1109/EDTC.1994.326922},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/BeckerD94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/BeckerD94,
author = {Bernd Becker and
Rolf Drechsler},
title = {{OFDD} Based Minimization of Fixed Polarity Reed-Muller Expressions
Using Hybrid Genetic Algorithms},
booktitle = {Proceedings 1994 {IEEE} International Conference on Computer Design:
{VLSI} in Computer {\&} Processors, {ICCD} '94, Cambridge, MA,
USA, October 10-12, 1994},
pages = {106--110},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/ICCD.1994.331866},
doi = {10.1109/ICCD.1994.331866},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/BeckerD94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/BeckerD94,
author = {Bernd Becker and
Rolf Drechsler},
title = {Efficient Graph Based Representation of Multi-Valued Functions with
an Application to Genetic Algorithms},
booktitle = {24th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1994, Boston, Massachusetts, USA, May 25-27, 1994, Proceedings},
pages = {65--72},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/ISMVL.1994.302218},
doi = {10.1109/ISMVL.1994.302218},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/BeckerD94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/HengsterDB94,
author = {Harry Hengster and
Rolf Drechsler and
Bernd Becker},
title = {Testability Properties of Local Circuit Transformations with Respect
to the Robust Path-Delay-Fault Model},
booktitle = {Proceedings of the Seventh International Conference on {VLSI} Design,
{VLSI} Design 1994, Calcutta, India, January 5-8, 1994},
pages = {123--126},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/ICVD.1994.282669},
doi = {10.1109/ICVD.1994.282669},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/HengsterDB94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/BeckerDM93,
author = {Bernd Becker and
Rolf Drechsler and
Paul Molitor},
title = {On the implementation of an efficient performance driven generator
for conditional-sum-adders},
booktitle = {Proceedings of the European Design Automation Conference 1993, {EURO-DAC}
'93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993},
pages = {402--407},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/EURDAC.1993.410668},
doi = {10.1109/EURDAC.1993.410668},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/BeckerDM93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/BeckerD92,
author = {Bernd Becker and
Rolf Drechsler},
editor = {Gerald Musgrave},
title = {A time optimal robust path-delay-fault self-testable adder},
booktitle = {Proceedings of the conference on European design automation, {EURO-DAC}
'92, Hamburg, Germany, September 7-10, 1992},
pages = {376--381},
publisher = {{IEEE} Computer Society Press},
year = {1992},
url = {https://doi.org/10.1109/EURDAC.1992.246216},
doi = {10.1109/EURDAC.1992.246216},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/BeckerD92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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