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BibTeX records: Said Derradji
@inproceedings{DBLP:conf/dsd/BiagioniCFCLMPP22, author = {Andrea Biagioni and Paolo Cretaro and Ottorino Frezza and Francesca Lo Cicero and Alessandro Lonardo and Michele Martinelli and Pier Stanislao Paolucci and Elena Pastorelli and Francesco Simula and Matteo Turisini and Piero Vicini and Roberto Ammendola and Pascale Bernier{-}Bruna and Claire Chen and Said Derradji and St{\'{e}}phane Guez and Pierre{-}Axel Lagadec and Gregoire Pichon and Etienne Walter and Gaetan De Gassowski and Matthieu Hautreaux and Stephane Mathieu and Gilles Moreau and Marc P{\'{e}}rache and Hugo Taboada and Torsten Hoefler and Timo Schneider and Matteo Barnaba and Giuseppe Piero Brandino and Francesco De Giorgi and Matteo Poggi and Iakovos Mavroidis and Yannis Papaefstathiou and Nikolaos Tampouratzis and Benjamin Kalisch and Ulrich Krackhardt and Mondrian Nuessle and Pantelis Xirouchakis and Vangelis Mageiropoulos and Michalis Gianioudis and Harisis Loukas and Aggelos Ioannou and Nikos Kallimanis and Nikos Chrysos and Manolis Katevenis and Wolfgang Frings and Dominik Gottwald and Felime Guimaraes and Max Holicki and Volker Marx and Yannik M{\"{u}}ller and Carsten Clauss and Hugo Falter and Xu Huang and Jennifer Lopez Barillao and Thomas Moschny and Simon Pickartz and Francisco J. Alfaro and Jes{\'{u}}s Escudero{-}Sahuquillo and Pedro Javier Garc{\'{\i}}a and Francisco J. Quiles and Jos{\'{e}} L. S{\'{a}}nchez and Adri{\'{a}}n Castell{\'{o}} and Jose Duro and Mar{\'{\i}}a Engracia G{\'{o}}mez and Enrique S. Quintana{-}Ort{\'{\i}} and Julio Sahuquillo and Eugenio Stabile}, title = {{RED-SEA:} Network Solution for Exascale Architectures}, booktitle = {25th Euromicro Conference on Digital System Design, {DSD} 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022}, pages = {712--719}, publisher = {{IEEE}}, year = {2022}, url = {https://doi.org/10.1109/DSD57027.2022.00100}, doi = {10.1109/DSD57027.2022.00100}, timestamp = {Sun, 04 Aug 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dsd/BiagioniCFCLMPP22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/ArmejachBCD0HLL21, author = {Adri{\`{a}} Armejach and Bine Brank and Jordi Cortina and Fran{\c{c}}ois Dolique and Timothy Hayes and Nam Ho and Pierre{-}Axel Lagadec and Romain Lemaire and Guillem L{\'{o}}pez{-}Parad{\'{\i}}s and Laurent Marliac and Miquel Moret{\'{o}} and Pedro Marcuello and Dirk Pleiter and Xubin Tan and Said Derradji}, title = {Mont-Blanc 2020: Towards Scalable and Power Efficient European {HPC} Processors}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2021, Grenoble, France, February 1-5, 2021}, pages = {136--141}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.23919/DATE51398.2021.9474093}, doi = {10.23919/DATE51398.2021.9474093}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/date/ArmejachBCD0HLL21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ddecs/NocuaDVLM20, author = {Alejandro Nocua and Said Derradji and Gregory Vaumourin and Pierre{-}Axel Lagadec and Zoltan Menyhart}, title = {Mont-Blanc 2020: Simulation Efforts Towards Exascale High Performance Computing : Embedded Tutorial on "DDECS-2020"}, booktitle = {23rd International Symposium on Design and Diagnostics of Electronic Circuits {\&} Systems, {DDECS} 2020, Novi Sad, Serbia, April 22-24, 2020}, pages = {1--2}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1109/DDECS50862.2020.9095675}, doi = {10.1109/DDECS50862.2020.9095675}, timestamp = {Tue, 26 May 2020 15:38:10 +0200}, biburl = {https://dblp.org/rec/conf/ddecs/NocuaDVLM20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tpds/CahenyADVMC18, author = {Paul Caheny and Lluc Alvarez and Said Derradji and Mateo Valero and Miquel Moret{\'{o}} and Marc Casas}, title = {Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach}, journal = {{IEEE} Trans. Parallel Distributed Syst.}, volume = {29}, number = {5}, pages = {1174--1187}, year = {2018}, url = {https://doi.org/10.1109/TPDS.2017.2787123}, doi = {10.1109/TPDS.2017.2787123}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tpds/CahenyADVMC18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/mam/WeloliBVDB17, author = {Jo{\"{e}}l Wanza Weloli and S{\'{e}}bastien Bilavarn and Maarten de Vries and Said Derradji and C{\'{e}}cile Belleudy}, title = {Efficiency modeling and exploration of 64-bit {ARM} compute nodes for exascale}, journal = {Microprocess. Microsystems}, volume = {53}, pages = {68--80}, year = {2017}, url = {https://doi.org/10.1016/j.micpro.2017.06.019}, doi = {10.1016/J.MICPRO.2017.06.019}, timestamp = {Tue, 26 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/mam/WeloliBVDB17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dsd/WeloliBDBL16, author = {Jo{\"{e}}l Wanza Weloli and S{\'{e}}bastien Bilavarn and Said Derradji and C{\'{e}}cile Belleudy and Sylvie Lesmanne}, editor = {Paris Kitsos}, title = {Efficiency Modeling and Analysis of 64-bit {ARM} Clusters for {HPC}}, booktitle = {2016 Euromicro Conference on Digital System Design, {DSD} 2016, Limassol, Cyprus, August 31 - September 2, 2016}, pages = {342--347}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/DSD.2016.74}, doi = {10.1109/DSD.2016.74}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dsd/WeloliBDBL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sc/RajovicRMRVGBNS16, author = {Nikola Rajovic and Alejandro Rico and Filippo Mantovani and Daniel Ruiz and Josep Oriol Vilarrubi and Constantino G{\'{o}}mez and Luna Backes and Diego Nieto and Harald Servat and Xavier Martorell and Jes{\'{u}}s Labarta and Eduard Ayguad{\'{e}} and Chris Adeniyi{-}Jones and Said Derradji and Herv{\'{e}} Gloaguen and Piero Lanucara and Nico Sanna and Jean{-}Fran{\c{c}}ois M{\'{e}}haut and Kevin Pouget and Brice Videau and Eric Boyer and Momme Allalen and Axel Auweter and David Brayford and Daniele Tafani and Volker Weinberg and Dirk Br{\"{o}}mmel and Ren{\'{e}} Halver and Jan H. Meinke and Ram{\'{o}}n Beivide and Mariano Benito and Enrique Vallejo and Mateo Valero and Alex Ram{\'{\i}}rez}, editor = {John West and Cherri M. Pancake}, title = {The mont-blanc prototype: an alternative approach for {HPC} systems}, booktitle = {Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, {SC} 2016, Salt Lake City, UT, USA, November 13-18, 2016}, pages = {444--455}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/SC.2016.37}, doi = {10.1109/SC.2016.37}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/sc/RajovicRMRVGBNS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hoti/DerradjiPPPA15, author = {Said Derradji and Thibaut Palfer{-}Sollier and Jean{-}Pierre Panziera and Axel Poudes and Francois Wellenreiter}, title = {The {BXI} Interconnect Architecture}, booktitle = {23rd {IEEE} Annual Symposium on High-Performance Interconnects, {HOTI} 2015, Santa Clara, CA, USA, August 26-28, 2015}, pages = {18--25}, publisher = {{IEEE} Computer Society}, year = {2015}, url = {https://doi.org/10.1109/HOTI.2015.15}, doi = {10.1109/HOTI.2015.15}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hoti/DerradjiPPPA15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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