BibTeX records: Vinay Dabholkar

• > Home > Persons > Vinay Dabholkar

@article{DBLP:journals/tcad/DabholkarCPR98,
  author       = {Vinay Dabholkar and
                  Sreejit Chakravarty and
                  Irith Pomeranz and
                  Sudhakar M. Reddy},
  title        = {Techniques for minimizing power dissipation in scan and combinational
                  circuits during test application},
  journal      = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
  volume       = {17},
  number       = {12},
  pages        = {1325--1333},
  year         = {1998},
  url          = {https://doi.org/10.1109/43.736572},
  doi          = {10.1109/43.736572},
  timestamp    = {Thu, 24 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcad/DabholkarCPR98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsid/DabholkarC98,
  author       = {Vinay Dabholkar and
                  Sreejit Chakravarty},
  title        = {Computing Stress Tests for Gate Oxide Shorts},
  booktitle    = {11th International Conference on {VLSI} Design {(VLSI} Design 1991),
                  4-7 January 1998, Chennai, India},
  pages        = {378--391},
  publisher    = {{IEEE} Computer Society},
  year         = {1998},
  url          = {https://doi.org/10.1109/ICVD.1998.646637},
  doi          = {10.1109/ICVD.1998.646637},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/DabholkarC98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/ats/DabholkarC97,
  author       = {Vinay Dabholkar and
                  Sreejit Chakravarty},
  title        = {Computing stress tests for interconnect defects},
  booktitle    = {6th Asian Test Symposium {(ATS} '97), 17-18 November 1997, Akita,
                  Japan},
  pages        = {143--148},
  publisher    = {{IEEE} Computer Society},
  year         = {1997},
  url          = {https://doi.org/10.1109/ATS.1997.643950},
  doi          = {10.1109/ATS.1997.643950},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ats/DabholkarC97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vts/DabholkarCNP95,
  author       = {Vinay Dabholkar and
                  Sreejit Chakravarty and
                  J. Najm and
                  Janak H. Patel},
  title        = {Cyclic stress tests for full scan circuits},
  booktitle    = {13th {IEEE} {VLSI} Test Symposium (VTS'95), April 30 - May 3, 1995,
                  Princeton, New Jersey, {USA}},
  pages        = {89--94},
  publisher    = {{IEEE} Computer Society},
  year         = {1995},
  url          = {https://doi.org/10.1109/VTEST.1995.512622},
  doi          = {10.1109/VTEST.1995.512622},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vts/DabholkarCNP95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}