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ORCIDBibTeX records: Yi-Jung Chen
@inproceedings{DBLP:conf/hpca/LinCCY23,
author = {Shao{-}Fu Lin and
Yi{-}Jung Chen and
Hsiang{-}Yun Cheng and
Chia{-}Lin Yang},
title = {Tensor Movement Orchestration in Multi-GPU Training Systems},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2023, Montreal, QC, Canada, February 25 - March 1, 2023},
pages = {1140--1152},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/HPCA56546.2023.10071043},
doi = {10.1109/HPCA56546.2023.10071043},
timestamp = {Wed, 29 Mar 2023 11:07:46 +0200},
biburl = {https://dblp.org/rec/conf/hpca/LinCCY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LinLCJY22,
author = {Chung{-}Hsiang Lin and
Shao{-}Fu Lin and
Yi{-}Jung Chen and
En{-}Yu Jenp and
Chia{-}Lin Yang},
title = {{PUMP:} Profiling-free Unified Memory Prefetcher for Large {DNN} Model
Support},
booktitle = {27th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2022, Taipei, Taiwan, January 17-20, 2022},
pages = {122--127},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ASP-DAC52403.2022.9712507},
doi = {10.1109/ASP-DAC52403.2022.9712507},
timestamp = {Fri, 04 Mar 2022 13:11:07 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/LinLCJY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sac/LiuCH20,
author = {Chia{-}Yin Liu and
Yi{-}Jung Chen and
Masanori Hariyama},
editor = {Chih{-}Cheng Hung and
Tom{\'{a}}s Cern{\'{y}} and
Dongwan Shin and
Alessio Bechini},
title = {Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid
memories},
booktitle = {{SAC} '20: The 35th {ACM/SIGAPP} Symposium on Applied Computing, online
event, [Brno, Czech Republic], March 30 - April 3, 2020},
pages = {546--553},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3341105.3373858},
doi = {10.1145/3341105.3373858},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sac/LiuCH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/racs/LiuWC18,
author = {Chia{-}Yin Liu and
Cheng{-}En Wu and
Yi{-}Jung Chen},
editor = {Chih{-}Cheng Hung and
Lamjed Ben Said},
title = {Thermal-aware task and data co-allocation for multi-processor system-on-chips
with 3D-stacked memories},
booktitle = {Proceedings of the 2018 Conference on Research in Adaptive and Convergent
Systems, {RACS} 2018, Honolulu, HI, USA, October 09-12, 2018},
pages = {243--248},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3264746.3264771},
doi = {10.1145/3264746.3264771},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/racs/LiuWC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/ChenCLWCT17,
author = {Yi{-}Jung Chen and
Wen{-}Wei Chang and
Chia{-}Yin Liu and
Cheng{-}En Wu and
Bo{-}Yuan Chen and
Ming{-}Ying Tsai},
title = {Processors Allocation for MPSoCs With Single {ISA} Heterogeneous Multi-Core
Architecture},
journal = {{IEEE} Access},
volume = {5},
pages = {4028--4036},
year = {2017},
url = {https://doi.org/10.1109/ACCESS.2017.2688699},
doi = {10.1109/ACCESS.2017.2688699},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/ChenCLWCT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ChangCCYECY17,
author = {Che{-}Wei Chang and
Geng{-}You Chen and
Yi{-}Jung Chen and
Chia{-}Wei Yeh and
Pei Yin Eng and
Ana Cheung and
Chia{-}Lin Yang},
title = {Exploiting Write Heterogeneity of Morphable {MLC/SLC} SSDs in Datacenters
with Service-Level Objectives},
journal = {{IEEE} Trans. Computers},
volume = {66},
number = {8},
pages = {1457--1463},
year = {2017},
url = {https://doi.org/10.1109/TC.2017.2677425},
doi = {10.1109/TC.2017.2677425},
timestamp = {Tue, 18 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/ChangCCYECY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/LinSCYW15,
author = {Chung{-}Hsiang Lin and
De{-}Yu Shen and
Yi{-}Jung Chen and
Chia{-}Lin Yang and
Cheng{-}Yuan Michael Wang},
title = {{SECRET:} {A} Selective Error Correction Framework for Refresh Energy
Reduction in DRAMs},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {12},
number = {2},
pages = {19:19:1--19:19:24},
year = {2015},
url = {https://doi.org/10.1145/2747876},
doi = {10.1145/2747876},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/LinSCYW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/racs/ChenYLL15,
author = {Yi{-}Jung Chen and
Chia{-}Lin Yang and
Ping{-}Sheng Lin and
Yi{-}Chang Lu},
editor = {Esmaeil S. Nadimi and
Tom{\'{a}}s Cern{\'{y}} and
Sung{-}Ryul Kim and
Wei Wang},
title = {Thermal/performance characterization of CMPs with 3D-stacked DRAMs
under synergistic voltage-frequency control of cores and DRAMs},
booktitle = {Proceedings of the 2015 Conference on research in adaptive and convergent
systems, {RACS} 2015, Prague, Czech Republic, October 9-12, 2015},
pages = {430--436},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2811411.2811515},
doi = {10.1145/2811411.2811515},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/racs/ChenYLL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/TsaiCCC14,
author = {Meng{-}Ling Tsai and
Yi{-}Jung Chen and
Yi{-}Ting Chen and
Ru{-}Hua Chang},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Scenario-aware data placement and memory area allocation for Multi-Processor
System-on-Chips with reconfigurable 3D-stacked SRAMs},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--6},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.336},
doi = {10.7873/DATE.2014.336},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/TsaiCCC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/LinCYL13,
author = {Ping{-}Sheng Lin and
Yi{-}Jung Chen and
Chia{-}Lin Yang and
Yi{-}Chang Lu},
editor = {Pai H. Chou and
Ru Huang and
Yuan Xie and
Tanay Karnik},
title = {Exploring synergistic {DVFS} control of cores and DRAMs for thermal
efficiency in CMPs with 3D-stacked DRAMs},
booktitle = {International Symposium on Low Power Electronics and Design (ISLPED),
Beijing, China, September 4-6, 2013},
pages = {304},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISLPED.2013.6629313},
doi = {10.1109/ISLPED.2013.6629313},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/LinCYL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChenYC12,
author = {Yi{-}Jung Chen and
Chia{-}Lin Yang and
Jian{-}Jia Chen},
editor = {Alan J. Hu},
title = {Distributed memory interface synthesis for Network-on-Chips with 3D-stacked
DRAMs},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {458--465},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429479},
doi = {10.1145/2429384.2429479},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ChenYC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/LinSCYW12,
author = {Chung{-}Hsiang Lin and
De{-}Yu Shen and
Yi{-}Jung Chen and
Chia{-}Lin Yang and
Cheng{-}Yuan Michael Wang},
title = {{SECRET:} Selective error correction for refresh energy reduction
in DRAMs},
booktitle = {30th International {IEEE} Conference on Computer Design, {ICCD} 2012,
Montreal, QC, Canada, September 30 - Oct. 3, 2012},
pages = {67--74},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ICCD.2012.6378619},
doi = {10.1109/ICCD.2012.6378619},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/LinSCYW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ChenYCC11,
author = {Yi{-}Jung Chen and
Chia{-}Lin Yang and
Jaw{-}Wei Chi and
Jian{-}Jia Chen},
title = {{TACLC:} Timing-Aware Cache Leakage Control for Hard Real-Time Systems},
journal = {{IEEE} Trans. Computers},
volume = {60},
number = {6},
pages = {767--782},
year = {2011},
url = {https://doi.org/10.1109/TC.2011.44},
doi = {10.1109/TC.2011.44},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/ChenYCC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChenYW10,
author = {Yi{-}Jung Chen and
Chia{-}Lin Yang and
Po{-}Han Wang},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {{PM-COSYN:} {PE} and memory co-synthesis for MPSoCs},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {1590--1595},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5457064},
doi = {10.1109/DATE.2010.5457064},
timestamp = {Tue, 04 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/ChenYW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/ChenYC09,
author = {Yi{-}Jung Chen and
Chia{-}Lin Yang and
Yen{-}Sheng Chang},
title = {An architectural co-synthesis algorithm for energy-aware Network-on-Chip
design},
journal = {J. Syst. Archit.},
volume = {55},
number = {5-6},
pages = {299--309},
year = {2009},
url = {https://doi.org/10.1016/j.sysarc.2009.02.002},
doi = {10.1016/J.SYSARC.2009.02.002},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/ChenYC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jise/ChenDH07,
author = {Yi{-}Jung Chen and
Dyi{-}Rong Duh and
Yunghsiang Sam Han},
title = {Improved Modulo (2n+1) Multiplier for {IDEA}},
journal = {J. Inf. Sci. Eng.},
volume = {23},
number = {3},
pages = {911--923},
year = {2007},
url = {http://www.iis.sinica.edu.tw/page/jise/2007/200705\_16.html},
timestamp = {Fri, 16 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jise/ChenDH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/ChiYCC07,
author = {Jaw{-}Wei Chi and
Chia{-}Lin Yang and
Yi{-}Jung Chen and
Jian{-}Jia Chen},
editor = {Taewhan Kim and
Pascal Sainrat and
Steven S. Lumetta and
Nacho Navarro},
title = {Cache leakage control mechanism for hard real-time systems},
booktitle = {Proceedings of the 2007 International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems, {CASES} 2007, Salzburg, Austria,
September 30 - October 3, 2007},
pages = {248--256},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1289881.1289924},
doi = {10.1145/1289881.1289924},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/ChiYCC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sac/HungCYCS07,
author = {Wei{-}Hsuan Hung and
Yi{-}Jung Chen and
Chia{-}Lin Yang and
Yen{-}Sheng Chang and
Alan P. Su},
editor = {Yookun Cho and
Roger L. Wainwright and
Hisham Haddad and
Sung Y. Shin and
Yong Wan Koo},
title = {An architectural co-synthesis algorithm for energy-aware network-on-chip
design},
booktitle = {Proceedings of the 2007 {ACM} Symposium on Applied Computing (SAC),
Seoul, Korea, March 11-15, 2007},
pages = {680--684},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1244002.1244156},
doi = {10.1145/1244002.1244156},
timestamp = {Sun, 02 Jun 2019 21:18:37 +0200},
biburl = {https://dblp.org/rec/conf/sac/HungCYCS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aPcsac/YangWC06,
author = {Chia{-}Lin Yang and
Shun{-}Ying Wang and
Yi{-}Jung Chen},
editor = {Chris R. Jesshope and
Colin Egan},
title = {Branch Behavior Characterization for Multimedia Applications},
booktitle = {Advances in Computer Systems Architecture, 11th Asia-Pacific Conference,
{ACSAC} 2006, Shanghai, China, September 6-8, 2006, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4186},
pages = {523--530},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11859802\_53},
doi = {10.1007/11859802\_53},
timestamp = {Tue, 14 May 2019 10:00:42 +0200},
biburl = {https://dblp.org/rec/conf/aPcsac/YangWC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csreaSAM/ChenDH04,
author = {Yi{-}Jung Chen and
Dyi{-}Rong Duh and
Yunghsiang S. Han},
editor = {Hamid R. Arabnia and
Selim Aissi and
Youngsong Mun},
title = {A New Modulo (2\({}^{\mbox{n}}\)+1) Multiplier for {IDEA}},
booktitle = {Proceedings of the International Conference on Security and Management,
{SAM} '04, June 21-24, 2004, Las Vegas, Nevada, {USA}},
pages = {318--324},
publisher = {{CSREA} Press},
year = {2004},
timestamp = {Thu, 24 Feb 2011 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/csreaSAM/ChenDH04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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