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ORCIDAndreas Ehliar
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2010 – 2019
- 2014
[c10]Andreas Ehliar:
Area efficient floating-point adder and multiplier with IEEE-754 compatible semantics. FPT 2014: 131-138- [c9]Mario Garrido
, Miguel Acevedo, Andreas Ehliar, Oscar Gustafsson:
Challenging the limits of FFT performance on FPGAs (Invited paper). ISIC 2014: 172-175 - 2013
- [c8]Oscar Gustafsson, Andreas Ehliar:
Low-complexity general FIR filters based on Winograd's inner product algorithm. ISCAS 2013: 93-96 - 2012
- [c7]Andreas Ehliar:
EBRAM - Extending the BlockRAMs in FPGAs to Support Caches and Hash Tables in an Efficient Manner. FCCM 2012: 242 - no results
2000 – 2009
- 2009
- [b1]Andreas Ehliar:
Performance driven FPGA design with an ASIC perspective. Linköping University, Sweden, 2009 - [c6]Andreas Ehliar, Dake Liu:
An ASIC perspective on FPGA optimizations. FPL 2009: 218-223 - 2008
- [j1]Per Karlström, Andreas Ehliar, Dake Liu:
High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4. IET Comput. Digit. Tech. 2(4): 305-313 (2008) - [c5]Andreas Ehliar, Per Karlström, Dake Liu:
A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. FPL 2008: 599-602 - 2007
- [c4]Andreas Ehliar, Dake Liu:
An fpga based open source network-on-chip architecture. FPL 2007: 800-803 - 2005
- [c3]Andreas Ehliar, Dake Liu:
Flexible route lookup using range search. Communications and Computer Networks 2005: 345-350 - 2004
- [c2]Mikael Olausson, Andreas Ehliar, Johan Eilert, Dake Liu:
Reduced floating point for MPEG1/2 layer III decoding. ICASSP (5) 2004: 209-212 - [c1]Johan Eilert, Andreas Ehliar, Dake Liu:
Using low precision floating point numbers to reduce memory cost for MP3 decoding. MMSP 2004: 119-122 - no results
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