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ORCIDThe Journal of VLSI Signal Processing, Volume 11
Volume 11, Numbers 1-2, October 1995
- Magdy A. Bayoumi:
Introduction. 5-6 - Catherine H. Gebotys:
An optimal methodology for synthesis of DSP multichip architectures. 9-19 - Sati Banerjee, Paul M. Chau, Ronald D. Fellman:
Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems. 21-34 - Hyeong-Kyo Kim, Thomas P. Barnwell III:
A design synthesis system for recursive DSP algorithms represented by fully specified flow graphs. 35-50 - Mirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner:
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques. 51-74 - Ching-Yi Wang, Keshab K. Parhi:
Resource-constrained loop list scheduler for DSP algorithms. 75-96 - Marc Pauwels, Gert Goossens, Francky Catthoor, Hugo De Man:
Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures. 97-112 - Yoav Yaacoby, Peter R. Cappello:
Converting affine recurrence equations to quasi-uniform recurrence equations. 113-131 - Yin-Tsung Hwang, Yu Hen Hu:
A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays. 133-150 - Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili:
Design techniques for fault-tolerant systolic arrays. 151-168 - Nam Ling:
A special purpose formal verifier for systolic designs in DSP applications. 169-187
Volume 11, Number 3, December 1995
- Giuseppe Caire, Javier Ventura-Traveset, J. Murphy, Sun-Yuan Kung:
Parallel and pipelined VLSI implementation of a staged decoder for BCM signals. 195-211 - Kazuhito Ito, Keshab K. Parhi:
Determining the minimum iteration period of an algorithm. 229-244 - Qutaibah M. Malluhi, Magdy A. Bayoumi, T. R. N. Rao:
Tree-based special-purpose Array architectures for neural computing. 245-262 - Dusan Caf, David J. Evans:
A fast solution of banded circulant systems. 263-271 - Chen-Yi Lee, Jer-Min Tsai:
A shift register architecture for high-speed data sorting. 273-280
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