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Microprocessors and Microsystems, Volume 68
Volume 68, July 2019
- V. Suresh kumar, R. Manimegalai
:
Efficient test vector volume reduction based on equal run length coding technique. 1-10 - S. Gnanamurugan
, P. Sivakumar
:
Performance analysis of rectangular microstrip patch antenna for wireless application using FPGA. 11-16
- Prasanna Ravi
, Zakaria Najm, Shivam Bhasin
, Mustafa Khairallah
, Sourav Sen Gupta
, Anupam Chattopadhyay
:
Security is an architectural design constraint. 17-27
- M. Suresh, A. K. Panda, J. Sudhakar:
Low power aware standard cells using dual rail multi threshold null convention logic methodology. 28-33
- Leandro Soares Indrusiak
, James Harbin, Cezar Reinbrecht, Johanna Sepúlveda:
Side-channel protected MPSoC through secure real-time networks-on-chip. 34-46
- Med fehmi Chatmen
, Adel Baganne, Rached Tourki:
Low latency multicasting architecture implemented using new network topology. 47-57
- Cristina Silvano, Giovanni Agosta, Andrea Bartolini
, Andrea Rosario Beccari, Luca Benini
, Loïc Besnard, João Bispo
, Radim Cmar, João M. P. Cardoso
, Carlo Cavazzoni, Daniele Cesarini
, Stefano Cherubin
, Federico Ficarelli, Davide Gadioli, Martin Golasowski, Antonio Libri, Jan Martinovic
, Gianluca Palermo, Emanuele Vitali:
The ANTAREX domain specific language for high performance computing. 58-73
- Anastasios Fanariotis, Foteini Andriopoulou, Theofanis Orphanoudakis, Ilias Politis
:
An embedded framework enabling access of elderly and disabled persons to IP-based emergency communications. 74-83
- S. Vijayalakshmi, Velmurugan Nagarajan
:
Energy efficient low density parity check scheme for body channel communication using FPGA. 84-91 - R. Murugasami, U. S. Ragupathy:
Design and comparative analysis of D-Flip-flop using conditional pass transistor logic for high-performance with low-power systems. 92-101

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