default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Journal of Solid-State Circuits, Volume 61
Volume 61, Number 1, January 2026
- Boris Murmann:
New Associate Editor. 3 - Hyo Gyuem Rhew, Heein Yoon, Chia-Hsiang Yang, Utsav Banerjee, Xueqing Li:
Guest Editorial Introduction to the Special Section on the 2025 IEEE International Solid-State Circuits Conference (ISSCC). 4-7 - Jaewon Lee, Pier Andrea Francese
, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Seoyoung Jang, Yujin Choi, Donggeon Kim, Taekwang Jang, Gain Kim:
A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET. 8-19 - Ahmed E. AbdelRahman, Mohamed Badr Younis, Mohamed Osama Selim, Mohamed Saad Aly, Mahmoud A. Khalil, Pavan Kumar Hanumolu:
A 1.54-pJ/b 64-Gb/s 16-QAM Intradyne Coherent Optical Receiver in 28-nm CMOS. 20-32 - Susnata Mondal, Sashank Krishnamurthy, Junyi Qiu, Tolga Acikalin, Soumya Bose, Shuhei Yamada, James E. Jaussi, Mozhgan Mansuri:
A 108 Gb/s PAM-4 VCSEL-Based Direct-Drive Optical Engine for Co-Packaged Optics Applications. 33-46 - Yechen Tian, Junjie Gu, Weitao He, Shuai Liu, Rui Yin, Xiaoliang Shen, Long Kong, Hao Xu, Na Yan:
A 28-nm 8-28-GHz Eight-Phase Clock Generator Using an Injection-Locked Dual-Feedback Ring Oscillator. 47-62 - Tobias Webel, Phillip J. Restle, Ramon Bertran, Alper Buyuktosunoglu, Sean M. Carey, Alejandro Cook, Karl Anderson, Michael Romain, Thomas Strach, Pradeep Bhadravati Parashurama, Aishwarya Tadkase, Rahman Abber Tahir, Luke Jenkins, Kevin Low, Eberhard Engler:
Dynamic Guardband Features of the IBM z17 System. 63-77 - Hikmet Seha Öztürk, Julian Arenas, Carlos Tokunaga, Nasser A. Kurd, Visvesh S. Sathe:
A Compact, Highly-Digital Sensor-Fusion-Based Joint Vdd-Temperature Sensor for SoC Thermal Management. 78-89 - Haozhe Zhu, Bo Jiao, Yuman Zeng, Yongjiang Li, Jie Liao, Siyao Jia, Zexing Chen, Liyu Lin, Xuanda Lin, Suchang Huang, Mochen Tian, Jundong Zhu, Dexin Wen, Yan Wang, Yu Wang, Jian Xu, Feng Wang, Jun Tao, Chixiao Chen, Qi Liu, Ming Liu:
SHINSAI: A 586 mm2 Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory. 90-102 - Anjali Agrawal, Zhenghong Chen, Braden E. Desman, Jinhua Wang, Akiyoshi Tanaka, Fahim Foysal, Charlie D. Hess, Will Farrell, Jim Owens, Daniel S. Truesdell, Benton H. Calhoun:
kNOT: A 2-D Distributed Network-on-Textile Architecture With Direct Die-to-Yarn Integration of 0.6 × 2.15 mm2 SoC and bySPI Chiplets for Wearable Computing. 103-115 - Jaeho Kim, Myeongho Han, Hyunjun Song, Jooeun Bang, Younghyun Lim, Jaehyouk Choi:
A Command-Aware Hybrid LDO With Ultra-Small Voltage Droop and Fast Settling Time for Power-Supply-Induced Jitter Mitigation in HBM Interfaces. 116-128 - Gerald Strevig, David Wolpert, Leon Sigal, Bill Huott, Mark Cichanowski, Noam Jungmann, Michael A. Sperling, Michael J. Becht, Matthias Pflanz, Daniel Kiss, Simon Büchsenstein, Tobias Werner, Philipp Salz, Michael Romain, Richard E. Serton, Nick Jing, Rajesh Veerabhadraiah, Dureseti Chidambarrao, Robert Arelt, Matt Angyal, Ben Trombley, Arvind Haran, Rahul M. Rao, Christopher J. Berry, Amanda Venton, Elazar Kachir, Andreas Arp:
IBM Telum II Microprocessor: 5.5 GHz With On-Die AI and Data Processing, and Design-Technology Co-Optimizations for Power, Area, and Reliability. 129-141 - Srivatsa Rangachar Srinivasa, Dileep John Kurian, Paolo A. Aseron, Prerna Budhkar, Vinayak Honkote, Dan Lake, Mikhail J. Moiseev, Robert J. Munoz, Anuradha Srinivasan, Tanay Karnik:
A Standardized 20-Tb/s Bandwidth Scalable Heterogeneous 2.5-D System Supporting Assembly Time Workload-Dependent Chiplet Configurations. 142-153 - Seunghyun Moon, Mao Li, Gregory K. Chen, Phil C. Knag, Ram K. Krishnamurthy, Mingoo Seok:
T-REX: Hardware-Software Co-Optimized Transformer Accelerator With Reduced External Memory Access and Enhanced Hardware Utilization. 154-167 - Sangjin Kim, Jungjun Oh, Jeonggyu So, Yuseon Choi, Sangyeob Kim, Dongseok Im, Gwangtae Park, Hoi-Jun Yoo:
EdgeDiff: Energy-Efficient Multi-Modal Few-Step Diffusion Model Accelerator Using Mixed-Precision and Reordered Group Quantization. 168-182 - Seokchan Song, Seryeong Kim, Wonhoon Park, Jongjun Park, Sanghyuk An, Gwangtae Park, Minseo Kim, Hoi-Jun Yoo:
IRIS: An Energy-Efficient Spatial Computing SoC for Real-Time Interactive Rendering and Modeling With Surface-Aware 3-D Gaussian Splatting. 183-196 - Xiaoyu Feng, Hedi Wang, Huazhong Yang, Yongpan Liu:
An Edge 3-D Gaussian Splatting Processor Based on Shape-Aware Computation Architecture and Spatio-Temporal Gaussian Cache. 197-210 - Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device. 211-224 - De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks. 225-236 - Kosuke Yanagidaira, Mario Sako, Yasuhiro Hirashima, Yumi Higashi, Yutaka Shimizu, Takeshi Nakano, Yusuke Ochi, Hiroaki Yamada, Nobushi Matsuura, Akihiro Imamoto, Kazuaki Kawaguchi, Koji Tabata, Hiroaki Hoshino, Takeshi Hioka, Shigehito Saigusa, Hiroki Date, Masaki Unno, Jumpei Sato, You Kamata, Takahiro Shimizu, Akio Sugahara, Taira Shibuya, Atsushi Okuyama, Junji Yamada, Takatoshi Minamoto, Hardwell Chibvongodze, Naoki Ojima, Hiroshi Sugawara, Masahiro Kano, Jang-Woo Lee, Hiroyuki Mizukoshi, Ryuji Yamashita, Kensaku Abe, Naohito Morozumi, In-Soo Yoon, Takuya Ariki, Jong Hak Yuh, Khin Htoo, Yosuke Kato, Yoshihiro Oyama, Yen-Lung Jason Li, Yoshihisa Watanabe, Toshiyuki Kouchi, Koji Hosono:
A 29-Gb/mm2 1-Tb 3-b/Cell 3-D Flash Memory With CMOS Direct Bonded Array (CBA) Technology. 237-249 - Sang-Soo Park, Jaedoeg Lyu, Myungjun Kim, Jaeyun Lee, Youngsun Song, Chung-Ho Yu, Makoto Hirano, Yongseok Kwon, Jonghoon Park, Ho-Joon Kim, Daein Lee, Donghyun Seo, Philkyu Kang, Byungrok Go, Minseok Kim, Seoyoon Jeon, Jaehwan Ryu, Jungmin Seo, Hwan-Seok Ku, Youngmin Jo, Doo-Hyun Kim, Hyunjun Yoon, Wontae Kim, Inmo Kim, Sunghoon Kim, Jiho Cho, Moosung Kim, Jae-Woo Im, Jongmin Park, Youngdon Choi, Il-Han Park, Chiweon Yoon, Hyunsuk Kim, Jae-hoon Jang, Seungjae Lee, Ki-Whan Song, Sunghoi Hur:
A 28-Gb/mm2 4XX-Layer 1-Tb 3-b/Cell WF-Bonding 3D-nand Flash With 5.6-Gb/s/Pin IOs. 250-258 - Xiaofei Wang, Gwanghyeon Baek, Kunal Girish Bannore, Kaushal Dave, Arash Joushaghani, Minwoo Ko, Anandkumar Mahadevan Pillai, Hema Chandra Prakash Movva, Gyusung Park, Seenivasan Subramaniam, Teng Yang, Zheng Guo, Fatih Hamzaoglu, Eric A. Karl:
0.021-μm2 High-Density SRAM in Intel 18A RibbonFET Technology With PowerVia Backside Power Delivery. 259-266 - Kahyun Kim, Dae-Hoon Na, Jeongeun Song, Ha-Jung Park, Jin-Seok Heo, Hyunjun Park, Jihee Kim, Hanseok Kim, Hyeri Roh, Jung-Hun Park, Woo-Seok Choi:
A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces. 267-280 - Hui Zhang, Longyang Lin, Dingyi Xiong, Massimo Alioto:
Laser Voltage Probing Attack Detection via Leakage Shift Monitoring Without Dedicated Sensors at 4.35% Area Overhead. 281-292 - Hongzhi Wu, Xuxu Cheng, Weitao Wu, Liping Zhong, Catherine Wang, Yangyi Zhang, Xiongshi Luo, Dongfan Xu, Quan Pan:
A 128-Gb/s PAM-4 Transmitter With Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28-nm CMOS. 293-304 - Hwaseok Shin, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Junseob So, Seon-Been Lee, Taehwan Kim, Chulwoo Kim:
A 15-Gb/s PAM-3 Transceiver With Hybrid Equalization and Time-Domain Decoder for High-Bandwidth-Memory Interfaces. 305-317 - Xin Wang, Achim Vandierendonck, Bruno Govaerts, Tinus Pannier, Warre Geeroms, Caro Meysmans, Johan Bauwelinck, Guy Torfs:
A Duty-Cycle Switching 30-Gb/s Burst-Mode CDR With 1.6-ns Locking Time in 28-nm CMOS. 318-330 - Giacomo Castoro, Simone Mattia Dartizio, Michele Rossoni, Francesco Tesolin, Francesco Buccoleri, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A Low-Jitter Fractional- N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology. 331-342 - Gengzhen Qi, Pui-In Mak:
A Multi-Band RF Transmitter Employing a Transformer-Based N-Path Switched-Capacitor Modulator for CIM3 Suppression. 343-352 - Yutang Chen, Yuxuan Luo, Yifan Lin, Lei Shao, Dihu Chen, Jianping Guo:
A High-Efficiency Wireless Power Transfer System Under Wide Coupling Coefficient Range Based on Phase Shift and Near-Zero-Time Detection. 353-365 - Jiacheng Yang, Tingxu Hu, Yan Lu, Xin Ming, Rui Paulo Martins, Mo Huang:
Phase-Scalable CF-Cross-Connected-Based Hybrid DC-DC Converter With Auto VCF Balancing and Inactive CF Charging. 366-377 - Jee-Ho Park, Ji-Hyoung Cha, Yongjae Park, Seong-Jin Kim:
A Compact Photocurrent Recording IC With High-Linearity Dual PWM Buffered R-DACs. 378-390
Volume 61, Number 2, February 2026
- Tony Chan Carusone, Timothy O. Dickson, Samuel Palermo, Sudip Shekhar, Mozhgan Mansuri:
Modern Wireline Transceivers. 395-422 - Yen-Po Lin, Pen-Jui Peng, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh:
A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS. 423-433 - Suil Kang, Sinho Lee, Young-Wook Kim, Junhak Kim, Ho-Joon Shin, Haram Ju, Kwangho Lee, Kwanseo Park:
A 1.19-pJ/b 32-Gb/s Baud-Rate Receiver Employing 2UI Integrated Pattern-Based CDR and DFE Adaptation Without Data-Level Reference. 434-447 - Jaeho Lee, Kyongsu Lee, Jae-Yoon Sim, Seon-Kyoo Lee:
A 20-Gb/s/Line Single-Ended Transceiver With Coupling-Balanced Crosstalk-Cancellation for Shield-Less 1.5-μm-Pitch Interconnect. 448-459 - Susnata Mondal, Junyi Qiu, Sashank Krishnamurthy, Joseph T. Kennedy, Soumya Bose, Tolga Acikalin, Shuhei Yamada, James E. Jaussi, Mozhgan Mansuri:
A 4-Ch × 64 Gb/s/Ch NRZ VCSEL-Based Co-Packaged Fiber-Terminated Optical TX and 80-Gb/s Optical Driver. 460-474 - Weichen Tao, Yuhao Yang, Robert Bogdan Staszewski, Yizhe Hu:
A PLL Technique: Charge-Steering Sampling. 475-490 - Ruichen Wan, Wei Deng, Qixiu Wu, Haikun Jia, Rui Wu, Angxiao Yan, Haowen Cai, Sanming Hu, Zhihua Wang, Baoyong Chi:
A D-Band Distributed MIMO FMCW Radar CMOS Transceiver. 491-509 - Peng Gu, Enqi Zheng, Chenyu Xu, Huiqi Liu, Dixian Zhao:
Packaged K-/Ka-Band Down/Up Frequency Converter Chipsets for Phased Array SATCOM Ground Terminals in 65-nm CMOS. 510-524 - Masoud Pashaeifar, Leo C. N. de Vreede, Morteza S. Alavi:
A Millimeter-Wave Power Amplifier With an Integrated CMOS Isolator/Circulator/Receiver. 525-537 - Ahmed Afifi, Gabriel M. Rebeiz:
A Multi-Band 5.3-18 GHz LNA for FR3 Bands Using Hybrid Switching With Sub-2 dB NF in FDSOI. 538-548 - Xuan Wang, Xujun Ma, Yupeng Fu, Xu Wu, Dongming Wang, Lianming Li, Xiaohu You:
An 11-GHz Ultra-Fast Wideband FMCW Chirp Generator With 0.051% RMS Frequency Error Under 2.3-GHz Chirp Bandwidth and 2.3-GHz/μs Slope in 65-nm CMOS. 549-565 - Jae-Geun Lim, Jun-Ho Boo, Jae-Hyuk Lee, Hyoung-Jung Kim, Byeongho Yu, Kang-Il Cho, Sungho Lee, Un-Ku Moon, Gil-Cho Ahn:
A Hybrid Voltage-Time Domain Pipelined ADC With Reference-Embedded Time-Domain Residues. 566-577 - Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong, Yuan Wang, Xiyuan Tang:
An Easy-Driving Incremental Zoom ADC With Skipped Sampling Scheme and NS-SAR Quantizer. 578-588 - Xiongfei Jiang, Yuntao Han, Grahame Reynolds, Zhaoguang Si, Alfredo Gonzalez-Sulser, Themis Prodromakis, Shiwei Wang:
A Bi-Directional Neural Interface Chip With 32-Channel 83-dB DR CTDSM-Based Recording Using FIRDAC With Pre-Emptive ELD Compensation. 589-602 - Xinhang Xu, Siyuan Ye, Yaohui Luan, Jihang Gao, Jie Li, Jiajia Cui, Linxiao Shen:
A Highly Power-Efficient Input-Boosted First Stage for Capacitively Coupled Chopper Instrumentation Amplifiers. 603-614 - Xiangdong Feng, Zhiyu Wang, Yekan Chen, Tianyi Cai, Yangfan Xuan, Weixiao Wang, Yunshan Zhang, Changgui Yang, Zhong Tang, Yuxuan Luo, Bo Zhao:
A Capacitive Touch-Sensing Chip With NTF-Alignment Excitation Source and Direct Lock-In ADC. 615-628 - Minsu Kim, Woojoong Jung, Hyunjun Park, Junho Song, Youngkook Ahn, Taekyu Nam, Yoonsoo Shin, Young-Jin Woo, Hyung-Min Lee:
A 96.5% Efficiency Hybrid Step-Up Converter With Low Input-Level Voltage Stress and Duty-Independent Constant Inductor Current. 629-640 - Yuxiang Li, Jing Jin, Yuekang Guo, Jianjun Zhou, Junmin Jiang:
A 3-5 V to Sub-1 V DLDO-SC-Sigma Converter With Auxiliary Loop for Efficiency Improvement in High-Density Power Delivery. 641-650 - Dongfang Pan, Weiwei Xu, Xiangfeng Wu, Lin Cheng:
A 24-20-V Isolated DC-DC Converter Using a Transformer-Based Supply-Generating Technique. 651-661 - Yi-Hsiang Kao, Chi-Lung Lee, Chih-Cherng Liao, Hui-Hsuan Chang, Yu-Tse Shih, Yu-Chen Kuo, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
A 48-5-V Buck Converter With Triple EMI Suppression Circuit for Achieving 41-dB Peak EMI Reduction and Meeting CISPR 25 Automotive Standards. 662-672 - Peter Toth, Paul Shine Eugine, Yerzhan Kudabay, Kaoru Yamashita, Sebastian Halama, Judi Parvizinejad, Marco Bonkowski, Hiroki Ishikuro, Christian Ospelkaus, Vadim Issakov:
A Cryo-BiCMOS Controller for Quantum Computers based on Trapped Beryllium Ions. 673-689 - Tianqi Wang, Joydeep Basu, Viveka Konandur Rajanna, Massimo Alioto:
SRAM Static Entropy Extraction From Every Single Transistor in Unmodified Bitcell and Data Fingerprinting for Provenance Assurance. 690-703 - Clara Nieto-Taladriz, Wim Dehaene:
EMEP: Early-Monitoring Error Prediction for Activity and Variability Resilience in a 28-nm RISC-V Controller. 704-712 - Daniel Yingling, Yimai Peng, Robert Vachon, Dipti Pal, Sagar Jariwala, Felipe G. Cabral, Shih-Hsin Hu, Rajan Verma, Vamshidhar Chiranji, Anil Kumar, Santanu Sarma, Keith A. Bowman:
An Adaptive Clock Duty-Cycle Controller to Mitigate Aging-Induced Clock Duty-Cycle Distortion in Automotive and IoT Processors. 713-723 - Jungmyung Kang, Keonhee Cho, Sekeon Kim, Giseok Kim, Hyunjun Kim, Dongwook Seo, Sangyeop Baeck, Sei Seung Yoon, Seong-Ook Jung:
A 14 nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage With Minimal Power Overhead. 724-735 - Siqi He, Haozhe Zhu, Hongyi Zhang, Yujie Ma, Zexing Chen, Mengjie Li, Danfeng Zhai, Chixiao Chen, Qi Liu, Xiaoyang Zeng, Ming Liu:
A 22-nm 109.3-to-249.5-TFLOPS/W Outlier-Aware Floating-Point SRAM Compute-in-Memory Macro for Large Language Models. 736-749 - Sangwoo Ha, Soyeon Um, Sangjin Kim, Kyomin Sohn, Hoi-Jun Yoo:
Cache-PIM: An ECC-Compatible eDRAM Processing-in-Memory for Last-Level Cache With Triple-Level Error Correction. 750-762 - Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin:
ETCIM: Error-Tolerant Digital CIM Processor With Redundancy-Free Hard Error Repair and Run-Time Soft Error Correction. 763-776 - Yi Zhang, Wenyue Zhou, Yiwei Zhang, Houren Ji, Yongming Huang, Xiaohu You, Chuan Zhang:
BayesBB: A 9.6-Gb/s 1.61-ms Configurable All-Message-Passing Baseband-Accelerator for B5G/6G Cell-Free Massive-MIMO Systems. 777-790 - Ruixin Mao, Lin Tang, Zihan Xia, Aoyu Shen, Haojie Wei, Zhaomin Zhang, Yuncheng Lu, Yu Long, Jinhong Guo, Liang Zhou, Liang Chang, Shanshan Liu, Tony Tae-Hyoung Kim, Jun Zhou:
FSNAP: An Ultra-Energy-Efficient Reconfigurable Few-Spikes-Neuron-Based SNN Processor Supporting Unified On-Chip Learning and Adaptive Time-Window Tuning. 791-807
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-03-06 21:37 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
