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ORCIDFormal Methods in System Design, Volume 7
Volume 7, Number 1/2, August 1995
- David M. Russinoff:
A Formalization of a Subset of VHDL in the Boyer-Moore Logic. 7-25 - Peter T. Breuer
, Luis Sánchez Fernández, Carlos Delgado Kloos:
A Simple Denotational Semantics, Proof Theory and a Validation Condition Generator for Unit-Delay VHDL. 27-51 - Dominique Borrione, Ashraf M. Salem:
Denotational Semantics of a Synchronous VHDL Subset. 53-71 - Ralf Reetz, Thomas Kropf:
A Flowgraph Semantics of VHDL: Toward a VHDL Verification Workbench in HOL. 73-99 - Serafín Olcoz, José Manuel Colom:
A Colored Petri Net Model of VHDL. 101-123 - Gert Döhmen, Ronald Herrmann, Hergen Pargmann:
Translating VHDL into Functional Symbolic Finite-State Models. 125-148
Volume 7, Number 3, November 1995
- Scott F. Smith, Amy E. Zwarico:
Correct Compilation of Specifications to Deterministic Asynchronous Circuits. 155-226 - Patrice Godefroid, Gerard J. Holzmann, Didier Pirottin:
State-Space Caching Revisited. 227-241 - Huimin Lin:
PAM: A Process Algebra Manipulator. 243-259
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