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ORCIDDesign Automation for Embedded Systems, Volume 21
Volume 21, Number 1, March 2017
- Muhammad Waseem Anwar
, Muhammad Rashid, Farooque Azam, Muhammad Kashif:
Model-based design verification for embedded systems through SVOCL: an OCL extension for SystemVerilog. 1-36 - Saurav Kumar Ghosh, P. Vishnuvardhan, Satya Gautam Vadlamudi, Aritra Hazra, Soumyajit Dey, Partha Pratim Chakrabarti:
RELSPEC: a framework for reliability aware design of component based embedded systems. 37-87
Volume 21, Number 2, June 2017
- Burhan Khurshid:
LUT based realization of fixed-point multipliers targeting state-of-art FPGAs. 89-115 - Imane Hafnaoui, Rabeh Ayari, Gabriela Nicolescu, Giovanni Beltrame:
Scheduling real-time systems with cyclic dependence using data criticality. 117-136
Volume 21, Numbers 3-4, December 2017
- Alisson Vasconcelos de Brito, Antonio Carlos Schneider Beck Filho:
Special issue with selected papers from 2016 Brazilian Symposium on Computer Engineering (SBESC 2016). 137 - Gilles Silvano, Ivanovitch Silva, Leonardo Willer de Oliveira, Marcos Pinheiro, Bruno Ferreira:
LVWNet: an hybrid simulation architecture for wireless sensor networks. 139-155 - Jose de Sousa Barros, Thyago Oliveira, Vivek Nigam, Alisson V. Brito:
Analysis of design strategies for unmanned aerial vehicles using co-simulation. 157-172 - Mansureh Shahraki Moghaddam, M. Balakrishnan, Kiyoung Choi:
Optimal mapping of program overlays onto many-core platforms with limited memory capacity. 173-194 - R. Varatharajan:
Special issue on embedded systems in India. 195-196 - (Withdrawn) Test data compression for digital circuits using tetrad state skip scheme. 197-211
- Joel Josephson Pottipadu, R. Ramesh:
A novel algorithm for real-time framework in multiprocessor environment. 213-229 - S. Ravi, M. Joseph:
TTHLS: an HLS tool for testable hardware generation. 231-246 - Govindaraj Vellingiri, Ramesh Jayabalan:
An improved low transition test pattern generator for low power applications. 247-263 - D. Haripriya, C. Govindaraju, Manickam Sumathi:
A novel input data transition aware dynamic voltage scaling based low power MAC architecture for DSP applications. 265-281
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