default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Computer Architecture Letters, Volume 24
Volume 24, Number 1, January - June 2025
- Haseung Bong
, Nahyeon Kang, Youngsok Kim, Joonsung Kim, Hanhwi Jang:
IntervalSim++: Enhanced Interval Simulation for Unbalanced Processor Designs. 1-4 - Myoungjun Chun, Jae Yong Lee, Inhyuk Choi, Jisung Park, Myungsuk Kim, Jihong Kim:
Straw: A Stress-Aware WL-Based Read Reclaim Technique for High-Density NAND Flash-Based SSDs. 5-8 - Chaithanya Krishna Vadlamudi, Bahar Asgari:
Electra: Eliminating the Ineffectual Computations on Bitmap Compressed Matrices. 9-12 - Jiwon Lee, Yunjae Lee, Youngeun Kwon, Minsoo Rhu:
Characterization and Analysis of the 3D Gaussian Splatting Rendering Pipeline. 13-16 - Sepehr Tabrizchi, Mehrdad Morsali, David Z. Pan, Shaahin Angizi, Arman Roohi:
PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors. 17-20 - M. Vardhana, Rohan Pinto:
High-Performance Winograd Based Accelerator Architecture for Convolutional Neural Network. 21-24 - E. Kritheesh, Biswabandan Panda:
SPAM: Streamlined Prefetcher-Aware Multi-Threaded Cache Covert-Channel Attack. 25-28 - Houxiang Ji, Minho Kim, Seonmu Oh, Daehoon Kim, Nam Sung Kim:
Cooperative Memory Deduplication With Intel Data Streaming Accelerator. 29-32 - Woohyung Choi, Jinwoo Jeong, Hanhwi Jang, Jeongseob Ahn:
GPU-Centric Memory Tiering for LLM Serving With NVIDIA Grace Hopper Superchip. 33-36 - Jongho Baik, Jonghyeon Kim, Chang Hyun Park, Jeongseob Ahn:
Accelerating Page Migrations in Operating Systems With Intel DSA. 37-40 - Yunhyeong Jeon, Minwoo Jang, Hwanjun Lee, Yeji Jung, Jin Jung, Jonggeon Lee, Jinin So, Daehoon Kim:
RoPIM: A Processing-in-Memory Architecture for Accelerating Rotary Positional Embedding in Transformer Models. 41-44 - Sudhanva Gurumurthi, Mattan Erez:
Editorial: A Letter From the Editor-in-Chief of IEEE Computer Architecture Letters. iii-iv - Hyunwoo Nam, Jay Hwan Lee, Shinhyung Yang, Yeonsoo Kim, Jiun Jeong, Jeong-Geun Kim, Bernd Burgstaller:
Comprehensive Design Space Exploration for Graph Neural Network Aggregation on GPUs. 45-48 - Yanghui Ou, Hengrui Zhang, Austin Rovinski, David Wentzlaff, Christopher Batten:
Optically Connected Multi-Stack HBM Modules for Large Language Model Training and Inference. 49-52 - Byeori Kim, Changhun Lee, Gwangsun Kim, Eunhyeok Park:
Cost-Effective Extension of DRAM-PIM for Group-Wise LLM Quantization. 53-56 - Qirong Xia, Houxiang Ji, Yang Zhou, Nam Sung Kim:
Hardware-Accelerated Kernel-Space Memory Compression Using Intel QAT. 57-60 - Pooya Aghanoury, Santosh Ghosh, Nader Sehatbakhsh:
Security Helper Chiplets: A New Paradigm for Secure Hardware Monitoring. 61-64 - Yuanmiao Lin, Shansen Fu, Xueming Li, Chaoming Yang, Rongfeng Li, Hongmin Huang, Xianghong Hu, Shuting Cai, Xiaoming Xiong:
A DSP-Based Precision-Scalable MAC With Hybrid Dataflow for Arbitrary-Basis-Quantization CNN Accelerator. 65-68 - Farshad Dizani, Azam Ghanbari, Joshua Kalyanapu, Darsh Asher, Samira Mirbagher Ajorpaz:
Thor: A Non-Speculative Value Dependent Timing Side Channel Attack Exploiting Intel AMX. 69-72 - Omer Khan:
A Data Prefetcher-Based 1000-Core RISC-V Processor for Efficient Processing of Graph Neural Networks. 73-76 - Zhenlong Ma, Ning Kang, Fan Yang, Chongyang Hong, Jing Xu, Guojun Yuan, Peiheng Zhang, Zhan Wang, Ninghui Sun:
Toward Scalable RDMA Through Resource Prefetching. 77-80 - Zhengpan Fei, Mingchuan Lyu, Satoshi Kawakami, Koji Inoue:
Data-Pattern-Driven LUT for Efficient In-Cache Computing in CNNs Acceleration. 81-84 - Taehun Kim, Yunjae Lee, Juntaek Lim, Minsoo Rhu:
A Characterization of Generative Recommendation Models: Study of Hierarchical Sequential Transduction Unit. 85-88 - Pawan Kumar Sanjaya, Christina Giannoula, Ian Colbert, Ihab Amer, Mehdi Saeedi, Gabor Sines, Nandita Vijaykumar:
DPWatch: A Framework for Hardware-Based Differential Privacy Guarantees. 89-92 - Amin Mamandipoor, Huy Dinh Tran, Mohammad Alian:
SDT: Cutting Datacenter Tax Through Simultaneous Data-Delivery Threads. 93-96 - Chihun Song, Michael Jaemin Kim, Yan Sun, Houxiang Ji, Kyungsan Kim, TaeKyeong Ko, Jung Ho Ahn, Nam Sung Kim:
X-PPR: Post Package Repair for CXL Memory. 97-100 - Hossein SeyyedAghaei, Mahmood Naderan-Tahan, Magnus Jahre, Lieven Eeckhout:
Memory-Centric MCM-GPU Architecture. 101-104 - Shvetank Prakash, Andrew Cheng, Jason Yik, Arya Tschand, Radhika Ghosal, Ikechukwu Uchendu, Jessica Quaye, Jeffrey Ma, Shreyas Grampurohit, Sofia Giannuzzi, Arnav Balyan, Fin Amin, Aadya Pipersenia, Yash Choudhary, Ankita Nayak, Amir Yazdanbakhsh, Vijay Janapa Reddi:
QuArch: A Question-Answering Dataset for AI Agents in Computer Architecture. 105-108 - Heng Cao, Zhipeng Wu, Dejian Li, Peiguang Jing, Sio-Hang Pun, Yu Liu:
Accelerating Control Flow on CGRAs via Speculative Iteration Execution. 109-112 - Joshua Kalyanapu, Farshad Dizani, Azam Ghanbari, Darsh Asher, Samira Mirbagher Ajorpaz:
Exploiting Intel AMX Power Gating. 113-116 - Liang Yan, Xiaoyang Lu, Xiaoming Chen, Yinhe Han, Xian-He Sun:
Pyramid: Accelerating LLM Inference With Cross-Level Processing-in-Memory. 121-124 - Adnan Hasnat, Wim Heirman, Shoaib Akram:
Analyzing and Exploiting Memory Hierarchy Parallelism With MLP Stacks. 125-128 - Daniel Puckett, Tyler Tomer, Paul V. Gratz, Jiang Hu, Galen M. Shipman, Jered Dominguez-Trujillo, Kevin Sheridan:
Estimating CPI Stacks From Multiplexed Performance Counter Data Using Machine Learning. 129-132 - Shabirahmed Badashasab Jigalur, Daniel J. Mazure, Teresa C. Garcia, Yen-Cheng Kuan:
Accelerating Vector Permutation Instruction Execution via Controllable Bitonic Network. 133-136 - Aalaa M. A. Babai, Koji Inoue:
Exploring Volatile FPGAs Potential for Accelerating Energy-Harvesting IoT Applications. 137-140 - Daeun Kim, Jinwoo Hwang, Changhun Oh, Jongse Park:
MixDiT: Accelerating Image Diffusion Transformer Inference With Mixed-Precision MX Quantization. 141-144 - TaeHoon Kim, Jaechun No:
L-DTC: Load-based Dynamic Throughput Control for Guaranteed I/O Performance in Virtualized Environments. 145-148 - Arteen Abrishami, Zhengrong Wang, Tony Nowatzki:
Cache and Near-Data Co-Design for Chiplets. 149-152 - Mattia Tibaldi, Christian Pilato:
Amethyst: Reducing Data Center Emissions With Dynamic Autotuning and VM Management. 153-156 - Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández Pascual, Manuel E. Acacio, Alberto Ros:
WoperTM: Got Nacks? Use Them! 157-160 - Rui Liu, Zerun Li, Xiaoyu Zhang, Xiaoming Chen, Yinhe Han, Minghua Tang:
In-Memory Computing Accelerator for Iterative Linear Algebra Solvers. 161-164 - Minseok Seo, Jungi Hyun, Seongho Jeong, Xuan Truong Nguyen, Hyuk-Jae Lee, Hyokeun Lee:
OASIS: Outlier-Aware KV Cache Clustering for Scaling LLM Inference in CXL Memory Systems. 165-168
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-06-12 22:34 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
