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ORCID16th WCET 2016: Toulouse, France
- Martin Schoeberl:
16th International Workshop on Worst-Case Execution Time Analysis, WCET 2016, July 5, 2016, Toulouse, France. OASIcs 55, Schloss Dagstuhl - Leibniz-Zentrum für Informatik 2016, ISBN 978-3-95977-025-5 - Front Matter, Table of Contents, Preface, List of Authors, Committee. 0:i-0:xii
- Enrique Díaz, Jaume Abella
, Enrico Mezzetti, Irune Agirre, Mikel Azkarate-askasua, Tullio Vardanega, Francisco J. Cazorla:
Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis. 1:1-1:11 - Heiko Falk, Sebastian Altmeyer, Peter Hellinckx, Björn Lisper, Wolfgang Puffitsch, Christine Rochange, Martin Schoeberl, Rasmus Bo Sørensen, Peter Wägemann, Simon Wegener:
TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research. 2:1-2:10 - Vincent Mussot, Jordy Ruiz, Pascal Sotin, Marianne De Michiel, Hugues Cassé:
Expressing and Exploiting Conflicts over Paths in WCET Analysis. 3:1-3:11 - Boris Dreyer, Christian Hochberger, Alexander Lange, Simon Wegener, Alexander Weiss:
Continuous Non-Intrusive Hybrid WCET Estimation Using Waypoint Graphs. 4:1-4:11 - Amine Naji, Florian Brandner:
Eager Stack Cache Memory Transfers. 5:1-5:11 - Vincent Nélis, Patrick Meumeu Yomsi, Luís Miguel Pinho:
The Variability of Application Execution Times on a Multi-Core Platform. 6:1-6:11 - Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou:
BEST: a Binary Executable Slicing Tool. 7:1-7:10 - Wei-Tsun Sun, Hugues Cassé:
Dynamic Branch Resolution Based on Combined Static Analyses. 8:1-8:10 - Leonidas Kosmidis, Davide Compagnin, David Morales, Enrico Mezzetti, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla:
Measurement-Based Timing Analysis of the AURIX Caches. 9:1-9:11 - Martin Frieb, Alexander Stegmeier, Jörg Mische, Theo Ungerer:
Employing MPI Collectives for Timing Analysis on Embedded Multi-Cores. 10:1-10:11 - Christine Rochange:
Parallel Real-Time Tasks, as Viewed by WCET Analysis and Task Scheduling Approaches. 11:1-11:11 - Andreas Löfwenmark, Simin Nadjm-Tehrani:
Understanding Shared Memory Bank Access Interference in Multi-Core Avionics. 12:1-12:11
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