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ORCID11th NoCArc@MICRO 2018: Fukuoka City, Japan
- 11th International Workshop on Network on Chip Architectures, NoCArc@MICRO 2018, Fukuoka, Japan, October 20, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-8552-5
- Chun-Hsian Huang, Ching-Yen Chen, Hung-Yu Huang:
Hierarchical and Dependency-Aware Task Mapping for NoC-based Systems. 1-6 - Pieter Stroobant, Sergi Abadal
, Wouter Tavernier, Eduard Alarcón, Didier Colle, Mario Pickavet:
A General, Fault tolerant, Adaptive, Deadlock-free Routing Protocol for Network-on-chip. 1-6 - Andreas Moshovos:
Value-Based Deep Learning Hardware Acceleration. 1 - Poona Bahrebar, Dirk Stroobandt:
3D MAX: A Maximally Adaptive Routing Method for VC-less 3D Mesh-based Networks-on-Chip. 1-6 - Stanislaw Deniziak, Robert Tomaszewski:
Codesign of energy and resource efficient contention-free Network-on Chip for real-time embedded systems. 1-6 - Alireza Namazi, Meisam Abdollahi, Saeed Safari, Siamak Mohammadi, Masoud Daneshtalab:
LRTM: Life-time and Reliability-aware Task Mapping Approach for Heterogeneous Multi-core Systems. 1-6 - Ivan Perez, Enrique Vallejo, Ramón Beivide:
Efficient Router Bypass via Hybrid Flow Control. 1-6 - Mostafa Khamis, Sameh El-Ashry, Ahmed Shalaby, Mohamed Abdelsalam, M. Watheq El-Kharashi:
A Configurable RISC-V for NoC-Based MPSoCs: A Framework for Hardware Emulation. 1-6 - Taqwa Saeed, Constantinos Skitsas, Dimitrios Kouzapas, Marios Lestas, Vassos Soteriou, Anna Philippou, Sergi Abadal, Christos Liaskos, Loukas Petrou, Julius Georgiou, Andreas Pitsillides:
Fault Adaptive Routing in Metasurface Controller Networks. 1-6 - Shih-Hsu Huang:
Keynote Talk: 3D Core-based SoC Testing for Low Power and TSV Count Minimization. 1 - Kun-Chih Jimmy Chen, Ting-Yi Wang:
NN-Noxim: High-Level Cycle-Accurate NoC-based Neural Networks Simulator. 1-5
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