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Semantic Scholar28th HICSS 1995: Maui, Hawaii, USA - Volume 1
28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA. IEEE Computer Society 1995, ISBN 0-8186-6945-4
Volume 1
High Performance Computing and I/O Systems
- Keying Wu, P. K. H. Ng, Xing Dong Jia, Richard M. M. Chen, A. M. Layfield:
Performance tuning of a multiprocessor sparse matrix equation solver. 4-13 - Glenn Jennings:
Symbolic incompletely specified functions for correct evaluation in the presence of indeterminate input values. 23-31 - Dejan Raskovic, Emil Jovanov, Aleksandar Janicijevic, Veljko M. Milutinovic:
An implementation of hash based ATM router chip. 32-40 - Catherine H. Gebotys, Robert J. Gebotys:
Optimized mapping of video applications to hardware-software for VLSI architectures. 41-48 - Kuei Yu Wang, Dan C. Marinescu:
Correlation of the paging activity of individual node programs in the SPMD execution mode. 61-73
Reflective Memory and Distributed Shared Memory Architectures for OLTP
- Jelica Protic, Milo Tomasevic, Veljko M. Milutinovic:
A survey of distributed shared memory systems. 74-84 - Mark Natale, Mark Baker, Roger Collins, David Wilson, Stephen Lucci, Izidor Gertner:
Pentium MPP for OLTP applications. 95-102 - Mark Aldred, Ilya Gertner, Stephen McKellar:
A distributed lock manager on fault tolerant MPP. 134-136 - Milan M. Jovanovic, Milo Tomasevic, Veljko M. Milutinovic:
A simulation-based comparison of two reflective memory approaches. 140-152
Instruction Level Parallelism
- Instruction Level Parallelism. 151-152
- Siamak Arya, Howard Sachs, Sreeram Duvvuru:
An architecture for high instruction level parallelism. 153-162 - John G. Cleary, Murray Pearson, Husam Kinawi:
The architecture of an optimistic CPU: the WarpEngine. 163-172 - Thomas Scholz, Michael Schäfers:
An improved dynamic register array concept for high-performance RISC processors. 181-190 - Marc Tremblay, Bill Joy, Ken Shin:
A three dimensional register file for superscalar processors. 191-201 - Chi-Hung Chi, Chi-Sum Ho, Siu-Chung Lau:
Reducing memory latency using a small software driven array cache. 202-210 - Roger A. Bringmann, Scott A. Mahlke, Wen-mei W. Hwu:
A study of the effects of compiler-controlled speculation on instruction and data caches. 211-220 - Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor:
A comparative evaluation of software techniques to hide memory latency. 229-241
Scalable Shared-Memory Architectures
- Introduction. 240-241
- Mårten Björkman, Fredrik Dahlgren, Per Stenström:
Using hints to reduce the read miss penalty for flat COMA protocols. 242-251 - Alexandre E. Eichenberger, Santosh G. Abraham:
Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors. 262-271 - Igor Tartalja, Veljko M. Milutinovic:
A survey of software solutions for maintenance of cache consistency in shared memory multiprocessors. 272-287
Low Energy ILP Processors
- John Bunda, Donald S. Fussell, William C. Athas:
Energy-efficient instruction set architecture for CMOS microprocessors. 298-305 - Priyadarsan Patra, Donald S. Fussell:
Power-efficient delay-insensitive codes for data transmission. 316-323 - Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye:
A technique to determine power-efficient, high-performance superscalar processors. 324-333
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