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Semantic Scholar5. FPGA 1997: Monterey, CA, USA
Carl Ebeling:
Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, FPGA 1997, Monterey, CA, USA, February 9-11, 1997. ACM 1997, ISBN 0-89791-801-0- Steven Trimberger, Khue Duong, Bob Conn:
Architecture Issues and Solutions for a High-Capacity FPGA. 3-9 - Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic:
Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. 10-16 - Glenn H. Chapman, Benoit Dufort:
Laser Correcting Defects to Create Transparent Routing for Large Area FPGA's. 17-23 - Frank Vahid:
I/O and Performance Tradeoffs with the FunctionBus During Multi-FPGA Partitioning. 27-34 - Jason Cong, Yean-Yow Hwang:
Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. 35-42 - Amit Chowdhary, John P. Hayes:
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs. 43-49 - David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow:
The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. 53-61 - Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen:
Module Generation of Complex Macros for Logic-Emulation Applications. 69-75 - Michael J. Wirthlin, Brad L. Hutchings:
Improving Functional Density Through Run-Time Constant Propagation. 86-92 - Akihiro Tsutsui, Toshiaki Miyazaki:
YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing. 93-100 - Helena Krupnova, Christian Rabedaoro, Gabriele Saucier:
Synthesis and Floorplanning for Large Hierarchical FPGAs. 105-111 - R. Glenn Wood, Rob A. Rutenbar:
FPGA Routing and Routability Estimation via Boolean Satisfiability. 119-125 - Jonathan Rose, Dwight D. Hill:
Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond. 129-132 - Douglas Chang, Malgorzata Marek-Sadowska:
Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs. 142-148 - Michael D. Hutton, Jonathan Rose, Derek G. Corneil:
Generation of Synthetic Sequential Benchmark Circuits. 149-155 - Alexandre F. Tenca, Milos D. Ercegovac:
Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size. 159-165 - Monica Alderighi, E. L. Gummati, Vincenzo Piuri, Giacomo R. Sechi:
A FPGA-Based Implementation of a Fault-Tolerant Neural Architecture for Photon Identification. 166-172
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