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ORCID19th FMCAD 2019: San Jose, CA, USA
- Clark W. Barrett, Jin Yang:
2019 Formal Methods in Computer Aided Design, FMCAD 2019, San Jose, CA, USA, October 22-25, 2019. IEEE 2019, ISBN 978-0-9835678-9-9 - Dorsa Sadigh:
Safe and Interactive Autonomy: A Journey Starting from Formal Methods (Keynote). 1 - Martin Dixon:
An Increasing Need for Formality (Keynote). 1 - Nadia Polikarpova:
SuSLik: Synthesis of Safe Pointer-Manipulating Programs (Invited Tutorial). 1 - Grigory Fedyukovich:
The FMCAD 2019 Student Forum. 1 - Avi Ziv:
Challenges and Solutions in Post-Silicon Validation of High-end Processors (Invited Tutorial). 1 - Mark R. Greenstreet:
Integrating SMT with Theorem Proving for Verification of Analog and Mixed-Signal Circuits (Invited Tutorial). 1 - Rohit Dureja
, Jason Baumgartner, Alexander Ivrii, Robert Kanzelman, Kristin Y. Rozier:
Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties. 1-9 - Raj Kumar Gajavelly, Jason Baumgartner, Alexander Ivrii, Robert L. Kanzelman, Shiladitya Ghosh:
Input Elimination Transformations for Scalable Verification and Trace Reconstruction. 10-18 - Ryan Berryhill, Andreas G. Veneris:
Chasing Minimal Inductive Validity Cores in Hardware Model Checking. 19-27 - Daniela Kaufmann, Armin Biere, Manuel Kauers:
Verifying Large Multipliers by Combining SAT and Computer Algebra. 28-36 - Jakub Kuderski, Jorge A. Navas, Arie Gurfinkel:
Unification-based Pointer Analysis without Oversharing. 37-45 - Freark I. van der Berg, Jaco van de Pol:
Concurrent Chaining Hash Maps for Software Model Checking. 46-54 - Benjamin Ogles, Peter Aldous, Eric Mercer:
Proving Data Race Freedom in Task Parallel Programs Using a Weaker Partial Order. 55-63 - Nina Narodytska, Leonid Ryzhyk, Igor Ganichev, Soner Sevinc:
BDD-Based Algorithms for Packet Classification. 64-68 - Aellison Cassimiro T. dos Santos, Ben Schneider, Vivek Nigam:
TSNSCHED: Automated Schedule Generation for Time Sensitive Networking. 69-77 - Ali Ebnenasir:
Verification and Synthesis of Symmetric Uni-Rings for Leads-To Properties. 78-86 - Amer Tahat, Sarang Joshi, Pronnoy Goswami, Binoy Ravindran:
Scalable Translation Validation of Unverified Legacy OS Code. 87-95 - Faria Kalim, Karl Palmskog, Jayasi Mehar, Adithya Murali, Indranil Gupta, P. Madhusudan:
Kaizen: Building a Performant Blockchain System Verified for Consensus and Integrity. 96-104 - Luca Piccolboni, Giuseppe Di Guglielmo, Luca P. Carloni:
KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design. 105-109 - Sujit Kumar Muduli, Pramod Subramanyan, Sayak Ray:
Verification of Authenticated Firmware Loaders. 110-119 - Daniel Neider, Oliver Markgraf:
Learning-Based Synthesis of Safety Controllers. 120-128 - Meng Wu, Jingbo Wang, Jyotirmoy Deshmukh, Chao Wang:
Shield Synthesis for Real: Enforcing Safety in Cyber-Physical Systems. 129-137 - Gideon Geier, Philippe Heim, Felix Klein, Bernd Finkbeiner:
Syntroids: Synthesizing a Game for FPGAs using Temporal Logic Specifications. 138-146 - Roderick Bloem, Hana Chockler, Masoud Ebrahimi, Ofer Strichman:
Synthesizing Reactive Systems Using Robustness and Recovery Specifications. 147-151 - Dmitry Mordvinov, Grigory Fedyukovich:
Property Directed Inference of Relational Invariants. 152-160 - S. Akshay, Jatin Arora, Supratik Chakraborty, Shankara Narayanan Krishna, Divya Raghunathan, Shetal Shah:
Knowledge Compilation for Boolean Functional Synthesis. 161-169 - Gilles Barthe, Renate Eilers, Pamina Georgiou, Bernhard Gleiss, Laura Kovács, Matteo Maffei:
Verifying Relational Properties using Trace Logic. 170-178 - Oliver Kullmann, Ankit Shukla:
Autarkies for DQCNF. 179-183 - Aile Ge-Ernst, Christoph Scholl, Ralf Wimmer:
Localizing Quantifiers for DQBF. 184-192 - Alexander Nadel:
Anytime Weighted MaxSAT with Improved Polarity Selection and Bit-Vector Optimization. 193-202 - Rafael Dutra, Jonathan Bachrach, Koushik Sen:
GUIDEDSAMPLER: Coverage-guided Sampling of SMT Solutions. 203-211 - Haniel Barbosa, Andrew Reynolds, Daniel Larraz, Cesare Tinelli:
Extending enumerative function synthesis via SMT-driven classification. 212-220 - Florian Frohn, Jürgen Giesl:
Proving Non-Termination via Loop Acceleration. 221-230
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