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ORCID5th ACAC 2000: Canberra, ACT, Australia
- 5th Australasian Computer Architecture Conference (ACAC 2000), 31 January - 3 February 2000, Canberra, Australia. IEEE Computer Society 2000, ISBN 0-7695-0512-0
- Hon Nin Cheung, Li-Minn Ang
, Kamran Eshraghian:
Parallel Architecture for the Implementation of the Embedded Zerotree Wavelet Algorithm. 3-8 - Wanming Chu, Yamin Li:
Cost/Performance Tradeoff of n-Select Square Root Implementations. 9-16 - Lieven Eeckhout, Koen De Bosschere, Henk Neefs:
On the Feasibility of Fixed-Length Block Structured Architectures. 17-25 - Bernard K. Gunther:
The Circuit Object Organization Library. 26-33 - Chris R. Jesshope, Bing Luo:
Micro-Threading: A New Approach to Future RISC. 34-41 - Gareth Lee, John Morris:
Dataflow Java: Implicitly Parallel Java. 42-50 - T. Lund, Antonio Jesús Torralba Silgado, Ramón González Carvajal:
The Architecture of an FPGA-Style Programmable Fuzzy Logic Controller Chip. 51-56 - Bruce McClure, T. A. Au, Jadwiga Indulska:
Adaptive Middleware for Heterogeneous Defense Networks-An Exploratory Simulation Study. 57-63 - John Morris, Gary A. Bundell, Sonny Tham:
A Scalable Re-Configurable Processor. 64-73 - Partha S. Roop, Arcot Sowmya, S. Ramesh:
Automated Component Adaptation by Forced Simulation. 74-81 - Christian Siemers, Sybille Siemers:
Reconfigurable Computing Based on Universal Configurable Blocks-A New Approach for Supporting Performance- and Realtime-Dominated Applications. 82-89 - Daniel Tate, Gordon B. Steven, Fleur L. Steven:
Static Scheduling for Out-of-order Instruction Issue Processors. 90-96 - Adam Wiggins, Gernot Heiser:
Fast Address-Space Switching on the StrongARM SA-1100 Processor. 97-
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