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Publication search results
found 107 matches
- 2024
- Bing-Xun Song, Ting Xin Lin, Yih-Lang Li:
Routability Booster " Synthesize a Routing Friendly Standard Cell Library by Relaxing BEOL Resources. ISPD 2024: 185-193 - 2023
- Xinfa Zhang, Zuodong Zhang, Yibo Lin, Zhigang Ji, Runsheng Wang, Ru Huang:
Efficient Aging-Aware Standard Cell Library Characterization Based on Sensitivity Analysis. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 721-725 (2023) - Taehak Kim, Jaehoon Jeong, Seungmin Woo, Jeonggyu Yang, Hyunwoo Kim, Ahyeon Nam, Changdong Lee, Jinmin Seo, Minji Kim, Siwon Ryu, Yoonju Oh, Taigon Song:
NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact. IEEE Trans. Very Large Scale Integr. Syst. 31(2): 163-176 (2023) - Digvijay Rajurkar, Vidya Sagar Reddy Gopala, Srimathi Govindan:
Parasitic Extraction Modeling for Standard Cell Library on Intel 4 Technology. MWSCAS 2023: 64-68 - 2022
- Qingyang Zeng, Yeye Zhang, Delong Shang:
Design of low latency asynchronous arbiter based on standard cell library. IEICE Electron. Express 19(19): 20220265 (2022) - Yuki Imai, Shinichi Nishizawa, Kazuhito Ito:
Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 487-496 (2022) - Abubaker Sasi, Arash Ahmadi, Majid Ahmadi:
Characterizing a standard cell library for large scale design of memristive based signal processing. IET Circuits Devices Syst. 16(1): 13-25 (2022) - Yuting Chen, Yuxuan Nie, Hailong Jiao:
An Ultralow-Power 65-nm Standard Cell Library for Near/Subthreshold Digital Circuits. IEEE Trans. Very Large Scale Integr. Syst. 30(5): 676-680 (2022) - Roman Gauchi, Ashton Snelgrove, Pierre-Emmanuel Gaillardon:
An Open-source Three-Independent-Gate FET Standard Cell Library for Mixed Logic Synthesis. ISCAS 2022: 273-277 - Tingyuan Liang, Jingsong Chen, Lei Li, Wei Zhang:
AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining. CoRR abs/2207.12314 (2022) - 2021
- Kotaro Matsuoka, Yusuke Hoshizuki, Takashi Sato, Song Bian:
Towards Better Standard Cell Library: Optimizing Compound Logic Gates for TFHE. WAHC@CCS 2021: 63-68 - Suren Abazyan:
Standard Cell Library Enhancement For Mixed Multi-Height Cell Design Implementation. EWDTS 2021: 1-4 - Suren Abazyan, Shavarsh Melikyan, Davit Musayelyan:
Standard Cell Library Enhancement Using Neural Network Based Sleep Mode Control Integration For Low Leakage Designs. EWDTS 2021: 1-4 - Laysson Oliveira Luz, José Augusto Miranda Nacif, Ricardo S. Ferreira, Omar P. Vilela Neto:
NMLib: A Nanomagnetic Logic Standard Cell Library. ISCAS 2021: 1-5 - Akshay Kamath, Bharath Kumar, Sunil Aggarwal, Subramanian Parameswaran, Mitesh Goyal, Parag Lonkar, Somasunder Sreenath:
A Comprehensive Multi-Voltage Design Platform for System-Level Validation of Standard Cell Library. ISQED 2021: 285-291 - Digvijay Rajurkar, Sivakumar Venkataraman:
Pre-placement evaluation of Standard Cell Library compliance to Process Density constraints. MWSCAS 2021: 236-240 - Dmytro Petryk, Zoya Dyka, Peter Langendörfer:
Sensitivity of Standard Library Cells to Optical Fault Injection Attacks in IHP 250 nm Technology. CoRR abs/2103.12433 (2021) - 2020
- Liang Wen, Longmei Nan, Jing Zhang, Chunning Meng, Yan Lu, Shiqian Qi, Jianping Lv, Yuejun Zhang:
65 nm sub-threshold logic standard cell library using quasi-Schmitt-trigger design scheme and inverse narrow width effect aware sizing. IET Circuits Devices Syst. 14(3): 303-310 (2020) - Ting-Jung Chang, Zhuozhi Yao, Barry P. Rand, David Wentzlaff:
Organic-Flow: An Open-Source Organic Standard Cell Library and Process Development Kit. DATE 2020: 49-54 - Anuradha Chathuranga Ranasinghe, Sabih H. Gerez:
MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ Computing. ICCD 2020: 96-104 - Yue Yin, Songyao Tan, Peilin Yang, Hanjun Jiang, Zhihua Wang:
A Customized Low Static Leakage Near/Sub-threshold Standard Cell Library Using Thick-gate Transistors. ICTA 2020: 75-76 - Vibhav Kumarswami Salimath, Carl Sechen:
Optimal Standard Cell Library Composition for 7nm. ISCAS 2020: 1-5 - Yuan-Dar Chung, Rung-Bin Lin:
Engineering a Standard Cell Library for an Industrial Router with ASAP7 PDK. ISVLSI 2020: 404-409 - Dmytro Petryk, Zoya Dyka, Peter Langendörfer:
Sensitivity of Standard Library Cells to Optical Fault Injection Attacks in IHP 250 nm Technology. MECO 2020: 1-4 - AbdelRahman Hesham, Amin M. Nassar, Hassan Mostafa:
Energy-Efficient Near-Threshold Standard Cell Library for IoT Applications. NILES 2020: 567-572 - (Withdrawn) A Custom 7nm CMOS Standard Cell Library for Implementing TNN-based Neuromorphic Processors. CoRR abs/2012.05419 (2020)
- 2019
- Yang Wei Lim, Noor Ain Kamsani, Roslina Mohd Sidek, Shaiful Jahari Hashim, Fakhrul Zaman Rokhani:
Six-track multi-finger standard cell library design for near-threshold voltage operation in 130 nm complementary metal oxide semiconductor technology. IET Circuits Devices Syst. 13(5): 710-716 (2019) - Vijay Kumar Sharma:
Designing of Standard Cell Library for GBONOR Approach. ACOMP 2019: 147-151 - Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang:
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. AsianHOST 2019: 1-7 - Shaolan Li, Biying Xu, David Z. Pan, Nan Sun:
A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library. CICC 2019: 1-4
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