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Publication search results
found 18 matches
- 2023
- Thilo L. Fischer, Heiko Falk:
Analysis of Shared Cache Interference in Multi-Core Systems using Event-Arrival Curves. RTNS 2023: 23-33 - 2022
- Jun Xiao, Yixian Shen, Andy D. Pimentel:
Cache Interference-aware Task Partitioning for Non-preemptive Real-time Multi-core Systems. ACM Trans. Embed. Comput. Syst. 21(3): 28:1-28:28 (2022) - 2021
- Denis Hoornaert, Shahin Roozkhosh, Renato Mancuso, Marco Caccamo:
Work in Progress: Identifying Unexpected Inter-core Interference Induced by Shared Cache. RTAS 2021: 517-520 - 2020
- Jun Xiao, Andy D. Pimentel:
CITTA: Cache Interference-aware Task Partitioning for Real-time Multi-core Systems. LCTES 2020: 97-107 - Corey Tessler, Venkata P. Modekurthy, Nathan Fisher, Abusayeed Saifullah:
Bringing Inter-Thread Cache Benefits to Federated Scheduling. RTAS 2020: 281-295 - Corey Tessler, Venkata P. Modekurthy, Nathan Fisher, Abusayeed Saifullah:
Bringing Inter-Thread Cache Benefits to Federated Scheduling - Extended Results & Technical Report. CoRR abs/2002.12516 (2020) - 2019
- Jonathan Fish, Alfred Bognar:
Investigation of L2-Cache Interferences in a NXP QorIQ T4240 Multi-core Processor. ARCS 2019: 183-194 - 2017
- Xia Zhao, Yuxi Liu, Almutaz Adileh, Lieven Eeckhout:
LA-LLC: Inter-Core Locality-Aware Last-Level Cache to Exploit Many-to-Many Traffic in GPGPUs. IEEE Comput. Archit. Lett. 16(1): 42-45 (2017) - Corey Tessler, Gedare Bloom, Nathan Fisher:
Work-in-Progress: Reducing Cache Conflicts via Interrupts and BUNDLE Scheduling. RTAS 2017: 125-128 - 2016
- Dmitri Moltchanov, Alexander Antonov, Arkady Kluchev, Karolina Borunova, Pavel Kustarev, Vitaly Petrov, Yevgeni Koucheryavy, Alexey Platunov:
Statistical Traffic Properties and Model Inference for Shared Cache Interface in Multi-Core CPUs. IEEE Access 4: 4829-4839 (2016) - Kyungsu Kang, Sangho Park, Jong-Bae Lee, Luca Benini, Giovanni De Micheli:
A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache. DATE 2016: 1465-1468 - 2015
- Pascal Vivet, Christian Bernard, Eric Guthmuller, Ivan Miro Panades, Yvain Thonnart, Fabien Clermidy:
Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects. ISVLSI 2015: 615-620 - 2013
- Fazal Hameed, Lars Bauer, Jörg Henkel:
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache. CODES+ISSS 2013: 1:1-1:8 - 2011
- Jun Yan, Wei Zhang:
An Interference Matrix Based Approach to Bounding Worst-Case Inter-Thread Cache Interferences and WCET for Multi-Core Processors. J. Comput. Sci. Eng. 5(2): 131-140 (2011) - 2010
- Christoforos Kachris, George Nikiforos, Stamatis G. Kavadias, Vassilis Papaefstathiou, Manolis Katevenis:
Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface. ReConFig 2010: 328-333 - 2009
- Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang:
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. DAC 2009: 587-592 - Chenjie Yu, Xiangrong Zhou, Peter Petrov:
Low-power inter-core communication through cache partitioning in embedded multiprocessors. SBCCI 2009 - 1999
- Tony Givargis, Jörg Henkel, Frank Vahid:
Interface and cache power exploration for core-based embedded system design. ICCAD 1999: 270-273
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