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Publication search results
found 589 matches
- 2024
- Akash Kothari, Abdul Rafae Noor, Muchen Xu, Hassam Uddin, Dhruv Baronia, Stefanos Baziotis, Vikram S. Adve, Charith Mendis, Sudipta Sengupta:
Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware Architectures. ASPLOS (2) 2024: 514-529 - Stéphane Pouget, Louis-Noël Pouchet, Jason Cong:
Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. FPGA 2024: 184 - Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang:
Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis. FPGA 2024: 211-222 - Korbinian Staudacher, Ludwig Schmid, Johannes Zeiher, Robert Wille, Dieter Kranzlmüller:
Multi-controlled Phase Gate Synthesis with ZX-calculus applied to Neutral Atom Hardware. CoRR abs/2403.10864 (2024) - 2023
- Mathieu Leonel Mba:
Génération automatique de plate-forme matérielles distribuées pour des applications de traitement du signal. (Automatic synthesis of distributed hardware platforms for signal processing applications). University of Yaoundé I, Yaounde, Cameroon, 2023 - Kilryong Lee, Akira Yamawaki:
An investigation of software describing methods to design dual background scrolling hardware in high-level synthesis. Artif. Life Robotics 28(3): 547-552 (2023) - Mahendra Rathor, Aditya Anshul, K. Bharath, Rahul Chaurasia, Anirban Sengupta:
Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores. Comput. Electr. Eng. 105: 108476 (2023) - Aditya Anshul, Anirban Sengupta:
PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis. Expert Syst. Appl. 223: 119927 (2023) - Adib Hosseiny, Hadi Jahanirad:
Hardware acceleration of YOLOv7-tiny using high-level synthesis tools. J. Real Time Image Process. 20(4): 75 (2023) - Aditya Anshul, Anirban Sengupta:
Exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis. Microprocess. Microsystems 102: 104916 (2023) - Anirban Sengupta, Aditya Anshul, Rahul Chaurasia:
Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis. Microprocess. Microsystems 103: 104973 (2023) - Ashish Reddy Bommana, Susheel Ujwal Siddamshetty, Pudi Dhilleswararao, Arvind Thumatti K. R., Srinivas Boppu, M. Sabarimalai Manikandan, Linga Reddy Cenkeramaddi:
Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction. ACM Trans. Design Autom. Electr. Syst. 28(3): 32:1-32:35 (2023) - Alexander Kamkin, Mikhail M. Chupilko, Mikhail Lebedev, Sergey A. Smolov, Georgi Gaydadjiev:
High-Level Synthesis versus Hardware Construction. DATE 2023: 1-6 - Alexander El-Kady, Apostolos P. Fournaris, Vassilis Paliouras:
Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based High-Level Synthesis. ICCAD 2023: 1-7 - Ceyu Xu, Pragya Sharma, Tianshu Wang, Lisa Wu Wills:
Fast, Robust and Transferable Prediction for Hardware Logic Synthesis. MICRO 2023: 167-179 - Birte Caesar, Nico Jansen, Maximilian Weigand, Alexander Fay, Bernhard Rumpe:
Extracting Hardware Reconfiguration Models Based on Knowledge Synthesis from STEP Files. MoDELS (Companion) 2023: 434-443 - Haimanti Chakraborty, Ranga Vemuri:
Split Manufacturing Based Secure Hardware Design by BEOL Signal Selection In High Level Synthesis. MWSCAS 2023: 1083-1087 - Md Rafid Muttaki, Zahin Ibnat, Shang Shi, Hadi Mardani Kamali, Farimah Farahmandi:
Security of Hardware Generators: Enabling Assurance in High-Level Synthesis. MWSCAS 2023: 816-820 - William L. Harrison, Ian Blumenfeld, Eric Bond, Chris Hathhorn, Paul Li, May Torrence, Jared Ziegler:
Formalized High Level Synthesis with Applications to Cryptographic Hardware. NFM 2023: 332-352 - International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2023, Hamburg, Germany, September 17-22, 2023. IEEE 2023, ISBN 979-8-4007-0289-1 [contents]
- Stefan Bosse:
Rule-based High-level Hardware-RTL Synthesis of Algorithms, Virtualizing Machines, and Communication Protocols with FPGAs based on Concurrent Communicating Sequential Processes and the ConPro Synthesis Framework. CoRR abs/2302.02959 (2023) - James Timothy Meech:
Leveraging High-Level Synthesis and Large Language Models to Generate, Simulate, and Deploy a Uniform Random Number Generator Hardware Design. CoRR abs/2311.03489 (2023) - 2022
- Romina Soledad Molina, Veronica Gil-Costa, Maria Liz Crespo, Giovanni Ramponi:
High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks. IEEE Access 10: 90429-90455 (2022) - Kohei Shinyamada, Akira Yamawaki:
Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction. Artif. Life Robotics 27(3): 541-546 (2022) - Atsushi Shojima, Akira Yamawaki:
Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration. Artif. Life Robotics 27(3): 554-560 (2022) - Chong Yeam Tan, Chia Yee Ooi, Hau Sim Choo, Nordinah Ismail:
Efficient hardware-accelerated pseudoinverse computation through algorithm restructuring for parallelization in high-level synthesis. Int. J. Circuit Theory Appl. 50(2): 394-416 (2022) - Abdulhadi Mohammad din Dawrayn, Muhammad Bilal:
SVM-Based Switching Filter Hardware Design for Mixed Noise Reduction in Digital Images Using High-Level Synthesis Tools. Int. J. Comput. Vis. Image Process. 12(1): 1-16 (2022) - Patrick Sittel, Nicolai Fiege, John Wickerson, Peter Zipf:
Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 614-627 (2022) - Shihao Song, Harry Chong, Adarsha Balaji, Anup Das, James A. Shackleford, Nagarajan Kandasamy:
DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware. ACM Trans. Embed. Comput. Syst. 21(3): 27:1-27:35 (2022) - Serena Curzel, Nicolas Bohm Agostini, Antonino Tumeo, Fabrizio Ferrandi:
Hardware acceleration of complex machine learning models through modern high-level synthesis. CF 2022: 209-210
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