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Publication search results
found 9 matches
- 2005
- Yu Imai, Kiyotaka Yamamura, Yasuaki Inoue:
An Efficient Homotopy Method for Finding DC Operating Points of Nonlinear Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(10): 2554-2561 (2005) - Yasuaki Inoue, Yu Imai, Kiyotaka Yamamura:
A Homotopy Method Using a Nonlinear Auxiliary Function for Solving Transistor Circuits. IEICE Trans. Inf. Syst. 88-D(7): 1401-1408 (2005) - Yu Imai, Kiyotaka Yamamura, Yasuaki Inoue:
An efficient homotopy method for finding DC operating points of nonlinear circuits. ISCAS (5) 2005: 4911-4914 - Kiyotaka Imai, Yasushi Yamagata, Sadaaki Masuoka, Naohiko Kimuzuka, Yuri Yasuda, Mitsuhiro Togo, Masahiro Ikeda, Yasutaka Nakashiba:
Device technology for body biasing scheme. ISCAS (1) 2005: 13-16 - 2004
- Hideyuki Imai, Daigo Izawa, Kiyotaka Yoshida, Yoshiharu Sato:
On Detecting Interactions in Hayashi's Second Method of Quantification. MDAI 2004: 205-214 - 2001
- Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina:
A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. CICC 2001: 213-216 - 1998
- Yuhua Cheng, Kai Chen, Kiyotaka Imai, Chenming Hu:
A unified MOSFET channel charge model for device modeling in circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 641-644 (1998) - 1996
- Hitoshi Okamura, Takao Atsumo, Koichi Takeda, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Tom Yamazaki:
A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump. IEEE J. Solid State Circuits 31(1): 84-90 (1996) - 1995
- Hitoshi Okamura, Hideo Toyoshima, Koichi Takeda, Takashi Oguri, Satoshi Nakamura, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Hiroshi Yoshida, Tom Yamazaki:
A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors. IEEE J. Solid State Circuits 30(11): 1196-1202 (1995)
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