Tsutomu Yoshinaga (Selection)

List of publications from the DBLP Bibliography Server - FAQ

Ask others: ACM DL/Guide -

28 Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. IEEE Trans. Computers 60(6): 783-799 (2011)

26 Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga: An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. IJNC 1(2): 244-259 (2011)

25 Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga: An Efficient Path Setup for a Photonic Network-on-Chip. ICNC 2010: 156-161

22 Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction router: Yet another low latency on-chip router architecture. HPCA 2009: 367-378

Selection of 4 from 32 records - Tsutomu Yoshinaga has 46 coauthors

Last update 2012-09-10 CET by the DBLP Team —

Content released under the ODC-BY 1.0 license — See also our legal information page

28		Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. IEEE Trans. Computers 60(6): 783-799 (2011)
26		Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga: An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. IJNC 1(2): 244-259 (2011)
25		Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga: An Efficient Path Setup for a Photonic Network-on-Chip. ICNC 2010: 156-161
22		Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction router: Yet another low latency on-chip router architecture. HPCA 2009: 367-378