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| 140 |       | Jun Yan, Wei Zhang: Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches. JCSE 5(1): 1-18 (2011) |
| 139 | | Jun Yan, Wei Zhang: Computing and Reducing Transient Error Propagation in Registers. JCSE 5(2): 121-130 (2011) |
| 138 | | Jun Yan, Wei Zhang: An Interference Matrix Based Approach to Bounding Worst-Case Inter-Thread Cache Interferences and WCET for Multi-Core Processors. JCSE 5(2): 131-140 (2011) |
| 127 | | Jun Yan, Wei Zhang: Time-Predictable L2 Cache Design for High-Performance Real-Time Systems. RTCSA 2010: 357-366 |
| 117 | | Jun Yan, Wei Zhang: Design and implementation of hybrid multicore simulators. IJES 4(3/4): 270-275 (2010) |
| 98 | | Wei Zhang, Jun Yan: Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches. RTCSA 2009: 455-463 |
| 78 | | Yiqiang Ding, Jun Yan, Wei Zhang: Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications. JCSE 3(1): 59-71 (2009) |
| 70 | | Jun Yan, Wei Zhang: WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches. IEEE Real-Time and Embedded Technology and Applications Symposium 2008: 80-89 |
| 64 | | Jun Yan, Wei Zhang: Analyzing the worst-case execution time for instruction caches with prefetching. ACM Trans. Embedded Comput. Syst. 8(1): (2008) |
| 58 | | Jun Yan, Wei Zhang: A time-predictable VLIW processor and its compiler support. Real-Time Systems 38(1): 67-84 (2008) |
| 57 | | Jun Yan, Wei Zhang: Exploiting virtual registers to reduce pressure on real registers. TACO 4(4): (2008) |
| 54 | | Jun Yan, Wei Zhang: Virtual Registers: Reducing Register Pressure Without Enlarging the Register File. HiPEAC 2007: 57-70 |
| 50 | | Jun Yan, Wei Zhang: WCET analysis of instruction caches with prefetching. LCTES 2007: 175-184 |
| 43 | | Jun Yan, Wei Zhang: Hybrid multi-core architecture for boosting single-threaded performance. SIGARCH Computer Architecture News 35(1): 141-148 (2007) |
| 42 | | Jun Yan, Wei Zhang: Evaluating instruction cache vulnerability to transient errors. SIGARCH Computer Architecture News 35(4): 21-28 (2007) |
| 17 | | Jun Yan, Wei Zhang: Compiler-guided register reliability improvement against soft errors. EMSOFT 2005: 203-209 |
Selection of 16 from 164 records - Jun Yan has 206 coauthors
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