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| 40 |       | Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud: Embedded tutorial: essential issues for IP reuse. ASP-DAC 2000: 37-42 |
| 10 | | Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski: A transformation-based method for loop folding. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 439-450 (1994) |
| 8 | | Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin: An effective methodology for functional pipelining. ICCAD 1992: 230-233 |
| 7 | | Allen C.-H. Wu, Tedd Hadley, Daniel Gajski: An efficient multi-view design model for real-time interactive synthesis. ICCAD 1992: 328-331 |
| 6 | | Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul: Accurate layout area and delay modeling for system level design. ICCAD 1992: 355-361 |
| 5 | | Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu: Layout placement for sliced architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 102-114 (1992) |
| 4 | | Allen C.-H. Wu, Daniel D. Gajski: Partitioning algorithms for layout synthesis from register-transfer netlists. IEEE Trans. on CAD of Integrated Circuits and Systems 11(4): 453-463 (1992) |
| 3 |  | Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski: Layout-Area Models for High-Level Synthesis. ICCAD 1991: 34-37 |
| 2 | | Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski: A new algorithm for transistor sizing in CMOS circuits. EURO-DAC 1990: 589-593 |
| 1 | | Allen C.-H. Wu, Daniel Gajski: Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. ICCAD 1990: 144-147 |
Selection of 10 from 52 records - Allen C.-H. Wu has 46 coauthors
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