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Yih Wang (Selection)

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6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLEric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr: A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. ISSCC 2012: 230-232
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLFatih Hamzaoglu, Yih Wang, Pramod Kolar, Liqiong Wei, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang: Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design. IEEE Design & Test of Computers 28(1): 22-31 (2011)
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPramod Kolar, Eric Karl, Uddalak Bhattacharya, Fatih Hamzaoglu, Henry Nho, Yong-Gee Ng, Yih Wang, Kevin Zhang: A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation. J. Solid-State Circuits 46(1): 76-84 (2011)
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHyunwoo Nho, Pramod Kolar, Fatih Hamzaoglu, Yih Wang, Eric Karl, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang: A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation. ISSCC 2010: 346-347
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr: A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. J. Solid-State Circuits 45(1): 103-110 (2010)
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr: A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management. ISSCC 2009: 456-457

Selection of 6 from 6 records - Yih Wang has 13 coauthors

Last update 2012-09-10 CET by the DBLP TeamThis material is Open Data Content released under the ODC-BY 1.0 license — See also our legal information page