Jinxiang Wang (Selection)

List of publications from the DBLP Bibliography Server - FAQ

Ask others: ACM DL/Guide -

6 Qingli Zhang, Jinxiang Wang, Yizheng Ye: Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters. VLSI Design 2008: 377-382

4 Qingli Zhang, Jinxiang Wang, Yizheng Ye: An energy-efficient temporal encoding circuit technique for on-chip high performance buses. ACM Great Lakes Symposium on VLSI 2006: 422-427

3 Qingli Zhang, Jinxiang Wang, Yizheng Ye: Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses. APCCAS 2006: 1611-1614

2 Yong-sheng Wang, Jinxiang Wang, Feng-chang Lai, Yizheng Ye: Optimal Schemes for ADC BIST Based on Histogram. Asian Test Symposium 2005: 52-57

1 Yong-sheng Wang, Liyi Xiao, Mingyan Yu, Jinxiang Wang, Yizheng Ye: A Test Architecture for System-on-a-Chip. Asian Test Symposium 2003: 506

Selection of 5 from 7 records - Jinxiang Wang has 10 coauthors

6		Qingli Zhang, Jinxiang Wang, Yizheng Ye: Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters. VLSI Design 2008: 377-382
4		Qingli Zhang, Jinxiang Wang, Yizheng Ye: An energy-efficient temporal encoding circuit technique for on-chip high performance buses. ACM Great Lakes Symposium on VLSI 2006: 422-427
3		Qingli Zhang, Jinxiang Wang, Yizheng Ye: Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses. APCCAS 2006: 1611-1614
2		Yong-sheng Wang, Jinxiang Wang, Feng-chang Lai, Yizheng Ye: Optimal Schemes for ADC BIST Based on Histogram. Asian Test Symposium 2005: 52-57
1		Yong-sheng Wang, Liyi Xiao, Mingyan Yu, Jinxiang Wang, Yizheng Ye: A Test Architecture for System-on-a-Chip. Asian Test Symposium 2003: 506