Narayanan Vijaykrishnan (Selection)

Vijaykrishnan Narayanan

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175 Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada: Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED 2006: 775-780

152 Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan: A power estimation methodology for systemC transaction level models. CODES+ISSS 2005: 142-147

Selection of 2 from 297 records - Narayanan Vijaykrishnan has 235 coauthors

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175		Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada: Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED 2006: 775-780
152		Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan: A power estimation methodology for systemC transaction level models. CODES+ISSS 2005: 142-147