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Sreehari Veeramachaneni (Selection)

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16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design 2012: 280-285
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A Unified Architecture for BCD and Binary Adder/Subtractor. DSD 2011: 426-429
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A Prefix Based Reconfigurable Adder. ISVLSI 2011: 349-350
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A low power, variable resolution two-step flash ADC. ACM Great Lakes Symposium on VLSI 2010: 39-44
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A Novel, Variable Resolution Flash ADC with Sub Flash Architecture. ISVLSI 2010: 434-435
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas: An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. VLSI Design 2010: 411-416
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, M. B. Srinivas: An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. J. Low Power Electronics 6(3): 429-435 (2010)
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnshul Singh, Aman Gupta, Sreehari Veeramachaneni, M. B. Srinivas: A High Performance Unified BCD and Binary Adder/Subtractor. ISVLSI 2009: 211-216
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas: A novel low power, variable resolution pipelined ADC. SoCC 2009: 183-186
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas: Design of a Low Power, Variable-Resolution Flash ADC. VLSI Design 2009: 117-122
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas: A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter. J. Low Power Electronics 5(3): 279-290 (2009)
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas: A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. VLSI Design 2008: 547-552
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas: Novel architectures for efficient (m, n) parallel counters. ACM Great Lakes Symposium on VLSI 2007: 188-191
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas: Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. ISCAS 2007: 3271-3274
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas: Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. ISVLSI 2007: 343-350
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas: Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. VLSI Design 2007: 324-329

Selection of 16 from 16 records - Sreehari Veeramachaneni has 21 coauthors

Last update 2012-09-10 CET by the DBLP TeamThis material is Open Data Content released under the ODC-BY 1.0 license — See also our legal information page