Alejandro Valero (Selection)

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3 Alejandro Valero, Julio Sahuquillo, Vicente Lorente, Salvador Petit, Pedro López, José Duato: Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. IEEE Trans. VLSI Syst. 20(6): 1108-1117 (2012)

2 Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato: Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour. PACT 2011: 214

1 Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato: An hybrid eDRAM/SRAM macrocell to implement first-level data caches. MICRO 2009: 213-221

Selection of 3 from 3 records - Alejandro Valero has 6 coauthors

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3		Alejandro Valero, Julio Sahuquillo, Vicente Lorente, Salvador Petit, Pedro López, José Duato: Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. IEEE Trans. VLSI Syst. 20(6): 1108-1117 (2012)
2		Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato: Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour. PACT 2011: 214
1		Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato: An hybrid eDRAM/SRAM macrocell to implement first-level data caches. MICRO 2009: 213-221