Kyoko Ueda (Selection)

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2 Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. VLSI-SoC 2006: 290-295

1 Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Architecture-Level Performance Estimation for IP-Based Embedded Systems. DATE 2004: 1002-1007

Selection of 2 from 3 records - Kyoko Ueda has 10 coauthors

2		Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. VLSI-SoC 2006: 290-295
1		Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai: Architecture-Level Performance Estimation for IP-Based Embedded Systems. DATE 2004: 1002-1007