Trieu-Kien Truong (Selection)

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16 Trieu-Kien Truong, Irving S. Reed, In-Shek Hsu, Hsuen-Chyun Shyu, Howard M. Shao: A Pipeline Design of a Fast Prime Factor DFT on a Finite Field. IEEE Trans. Computers 37(3): 266-273 (1988)

11 Irving S. Reed, Trieu-Kien Truong, J. J. Chang, Howard M. Shao, In-Shek Hsu: VLSI residue multiplier modulo a Fermat number. IEEE Symposium on Computer Arithmetic 1985: 203-206

10 Howard M. Shao, Trieu-Kien Truong, Leslie J. Deutsch, Joseph H. Yuen, Irving S. Reed: A VLSI Design of a Pipeline Reed-Solomon Decoder. IEEE Trans. Computers 34(5): 393-403 (1985)

9 Charles C. Wang, Trieu-Kien Truong, Howard M. Shao, Leslie J. Deutsch, Jim K. Omura, Irving S. Reed: VLSI Architectures for Computing Multiplications and Inverses in GF(2^m). IEEE Trans. Computers 34(8): 709-717 (1985)

5 Trieu-Kien Truong, Irving S. Reed, C.-S. Yeh, Howard M. Shao: A Parallel Architecture for Digital Filtering Using Fermat Number Transforms. IEEE Trans. Computers 32(9): 874-877 (1983)

Selection of 5 from 76 records - Trieu-Kien Truong has 64 coauthors

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16		Trieu-Kien Truong, Irving S. Reed, In-Shek Hsu, Hsuen-Chyun Shyu, Howard M. Shao: A Pipeline Design of a Fast Prime Factor DFT on a Finite Field. IEEE Trans. Computers 37(3): 266-273 (1988)
11		Irving S. Reed, Trieu-Kien Truong, J. J. Chang, Howard M. Shao, In-Shek Hsu: VLSI residue multiplier modulo a Fermat number. IEEE Symposium on Computer Arithmetic 1985: 203-206
10		Howard M. Shao, Trieu-Kien Truong, Leslie J. Deutsch, Joseph H. Yuen, Irving S. Reed: A VLSI Design of a Pipeline Reed-Solomon Decoder. IEEE Trans. Computers 34(5): 393-403 (1985)
9		Charles C. Wang, Trieu-Kien Truong, Howard M. Shao, Leslie J. Deutsch, Jim K. Omura, Irving S. Reed: VLSI Architectures for Computing Multiplications and Inverses in GF(2^m). IEEE Trans. Computers 34(8): 709-717 (1985)
5		Trieu-Kien Truong, Irving S. Reed, C.-S. Yeh, Howard M. Shao: A Parallel Architecture for Digital Filtering Using Fermat Number Transforms. IEEE Trans. Computers 32(9): 874-877 (1983)