Hiroaki Shikano (Selection)

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5 Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara: Software-cooperative power-efficient heterogeneous multi-core for media processing. ASP-DAC 2008: 736-741

4 Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara: Power-Aware Compiler Controllable Chip Multiprocessor. IEICE Transactions 91-C(4): 432-439 (2008)

2 Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara: Power-Aware Compiler Controllable Chip Multiprocessor. PACT 2007: 427

1 Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara: Compiler Control Power Saving Scheme for Multi Core Processors. LCPC 2005: 362-376

Selection of 4 from 5 records - Hiroaki Shikano has 14 coauthors

5		Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara: Software-cooperative power-efficient heterogeneous multi-core for media processing. ASP-DAC 2008: 736-741
4		Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara: Power-Aware Compiler Controllable Chip Multiprocessor. IEICE Transactions 91-C(4): 432-439 (2008)
2		Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara: Power-Aware Compiler Controllable Chip Multiprocessor. PACT 2007: 427
1		Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara: Compiler Control Power Saving Scheme for Multi Core Processors. LCPC 2005: 362-376