dblp.uni-trier.dewww.dagstuhl.dewww.uni-trier.de

Toshiyuki Shibuya (Selection)

List of publications from the DBLP Bibliography Server - FAQ
Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo


9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng: Efficient Power Network Analysis Considering Multidomain Clock Gating. IEEE Trans. on CAD of Integrated Circuits and Systems 28(9): 1348-1358 (2009)
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng: Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. DATE 2008: 537-540
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng: Fast power network analysis with multiple clock domains. ICCD 2007: 456-463

Selection of 3 from 15 records - Toshiyuki Shibuya has 56 coauthors

Last update 2012-09-10 CET by the DBLP TeamThis material is Open Data Content released under the ODC-BY 1.0 license — See also our legal information page