Jan Schier (Selection)

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6 Premysl Sucha, Zdenek Hanzálek, Antonin Hermanek, Jan Schier: Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design - Implementation of Finite Interval Constant Modulus Algorithm. VLSI Signal Processing 46(1): 35-53 (2007)

3 Jan Schier, Antonin Hermanek: Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA. FPL 2004: 1149-1151

1 Zdenek Pohl, Jan Schier, Miroslav Lícko, Antonin Hermanek, Milan Tichý, Rudolf Matousek, Jiri Kadlec: Logarithmic Arithmetic for Real Data Types and Support for Matlab/Simulink Based Rapid-FPGA-Prototyping. IPDPS 2003: 190

Selection of 3 from 6 records - Jan Schier has 10 coauthors

6		Premysl Sucha, Zdenek Hanzálek, Antonin Hermanek, Jan Schier: Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design - Implementation of Finite Interval Constant Modulus Algorithm. VLSI Signal Processing 46(1): 35-53 (2007)
3		Jan Schier, Antonin Hermanek: Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA. FPL 2004: 1149-1151
1		Zdenek Pohl, Jan Schier, Miroslav Lícko, Antonin Hermanek, Milan Tichý, Rudolf Matousek, Jiri Kadlec: Logarithmic Arithmetic for Real Data Types and Support for Matlab/Simulink Based Rapid-FPGA-Prototyping. IPDPS 2003: 190