Mamoru Sasaki (Selection)

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9 Atsushi Iwata, Takeshi Yoshida, Mamoru Sasaki: Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices. IEICE Transactions 90-C(6): 1149-1155 (2007)

8 Takeshi Yoshida, Yoshihiro Masui, Takayuki Mashimo, Mamoru Sasaki, Atsushi Iwata: A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique. IEICE Transactions 89-C(6): 769-774 (2006)

7 Takeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata: A 1V supply successive approximation ADC with rail-to-rail input voltage range. ISCAS (1) 2005: 192-195

6 Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata: A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique. IEICE Transactions 88-C(6): 1233-1240 (2005)

Selection of 4 from 9 records - Mamoru Sasaki has 15 coauthors

9		Atsushi Iwata, Takeshi Yoshida, Mamoru Sasaki: Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices. IEICE Transactions 90-C(6): 1149-1155 (2007)
8		Takeshi Yoshida, Yoshihiro Masui, Takayuki Mashimo, Mamoru Sasaki, Atsushi Iwata: A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique. IEICE Transactions 89-C(6): 769-774 (2006)
7		Takeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata: A 1V supply successive approximation ADC with rail-to-rail input voltage range. ISCAS (1) 2005: 192-195
6		Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata: A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique. IEICE Transactions 88-C(6): 1233-1240 (2005)