Kaushik Roy (Selection)

Purdue University

other persons with the same name:

• Kaushik Roy - Institute for Information Systems Engineering, Concordia University

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446		Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy: Cognitive computing with spin-based neural networks. DAC 2012: 1262-1263
445		Sang Phill Park, Sumeet Kumar Gupta, Niladri Narayan Mojumder, Anand Raghunathan, Kaushik Roy: Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture. DAC 2012: 492-497
444		Swagath Venkataramani, Amit Sabne, Vivek J. Kozhikkottu, Kaushik Roy, Anand Raghunathan: SALSA: systematic logic synthesis of approximate circuits. DAC 2012: 796-801
443		Georgios Panagopoulos, Charles Augustine, Kaushik Roy: A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach. DATE 2012: 1443-1446
442		Sumeet Kumar Gupta, Sang Phill Park, Niladri Narayan Mojumder, Kaushik Roy: Layout-aware optimization of stt mrams. DATE 2012: 1455-1458
441		Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan: Functional analysis of circuits under timing variations. European Test Symposium 2012: 1
440		Kaushik Roy, Mohamed S. Kamel: Multibiometric System Using Level Set Method and Particle Swarm Optimization. ICIAR (2) 2012: 20-29
439		Elif S. Mungan, Chao Lu, Vijay Raghunathan, Kaushik Roy: Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems. ISLPED 2012: 123-128
438		Kaushik Roy: Spin as state variable for computation: prospects and perspectives. ISLPED 2012: 147-148
437		Rangharajan Venkatesan, Vivek J. Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan: TapeCache: a high density, energy efficient cache based on domain wall memory. ISLPED 2012: 185-190
436		Himanshu Markandeya, Shriram Raghunathan, Pedro Irazoqui, Kaushik Roy: A low-power "near-threshold" epileptic seizure detection processor with multiple algorithm programmability. ISLPED 2012: 285-290
435		Yusung Kim, Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos, Kaushik Roy: Write-optimized reliable design of STT MRAM. ISLPED 2012: 3-8
434		Dongsoo Lee, Sumeet Kumar Gupta, Kaushik Roy: High-performance low-energy STT MRAM based on balanced write scheme. ISLPED 2012: 9-14
433		Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy: Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems. VLSI Design 2012: 215-220
432		Mayur Bubna, Kaushik Roy, Ashish Goel: HBIST: An approach towards zero external test cost. VTS 2012: 13-18
431		Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy: Proposal For Neuromorphic Hardware Using Spin Devices CoRR abs/1206.3227: (2012)
430		Sang Phill Park, Dongsoo Lee, Kaushik Roy: Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code. IEEE Trans. VLSI Syst. 20(2): 248-256 (2012)
429		Jaydeep P. Kulkarni, Kaushik Roy: Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design. IEEE Trans. VLSI Syst. 20(2): 319-332 (2012)
428		W. Paul Griffin, Anand Raghunathan, Kaushik Roy: CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations. IEEE Trans. VLSI Syst. 20(5): 791-803 (2012)
427		Dongsoo Lee, Kaushik Roy: Viterbi-Based Efficient Test Data Compression. IEEE Trans. on CAD of Integrated Circuits and Systems 31(4): 610-619 (2012)
426		Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy: Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems. Signal Processing Systems 68(3): 415-431 (2012)
425		Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaushik Roy: Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays. ASP-DAC 2011: 695-700
424		Ashish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst, Kaushik Roy: Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost. Asian Test Symposium 2011: 486-491
423		Georgios Karakonstantis, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Tziantzioulis, Vaibhav Gupta, Kaushik Roy: Significance driven computation on next-generation unreliable platforms. DAC 2011: 290-291
422		Vinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar: Dynamic effort scaling: managing the quality-efficiency tradeoff. DAC 2011: 603-608
421		Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy: Stage number optimization for switched capacitor power converters in micro-scale energy harvesting. DATE 2011: 770-775
420		Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, Kaushik Roy: Design of voltage-scalable meta-functions for approximate computing. DATE 2011: 950-955
419		Georgios Karakonstantis, Kaushik Roy: Voltage over-scaling: A cross-layer design perspective for energy efficient systems. ECCTD 2011: 548-551
418		Dongsoo Lee, Kaushik Roy: Viterbi-Based Efficient Test Data Compression. European Test Symposium 2011: 204
417		Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan: MACACO: Modeling and analysis of circuits for approximate computing. ICCAD 2011: 667-673
416		Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Dag T. Wisland, Hamid Mahmoodi, Jens Kargaard Madsen, Kaushik Roy: Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology. ICCD 2011: 326-331
415		Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy: Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors. ISLPED 2011: 303-308
414		Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy: IMPACT: imprecise adders for low-power approximate computing. ISLPED 2011: 409-414
413		Soo Youn Kim, Selin Baytok, Kaushik Roy: Scaled LTPS TFTs for low-cost low-power applications. ISQED 2011: 745-750
412		Dongsoo Lee, Sang Phill Park, Ashish Goel, Kaushik Roy: Memory-based embedded digital ATE. VTS 2011: 266-271
411		Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy: A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications. IEEE Trans. Circuits Syst. Video Techn. 21(2): 101-112 (2011)
410		Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy: Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V. IEEE Trans. VLSI Syst. 19(8): 1429-1437 (2011)
409		Swaroop Ghosh, Kaushik Roy: Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking. IEEE Trans. VLSI Syst. 19(8): 1504-1507 (2011)
408		Jaydeep P. Kulkarni, Ashish Goel, Patrick Ndai, Kaushik Roy: A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array. IEEE Trans. VLSI Syst. 19(9): 1727-1730 (2011)
407		Jung Hwan Choi, Byung Guk Kim, Aurobindo Dasgupta, Kaushik Roy: Improved clock-gating control scheme for transparent pipeline. ASP-DAC 2010: 401-406
406		Chao Lu, Vijay Raghunathan, Kaushik Roy: Micro-scale energy harvesting: a system design perspective. ASP-DAC 2010: 89-94
405		Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy: Data-dependant sense-amplifier flip-flop for low power applications. CICC 2010: 1-4
404		Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar: Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. DAC 2010: 555-560
403		Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy: Efficient power conversion for ultra low voltage micro scale energy transducers. DATE 2010: 1602-1607
402		Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras: Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis. European Test Symposium 2010: 69-74
401		Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia: Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach. HOST 2010: 13-18
400		Vaibhav Gupta, Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy: VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture. ICCD 2010: 260-265
399		Kaushik Roy, Alireza Alaei, Umapada Pal: Word-Wise Handwritten Persian and Roman Script Identification. ICFHR 2010: 628-633
398		Georgios Karakonstantis, Charles Augustine, Kaushik Roy: A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique. IOLTS 2010: 3-8
397		Chao Lu, Vijay Raghunathan, Kaushik Roy: Maximum power point considerations in micro-scale solar energy harvesting systems. ISCAS 2010: 273-276
396		Georgios Karakonstantis, Georgios Panagopoulos, Kaushik Roy: HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs. ISLPED 2010: 117-122
395		Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy: Analysis and design of ultra low power thermoelectric energy harvesting systems. ISLPED 2010: 183-188
394		Himanshu Markandeya, Georgios Karakonstantis, Shriram Raghunathan, Pedro Irazoqui, Kaushik Roy: Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection. ISLPED 2010: 301-306
393		Mesut Meterelliyoz, Ashish Goel, Jaydeep P. Kulkarni, Kaushik Roy: Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit. ISSCC 2010: 186-187
392		Kaushik Roy, Byunghoo Jung, Anand Raghunathan: Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. VLSI Design 2010: 464-469
391		Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths. IEEE Trans. VLSI Syst. 18(1): 53-65 (2010)
390		Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy: Self-Repairing SRAM Using On-Chip Detection and Compensation. IEEE Trans. VLSI Syst. 18(1): 75-84 (2010)
389		Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy: Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing. IEEE Trans. VLSI Syst. 18(10): 1461-1470 (2010)
388		Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy: Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Trans. VLSI Syst. 18(11): 1621-1624 (2010)
387		Jing Li, Patrick Ndai, Ashish Goel, Sayeef S. Salahuddin, Kaushik Roy: Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective. IEEE Trans. VLSI Syst. 18(12): 1710-1723 (2010)
386		Kunhyuk Kang, Sang Phill Park, Keejong Kim, Kaushik Roy: On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures. IEEE Trans. VLSI Syst. 18(2): 270-280 (2010)
385		Myeong-Eun Hwang, Kaushik Roy: ABRM: Adaptive Beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling. IEEE Trans. VLSI Syst. 18(2): 281-290 (2010)
384		Jongsun Park, Jung Hwan Choi, Kaushik Roy: Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy. IEEE Trans. VLSI Syst. 18(5): 787-793 (2010)
383		Patrick Ndai, Ashish Goel, Kaushik Roy: A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors. IEEE Trans. VLSI Syst. 18(8): 1209-1219 (2010)
382		Swaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy: Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking. IEEE Trans. VLSI Syst. 18(9): 1301-1309 (2010)
381		Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy: Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 29(1): 2-13 (2010)
380		Seung Hoon Choi, Kunhyuk Kang, Florentin Dartu, Kaushik Roy: Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 497-502 (2010)
379		Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy: Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor. IEEE Trans. on Circuits and Systems 57-I(8): 1838-1847 (2010)
378		Ik Joon Chang, Sang Phill Park, Kaushik Roy: Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation. J. Solid-State Circuits 45(2): 401-410 (2010)
377		Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy: Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering. Signal Processing Systems 58(2): 125-137 (2010)
376		Mesut Meterelliyoz, Kaushik Roy: Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations. ASP-DAC 2009: 787-792
375		Jing Li, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy: An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective. ASP-DAC 2009: 841-846
374		Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy: A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems. ASP-DAC 2009: 847-852
373		Ashish Goel, Patrick Ndai, Jaydeep P. Kulkarni, Kaushik Roy: REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN. CICC 2009: 503-506
372		Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy: A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors. DAC 2009: 670-675
371		Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta: Device/circuit interactions at 22nm technology node. DAC 2009: 97-102
370		Umapada Pal, Rami Kumar Roy, Kaushik Roy, Fumitaka Kimura: Indian Multi-Script Full Pin-code String Recognition for Postal Automation. ICDAR 2009: 456-460
369		Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy: Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator. ISLPED 2009: 195-200
368		Kaushik Roy: Ultra low voltage CMOS. ISLPED 2009: 425-426
367		Bhanu Kapoor, Shankar Hemmady, Shireesh Verma, Kaushik Roy, Manuel A. d'Abreu: Impact of SoC power management techniques on verification and testing. ISQED 2009: 692-695
366		Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy: PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. ISQED 2009: 80-85
365		Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy: System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning. SiPS 2009: 133-138
364		Kaushik Roy: Design in the nano-scale Era: Low-power, reliability, and error resiliency. SoCC 2009: 445
363		Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy: Coping with Variations through System-Level Design. VLSI Design 2009: 581-586
362		Sang Phill Park, Kunhyuk Kang, Kaushik Roy: Reliability Implications of Bias-Temperature Instability in Digital ICs. IEEE Design & Test of Computers 26(6): 8-17 (2009)
361		Hamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy: Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating. IEEE Trans. VLSI Syst. 17(1): 33-44 (2009)
360		Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh: Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. IEEE Trans. VLSI Syst. 17(12): 1749-1752 (2009)
359		Jing Li, Kunhyuk Kang, Kaushik Roy: Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 46-59 (2009)
358		Jung Hwan Choi, Nilanjan Banerjee, Kaushik Roy: Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 87-97 (2009)
357		Nilanjan Banerjee, Georgios Karakonstantis, Jung Hwan Choi, Chaitali Chakrabarti, Kaushik Roy: Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering. IEEE Trans. on CAD of Integrated Circuits and Systems 28(8): 1127-1137 (2009)
356		Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy: Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation. IEEE Trans. on Circuits and Systems 56-I(7): 1428-1441 (2009)
355		Umapada Pal, Kaushik Roy, Fumitaka Kimura: A Lexicon-Driven Handwritten City-Name Recognition Scheme for Indian Postal Automation. IEICE Transactions 92-D(5): 1146-1158 (2009)
354		Swaroop Ghosh, Kaushik Roy: Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching. ASP-DAC 2008: 635-640
353		Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy: NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution? ASP-DAC 2008: 726-731
352		Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy: Process variation tolerant SRAM array for ultra low voltage applications. DAC 2008: 108-113
351		Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy: Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. DAC 2008: 278-283
350		Swaroop Ghosh, Patrick Ndai, Kaushik Roy: A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking. DATE 2008: 366-371
349		Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen: Power-Aware Testing and Test Strategies for Low Power Devices. DATE 2008
348		Dimitris Gizopoulos, Kaushik Roy, Subhasish Mitra, Pia Sanda: Soft Errors: System Effects, Protection Techniques and Case Studies. DATE 2008
347		Nilanjan Banerjee, Charles Augustine, Kaushik Roy: Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems. DFT 2008: 323-331
346		Kaushik Roy, Kinshuk Majumder: Trilingual Script Separation of Handwritten Postal Document. ICVGIP 2008: 693-700
345		Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy: Thermal analysis of 8-T SRAM for nano-scaled technologies. ISLPED 2008: 123-128
344		Swarup Bhunia, Kaushik Roy: Low power design under parameter variations. ISLPED 2008: 137-138
343		Swaroop Ghosh, Jung Hwan Choi, Patrick Ndai, Kaushik Roy: O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors. ISLPED 2008: 189-192
342		Bhanu Kapoor, J. Marc Edwards, Shankar Hemmady, Shireesh Verma, Kaushik Roy: Tutorial: SoC Power Management Verification and Testing Issues. MTV 2008: 67-72
341		Swarup Bhunia, Kaushik Roy: Low power design under parameter variations. SoCC 2008: 389-390
340		Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy: Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design 2008: 125-130
339		Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy: Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. VTS 2008: 101-106
338		Patrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy: Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput. IEEE Trans. Computers 57(7): 940-951 (2008)
337		Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy: Profit Aware Circuit Design Under Process Variations Considering Speed Binning. IEEE Trans. VLSI Syst. 16(7): 806-815 (2008)
336		Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy: Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 174-183 (2008)
335		Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy: Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J. Electronic Testing 24(6): 577-590 (2008)
334		Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy: An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs. JETC 4(3): (2008)
333		Jongsun Park, Kaushik Roy: A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption. Signal Processing Systems 53(3): 399-410 (2008)
332		Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy: High Performance and Low Power Electronics on Flexible Substrate. DAC 2007: 274-275
331		Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy: Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement. DAC 2007: 358-363
330		Kunhyuk Kang, Keejong Kim, Kaushik Roy: Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop. DAC 2007: 934-939
329		Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. DATE 2007: 1532-1537
328		Myeong-Eun Hwang, Tamer Cakici, Kaushik Roy: Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling. DATE 2007: 1550-1555
327		Nilanjan Banerjee, Georgios Karakonstantis, Kaushik Roy: Process variation tolerant low power DCT architecture. DATE 2007: 630-635
326		Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy: Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance. DDECS 2007: 69-74
325		Kaushik Roy, Claire Tomlin: A New Hybrid State Estimator for Systems with Limited Mode Changes. HSCC 2007: 487-500
324		Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy, Chaitali Chakrabarti: Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering. ICCAD 2007: 199-204
323		Kunhyuk Kang, Sang Phill Park, Kaushik Roy, Muhammad Ashraful Alam: Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance. ICCAD 2007: 730-734
322		Jung Hwan Choi, Jayathi Murthy, Kaushik Roy: The effect of process variation on device temperature in FinFET circuits. ICCAD 2007: 747-751
321		Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy: Tolerance to Small Delay Defects by Adaptive Clock Stretching. IOLTS 2007: 244-252
320		Nilanjan Banerjee, Jung Hwan Choi, Kaushik Roy: A process variation aware low power synthesis methodology for fixed-point FIR filters. ISLPED 2007: 147-152
319		Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy: A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM. ISLPED 2007: 171-176
318		Keejong Kim, Hamid Mahmoodi, Kaushik Roy: A low-power SRAM using bit-line charge-recycling technique. ISLPED 2007: 177-182
317		Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy: Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. ISLPED 2007: 387-390
316		Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy: Low-power process-variation tolerant arithmetic units using input-based elastic clocking. ISLPED 2007: 74-79
315		Tamer Cakici, Keejong Kim, Kaushik Roy: FinFET Based SRAM Design for Low Standby Power Applications. ISQED 2007: 127-132
314		Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy: Fine-Grained Redundancy in Adders. ISQED 2007: 317-321
313		Jaydeep P. Kulkarni, Kaushik Roy: A High Performance, Scalable Multiplexed Keeper Technique. ISQED 2007: 545-549
312		Jing Li, Swaroop Ghosh, Kaushik Roy: A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs. ITC 2007: 1-10
311		Kunhyuk Kang, Muhammad Ashraful Alam, Kaushik Roy: Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ. ITC 2007: 1-10
310		Swarup Bhunia, Kaushik Roy: Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions. ITC 2007: 1-10
309		Qikai Chen, Arjun Guha, Kaushik Roy: An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function. VLSI Design 2007: 615-620
308		Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: Process Variations and Process-Tolerant Design. VLSI Design 2007: 699-704
307		Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Low-Power and testable circuit synthesis using Shannon decomposition. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
306		Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies CoRR abs/0710.4663: (2007)
305		Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits CoRR abs/0710.4729: (2007)
304		Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy: Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. IEEE Trans. VLSI Syst. 15(6): 660-671 (2007)
303		Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy, Muhammad Ashraful Alam: Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1770-1781 (2007)
302		Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1947-1956 (2007)
301		Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, D. Lekshmanan, Kaushik Roy: Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1957-1966 (2007)
300		Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy: Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2059-2068 (2007)
299		Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy: Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 743-751 (2007)
298		Yongtao Wang, Khurram Muhammad, Kaushik Roy: Design of Sigma-Delta Modulators With Arbitrary Transfer Functions. IEEE Transactions on Signal Processing 55(2): 677-683 (2007)
297		Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy: Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders. IEICE Transactions 90-C(4): 865-876 (2007)
296		Nilanjan Banerjee, Kaushik Roy: Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing. J. Low Power Electronics 3(3): 254-270 (2007)
295		Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectronics Journal 38(8-9): 931-941 (2007)
294		Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh: SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ASP-DAC 2006: 158-163
293		Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy: Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. ASP-DAC 2006: 237-242
292		Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy: Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. ASP-DAC 2006: 665-670
291		Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy: Speed binning aware design methodology to improve profit under parameter variations. ASP-DAC 2006: 712-717
290		Hari Ananthan, Kaushik Roy: A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. DAC 2006: 413-418
289		Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy: A high density, carbon nanotube capacitor for decoupling applications. DAC 2006: 935-938
288		Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy: Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. DAC 2006: 971-976
287		Mark M. Budnik, Kaushik Roy: Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network. DATE 2006: 1116-1121
286		Jongsun Park, Jung Hwan Choi, Kaushik Roy: Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off. DATE 2006: 520-521
285		Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy: Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. DATE 2006: 780-785
284		Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy: Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. DATE 2006: 856-861
283		Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia: Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE 2006: 862-867
282		Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy: Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. DATE 2006: 983-988
281		Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy: Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. ICCAD 2006: 583-586
280		Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. ICCAD 2006: 619-624
279		Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy: Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI. ICCD 2006
278		Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. IOLTS 2006: 31-36
277		Ik Joon Chang, Jae-Joon Kim, Kaushik Roy: Robust level converter design for sub-threshold logic. ISLPED 2006: 14-19
276		Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy: Analysis of super cut-off transistors for ultralow power digital logic circuits. ISLPED 2006: 2-7
275		Qikai Chen, Mesut Meterelliyoz, Kaushik Roy: A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design. ISQED 2006: 243-248
274		Mark M. Budnik, Kaushik Roy: Minimizing Ohmic Loss in Future Processor IR Events. ISQED 2006: 650-658
273		Saibal Mukhopadhyay, Swaroop Ghosh, Keejong Kim, Kaushik Roy: Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies. SoCC 2006: 155-159
272		Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design 2006: 445-452
271		Kunhyuk Kang, Bipul C. Paul, Kaushik Roy: Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters. ACM Trans. Design Autom. Electr. Syst. 11(4): 848-879 (2006)
270		Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng: Test Consideration for Nanometer-Scale CMOS Circuits. IEEE Design & Test of Computers 23(2): 128-136 (2006)
269		Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim: Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro 26(2): 68-80 (2006)
268		Mark M. Budnik, Kaushik Roy: A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies. IEEE Trans. VLSI Syst. 14(12): 1336-1346 (2006)
267		Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. IEEE Trans. VLSI Syst. 14(2): 183-192 (2006)
266		Dongku Kang, Hunsoo Choo, Khurram Muhammad, Kaushik Roy: Layout-driven architecture synthesis for high-speed digital filters. IEEE Trans. VLSI Syst. 14(2): 203-207 (2006)
265		Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar: A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. VLSI Syst. 14(6): 646-649 (2006)
264		Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi: Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. IEEE Trans. VLSI Syst. 14(9): 1034-1039 (2006)
263		Arijit Raychowdhury, Kaushik Roy: Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 58-65 (2006)
262		Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Leakage Currents in Double-Gate Technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2052-2061 (2006)
261		Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2427-2436 (2006)
260		Aditya Bansal, Bipul Chandra Paul, Kaushik Roy: An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2765-2774 (2006)
259		Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2934-2943 (2006)
258		Jongsun Park, Khurram Muhammad, Kaushik Roy: Efficient modeling of 1/falpha/ noise using multirate process. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1247-1256 (2006)
257		Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1486-1495 (2006)
256		Kaushik Roy: Guest Editorial. Integration 39(2): 63 (2006)
255		Bipul Chandra Paul, Amit Agarwal, Kaushik Roy: Low-power design techniques for scaled technologies. Integration 39(2): 64-89 (2006)
254		Bipul C. Paul, Kaushik Roy: Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits. J. Electronic Testing 22(2): 115-124 (2006)
253		Kaushik Roy, Vivek Tiwari: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005 ACM 2005
252		Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy: Energy recovery clocked dynamic logic. ACM Great Lakes Symposium on VLSI 2005: 468-471
251		Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. Asian Test Symposium 2005: 170-175
250		Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy: Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. Asian Test Symposium 2005: 176-181
249		Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. Asian Test Symposium 2005: 404-409
248		Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy: A novel synthesis approach for active leakage power reduction using dynamic supply gating. DAC 2005: 479-484
247		Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy: A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE 2005: 1136-1141
246		Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. DATE 2005: 224-229
245		Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy: Statistical Timing Analysis using Levelized Covariance Propagation. DATE 2005: 764-769
244		Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. DATE 2005: 926-931
243		Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-gate SOI devices for low-power and high-performance applications. ICCAD 2005: 217-224
242		Amit Agarwal, Kunhyuk Kang, Kaushik Roy: Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. ICCAD 2005: 736-741
241		Patrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy: A Soft Error Monitor Using Switching Current Detection. ICCD 2005: 185-192
240		Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy: Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD 2005: 206-214
239		Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy: A Feasibility Study of Subthreshold SRAM Across Technology Generations. ICCD 2005: 417-424
238		Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy: Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS 2005: 100-105
237		Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy: Process Variation Tolerant Online Current Monitor for Robust Systems. IOLTS 2005: 171-176
236		Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. IOLTS 2005: 275-280
235		Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy: A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning. IOLTS 2005: 287-292
234		Aditya Bansal, Kaushik Roy: Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. ISCAS (1) 2005: 1-4
233		Yongtao Wang, Kaushik Roy: A novel low-complexity method for parallel multiplierless implementation of digital FIR filters. ISCAS (3) 2005: 2020-2023
232		Yongtao Wang, Kaushik Roy: A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems. ISCAS (5) 2005: 4963-4966
231		Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Y. Borkar: An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ISLPED 2005: 103-106
230		Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh: Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. ISLPED 2005: 115-118
229		Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy: Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. ISLPED 2005: 14-19
228		Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy: Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. ISLPED 2005: 8-13
227		Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. ISQED 2005: 358-363
226		Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415
225		Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy: Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED 2005: 453-458
224		Dongku Kang, Yiran Chen, Kaushik Roy: Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis. ISQED 2005: 48-53
223		Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. ISQED 2005: 490-495
222		Keejong Kim, Chris H. Kim, Kaushik Roy: TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. ISQED 2005: 59-64
221		Mesut Meterelliyoz, Hamid Mahmoodi, Kaushik Roy: A leakage control system for thermal stability during burn-in test. ITC 2005: 10
220		Saibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, Kaushik Roy: Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring. ITC 2005: 10
219		Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy: Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. VTS 2005: 292-297
218		Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy: Synthesis of skewed logic circuits. ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005)
217		Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy: Synthesis of application-specific highly efficient multi-mode cores for embedded systems. ACM Trans. Embedded Comput. Syst. 4(1): 168-188 (2005)
216		Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy: GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. IEEE Trans. Computers 54(6): 752-766 (2005)
215		Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy: A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. VLSI Syst. 13(1): 27-38 (2005)
214		Yiran Chen, Kaushik Roy, Cheng-Kok Koh: Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Trans. VLSI Syst. 13(1): 75-85 (2005)
213		Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy: Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. IEEE Trans. VLSI Syst. 13(11): 1213-1224 (2005)
212		Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy: Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans. VLSI Syst. 13(11): 1286-1295 (2005)
211		Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy: A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. VLSI Syst. 13(3): 349-357 (2005)
210		Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy: Low-power scan design using first-level supply gating. IEEE Trans. VLSI Syst. 13(3): 384-395 (2005)
209		Swarup Bhunia, Kaushik Roy: A novel wavelet transform-based transient current analysis for fault detection and localization. IEEE Trans. VLSI Syst. 13(4): 503-507 (2005)
208		Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar: Combined circuit and architectural level variable supply-voltage scaling for low power. IEEE Trans. VLSI Syst. 13(5): 564-576 (2005)
207		Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1859-1880 (2005)
206		Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy: Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 363-381 (2005)
205		Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. J. Electronic Testing 21(2): 147-159 (2005)
204		Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. J. Electronic Testing 21(3): 243-255 (2005)
203		Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004 ACM 2004
202		Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy: Adaptive supply voltage technique for low swing interconnects. ASP-DAC 2004: 284-287
201		Yiran Chen, Kaushik Roy, Cheng-Kok Koh: Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. ASP-DAC 2004: 893-898
200		Cheng-Yi Chen, Soonkeon Kwon, Kaushik Roy: Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array. Communications in Computing 2004: 167-176
199		Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy: Novel sizing algorithm for yield improvement under process variation in nanometer technology. DAC 2004: 454-459
198		Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy: Leakage in nano-scale technologies: mechanisms, impact and design considerations. DAC 2004: 6-11
197		Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. DATE 2004: 704-705
196		Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy: First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT 2004: 314-315
195		Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Statistical design and optimization of SRAM cell for yield enhancement. ICCAD 2004: 10-13
194		Arijit Raychowdhury, Kaushik Roy: A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies. ICCAD 2004: 237-240
193		Dongku Kang, Hunsoo Choo, Kaushik Roy: Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed. ICCD 2004: 354-357
192		Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy: A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD 2004: 60-65
191		Xiaowei Ding, Kaushik Roy: A Novel Bitstream Level Joint Channel Error Concealment Scheme for Realtime Video over Wireless Networks. INFOCOM 2004
190		Amit Agarwal, Bipul Chandra Paul, Kaushik Roy: A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. IOLTS 2004: 149-154
189		Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy: A Technique to Reduce Power and Test Application Time in BIST. IOLTS 2004: 182-183
188		Hamid Mahmoodi-Meimand, Kaushik Roy: Dual-edge triggered level converting flip-flops. ISCAS (2) 2004: 661-664
187		Hamid Mahmoodi-Meimand, Kaushik Roy: Data-retention flip-flops for power-down applications. ISCAS (2) 2004: 677-680
186		Myeong-Eun Hwang, Arijit Raychowdhury, Kaushik Roy: Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies. ISCAS (3) 2004: 709-712
185		Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy: Low-power carry-select adder using adaptive supply voltage based on input vector patterns. ISLPED 2004: 313-318
184		Hari Ananthan, Chris H. Kim, Kaushik Roy: Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. ISLPED 2004: 8-13
183		Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy: Device optimization for ultra-low power digital sub-threshold operation. ISLPED 2004: 96-101
182		Arijit Raychowdhury, Kaushik Roy: A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs. ISMVL 2004: 14-19
181		Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. ISQED 2004: 389-394
180		Hari Ananthan, Aditya Bansal, Kaushik Roy: FinFET SRAM - Device and Circuit Design Considerations. ISQED 2004: 511-516
179		Kaushik Roy: Low-Power Design. ISQED 2004: 8
178		Dongku Kang, Mark C. Johnson, Kaushik Roy: Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan. ISQED 2004: 98-103
177		Bipul Chandra Paul, Cassondra Neau, Kaushik Roy: Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. ITC 2004: 1269-1275
176		Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy: Modeling and Estimation of Leakage in Sub-90nm Devices. VLSI Design 2004: 65-
175		Naran Sirisantana, Kaushik Roy: Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses. IEEE Design & Test of Computers 21(1): 56-63 (2004)
174		Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy: Enhancing Yield at the End of the Technology Roadmap. IEEE Design & Test of Computers 21(6): 563-571 (2004)
173		Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar: DCG: deterministic clock-gating for low-power microprocessor design. IEEE Trans. VLSI Syst. 12(3): 245-254 (2004)
172		Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy: A circuit-compatible model of ballistic carbon nanotube field-effect transistors. IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1411-1420 (2004)
171		Hunsoo Choo, Khurram Muhammad, Kaushik Roy: Complexity reduction of digital filters using shift inclusive differential coefficients. IEEE Transactions on Signal Processing 52(6): 1760-1772 (2004)
170		Guoan Zhong, Cheng-Kok Koh, Kaushik Roy: A metric for analyzing effective on-chip inductive coupling. ASP-DAC 2003: 156-161
169		Woopyo Jeong, Kaushik Roy: Robust high-performance low-power carry select adder. ASP-DAC 2003: 503-506
168		Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy: Integer linear programming-based synthesis of skewed logic circuits. ASP-DAC 2003: 820-823
167		Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy: Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. DAC 2003: 169-174
166		Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy: An adaptive window-based susceptance extraction and its efficient implementation. DAC 2003: 728-731
165		Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy: Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. DATE 2003: 10096-10103
164		Hunsoo Choo, Khurram Muhammad, Kaushik Roy: MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters. DATE 2003: 10700-10705
163		Amit Agarwal, Kaushik Roy, T. N. Vijaykumar: Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. DATE 2003: 10778-10783
162		Seung Hoon Choi, Kaushik Roy: A New Crosstalk Noise Model for DOMINO Logic Circuits. DATE 2003: 11112-11113
161		Naran Sirisantana, Kaushik Roy: Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. DATE 2003: 11160-11161
160		Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy: Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. DFT 2003: 191-198
159		Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy: Deterministic Clock Gating for Microprocessor Power Reduction. HPCA 2003: 113-122
158		Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy: Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. ICCAD 2003: 487-490
157		Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy: Low Power Adder with Adaptive Supply Voltage. ICCD 2003: 103-106
156		Dongku Kang, Mark C. Johnson, Kaushik Roy: Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan. ICCD 2003: 412-418
155		Yonghee Im, Kaushik Roy: A logic-aware layout methodology to enhance the noise immunity of domino circuits. ISCAS (5) 2003: 637-640
154		Cassondra Neau, Kaushik Roy: Optimal body bias selection for leakage improvement and process compensation over different technology generations. ISLPED 2003: 116-121
153		Saibal Mukhopadhyay, Kaushik Roy: Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. ISLPED 2003: 172-175
152		Amit Agarwal, Kaushik Roy: A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. ISLPED 2003: 18-21
151		Yiran Chen, Kaushik Roy, Cheng-Kok Koh: Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED 2003: 229-234
150		Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy: Energy recovery clocking scheme and flip-flops for ultra low-energy applications. ISLPED 2003: 54-59
149		Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy: A forward body-biased low-leakage SRAM cache: device and architecture considerations. ISLPED 2003: 6-9
148		Yonghee Im, Kaushik Roy: LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits. ISVLSI 2003: 45-54
147		Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy: VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. MICRO 2003: 19-28
146		Rajiv V. Joshi, Kaushik Roy: Design of Deep Sub-Micron CMOS Circuits. VLSI Design 2003: 15-16
145		Kaushik Roy, T. M. Mak, Kwang-Ting Cheng: Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. VTS 2003: 313-318
144		Jongsun Park, Khurram Muhammad, Kaushik Roy: High-performance FIR filter design based on sharing multiplication. IEEE Trans. VLSI Syst. 11(2): 244-253 (2003)
143		Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy: Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. VLSI Syst. 11(4): 716-730 (2003)
142		Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Vivek De: Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ. IEEE Trans. VLSI Syst. 11(5): 863-870 (2003)
141		C. H.-I. Kim, Hendrawan Soeleman, Kaushik Roy: Ultra-low-power DLMS adaptive filter for hearing aid applications. IEEE Trans. VLSI Syst. 11(6): 1058-1067 (2003)
140		Guoan Zhong, Cheng-Kok Koh, Kaushik Roy: On-chip interconnect modeling by wire duplication. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1521-1532 (2003)
139		Hunsoo Choo, Khurram Muhammad, Kaushik Roy: Two's complement computation sharing multiplier and its applications to high performance DFE. IEEE Transactions on Signal Processing 51(2): 458-469 (2003)
138		Swarup Bhunia, Hai Li, Kaushik Roy: A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. Asian Test Symposium 2002: 157-
137		Swarup Bhunia, Kaushik Roy, Jaume Segura: A novel wavelet transform based transient current analysis for fault detection and localization. DAC 2002: 361-366
136		Amit Agarwal, Hai Li, Kaushik Roy: DRG-cache: a data retention gated-ground cache for low power. DAC 2002: 473-478
135		Seung Hoon Choi, Kaushik Roy, Florentin Dartu: Timed pattern generation for noise-on-delay calculation. DAC 2002: 870-873
134		Swarup Bhunia, Kaushik Roy: Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis. DATE 2002: 1118
133		Chris H. Kim, Kaushik Roy: Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. DATE 2002: 163-167
132		Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy: Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. DATE 2002: 931-935
131		Seung Hoon Choi, Kaushik Roy: Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits. DELTA 2002: 365-369
130		Jongsun Park, Soonkeon Kwon, Kaushik Roy: Low power reconfigurable DCT design based on sharing multiplication. ICASSP 2002: 3116-3119
129		Guoan Zhong, Cheng-Kok Koh, Kaushik Roy: On-chip interconnect modeling by wire duplication. ICCAD 2002: 341-346
128		Chris H. Kim, Kaushik Roy: Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. ISLPED 2002: 251-254
127		Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy: High performance and low power FIR filter design based on sharing multiplication. ISLPED 2002: 295-300
126		Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy: Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED 2002: 229-234
125		Bipul Chandra Paul, Kaushik Roy: Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. ITC 2002: 384-390
124		Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. VLSI Design 2002: 489-
123		Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy: Dynamic Noise Analysis with Capacitive and Inductive Coupling. VLSI Design 2002: 65-70
122		Swarup Bhunia, Kaushik Roy: Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. VTS 2002: 302-310
121		Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy: IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. IEEE Design & Test of Computers 19(2): 24-33 (2002)
120		Ali Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins: Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. IEEE Design & Test of Computers 19(5): 36-43 (2002)
119		Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy: Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Trans. VLSI Syst. 10(1): 1-5 (2002)
118		Yonghee Im, Kaushik Roy: O2ABA: a novel high-performance predictable circuit architecture for the deep submicron era. IEEE Trans. VLSI Syst. 10(3): 221-229 (2002)
117		Khurram Muhammad, Kaushik Roy: Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling. IEEE Trans. VLSI Syst. 10(3): 292-300 (2002)
116		Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes: Vertically integrated SOI circuits for low-power and high-performance applications. IEEE Trans. VLSI Syst. 10(3): 351-362 (2002)
115		Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy: Skewed CMOS: noise-tolerant high-performance low-power static circuit family. IEEE Trans. VLSI Syst. 10(4): 469-476 (2002)
114		Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 81-92 (2002)
113		Khurram Muhammad, Kaushik Roy: A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 204-216 (2002)
112		Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand: Leakage Current in Deep-Submicron CMOS Circuits. Journal of Circuits, Systems, and Computers 11(6): 575-600 (2002)
111		Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001 ACM 2001
110		Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy: Design Verification and Robust Design Technique for Cross-Talk Faults. Asian Test Symposium 2001: 449-
109		Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. DAC 2001: 846-851
108		Cassondra Neau, Khurram Muhammad, Kaushik Roy: Low complexity FIR filters using factorization of perturbed coefficients. DATE 2001: 268-272
107		Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar: An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. HPCA 2001: 147-157
106		Yonghee Im, Kaushik Roy: CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic. ICCAD 2001: 337-
105		Xiaodong Zhang, Kaushik Roy: Power Constrained Test Scheduling with Low Power Weighted Random Testing. IOLTW 2001: 136
104		Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Power trends and performance characterization of 3-dimensional integration. ISCAS (4) 2001: 414-417
103		Rui Wang, Kaushik Roy, Cheng-Kok Koh: Short-circuit power analysis of an inverter driving an RLC load. ISCAS (4) 2001: 886-889
102		Rongtian Zhang, Kaushik Roy, David B. Janes: Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design. ISLPED 2001: 213-218
101		Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy: Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED 2001: 267-270
100		Hyung-il Kim, Kaushik Roy: Ultra-low power DLMS adaptive filter for hearing aid applications. ISLPED 2001: 352-357
99		Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Decoupling capacitance allocation for power supply noise suppression. ISPD 2001: 66-71
98		Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. ISQED 2001: 217-222
97		Kaushik Roy, Ali Keshavarzi: Design and Test of Low Voltage CMOS Circuits. ISQED 2001: 7
96		Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy: Reducing set-associative cache energy via way-prediction and selective direct-mapping. MICRO 2001: 54-65
95		Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul: Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. VLSI Design 2001: 211-214
94		Khurram Muhammad, Kaushik Roy: Fault Detection and Location Using IDD Waveform Analysis. IEEE Design & Test of Computers 18(1): 42-49 (2001)
93		Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar: Reducing leakage in a high-performance deep-submicron instruction cache. IEEE Trans. VLSI Syst. 9(1): 77-89 (2001)
92		Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul: Robust subthreshold logic for ultra-low power operation. IEEE Trans. VLSI Syst. 9(1): 90-99 (2001)
91		Zhanping Chen, Liqiong Wei, Kaushik Roy: On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques. IEEE Trans. VLSI Syst. 9(5): 718-725 (2001)
90		Majid Sarrafzadeh, Prithviraj Banerjee, Kaushik Roy: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000 ACM 2000
89		Kaushik Roy, Sharat Prasad: Low-Power CMOS VLSI Circuit Design. Wiley 2000: I-XV, 1-359
88		Hendrawan Soeleman, Kaushik Roy: Digital CMOS logic operation in the sub-threshold region. ACM Great Lakes Symposium on VLSI 2000: 107-112
87		Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy: Test challenges for deep sub-micron technologies. DAC 2000: 142-149
86		Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De: Dynamic noise analysis in precharge-evaluate circuits. DAC 2000: 243
85		Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes: Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. ICCAD 2000: 208-213
84		Guoan Zhong, Cheng-Kok Koh, Kaushik Roy: A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. ICCAD 2000: 406-411
83		Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Frequency Domain Analysis of Switching Noise on Power Supply Network. ICCAD 2000: 487-492
82		Naran Sirisantana, Liqiong Wei, Kaushik Roy: High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. ICCD 2000: 227-
81		Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar: Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ICCD 2000: 241-246
80		Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh: Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. ICCD 2000: 65-72
79		Xiaodong Zhang, Kaushik Roy: Power Reduction in Test-Per-Scan BIST. IOLTW 2000: 133-
78		Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul: Robust ultra-low power sub-threshold DTMOS logic. ISLPED 2000: 25-30
77		Zhanping Chen, Liqiong Wei, Kaushik Roy: On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. ISQED 2000: 181-188
76		Xiaodong Zhang, Kaushik Roy: Peak Power Reduction in Low Power BIST. ISQED 2000: 425-432
75		Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, K. Soumyanath, Vivek De: Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. ITC 2000: 1051-1059
74		Kaushik Roy, Khurram Muhammad: Low Power VLSI Signal Processing. VLSI Design 2000: 12
73		Shiyou Zhao, Kaushik Roy: Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits. VLSI Design 2000: 168-
72		Liqiong Wei, Kaushik Roy, Vivek De: Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. VLSI Design 2000: 24-29
71		Hendrawan Soeleman, Kaushik Roy, Tan-Li Chou: Estimating Circuit Activity in Combinational CMOS Digital Circuits. IEEE Design & Test of Computers 17(2): 112-119 (2000)
70		Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins: Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions. IEEE Trans. VLSI Syst. 8(6): 717-723 (2000)
69		Zhanping Chen, Kaushik Roy, Edwin K. P. Chong: Estimation of power dissipation using a novel power macromodelingtechnique. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1363-1369 (2000)
68		Xiaodong Zhang, Wenlei Shan, Kaushik Roy: Low-power weighted random pattern testing. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1389-1398 (2000)
67		Yibin Ye, Kaushik Roy, Rolf Drechsler: Power Consumption in XOR-Based Circuits. ASP-DAC 1999: 299-302
66		Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De: Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. DAC 1999: 430-435
65		Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy: Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. DAC 1999: 442-445
64		Xiaodong Zhang, Kaushik Roy: Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction. DFT 1999: 148-
63		Khurram Muhammad, Kaushik Roy: A novel design methodology for high performance and low power digital filters. ICCAD 1999: 80-83
62		Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy: Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. ICCD 1999: 230-235
61		Kaushik Roy, Liqiong Wei, Zhanping Chen: Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. ISCAS (1) 1999: 366-370
60		Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De: Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. ISLPED 1999: 252-254
59		Hendrawan Soeleman, Kaushik Roy: Ultra-low power digital subthreshold logic circuits. ISLPED 1999: 94-96
58		Khurram Muhammad, Kaushik Roy: A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters. ISSS 1999: 94-99
57		Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik: POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing. VLSI Design 1999: 416-422
56		Kaushik Roy, Anand Raghunathan, Sujit Dey: Low Power Design Methodologies for Systems-on-Chips. VLSI Design 1999: 609
55		Sudip Nag, H. K. Verma, Kaushik Roy: VLSI Signal Processing in FPGAs. VLSI Design 1999: 609
54		Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De: Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. VLSI Syst. 7(1): 16-24 (1999)
53		Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy: Models and algorithms for bounds on leakage in CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 714-725 (1999)
52		Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De: Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. DAC 1998: 489-494
51		Zhanping Chen, Kaushik Roy: A Power Macromodeling Technique Based on Power Sensitivity. DAC 1998: 678-683
50		James R. Anderson, Siddharth Sheth, Kaushik Roy: A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering. FPGA 1998: 234-244
49		Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy: IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. Great Lakes Symposium on VLSI 1998: 243-248
48		Zhanping Chen, Kaushik Roy, Edwin K. P. Chong: Estimation of power sensitivity in sequential circuits with power macromodeling application. ICCAD 1998: 468-472
47		Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy: Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. ISLPED 1998: 239-244
46		Chuan-Yu Wang, Kaushik Roy: Maximum power estimation for CMOS circuits using deterministic and statistical approaches. IEEE Trans. VLSI Syst. 6(1): 134-140 (1998)
45		Zhanping Chen, Kaushik Roy, Tan-Li Chou: Efficient statistical approach to estimate power considering uncertain properties of primary inputs. IEEE Trans. VLSI Syst. 6(3): 484-492 (1998)
44		Dinesh Somasekhar, Kaushik Roy: LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. IEEE Trans. VLSI Syst. 6(4): 573-577 (1998)
43		Yibin Ye, Kaushik Roy: A Graph-Based Synthesis Algorithm for AND/XOR Networks. DAC 1997: 107-112
42		Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya: Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems. ICCAD 1997: 120-125
41		Zhanping Chen, Kaushik Roy, Tan-Li Chou: Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. ICCAD 1997: 40-44
40		Chuan-Yu Wang, Kaushik Roy: COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits. ICCAD 1997: 52-55
39		Khurram Muhammad, Kaushik Roy: On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution. ICCD 1997: 196-201
38		Chuan-Yu Wang, Kaushik Roy: Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions. ICCD 1997: 746-751
37		Dinesh Somasekhar, Kaushik Roy: LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. ISLPED 1997: 18-23
36		Yibin Ye, Kaushik Roy, Georgios I. Stamoulis: Quasi-static energy recovery logic and supply-clock generation circuits. ISLPED 1997: 96-99
35		Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins: Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs. ITC 1997: 146-155
34		Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya: Algorithms for Low Power FIR Filter Realization Using Differential Coefficients. VLSI Design 1997: 174-178
33		P. Patil, Tan-Li Chou, Kaushik Roy, R. Roy: Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique. VLSI Design 1997: 179-184
32		Mark C. Johnson, Kaushik Roy: Datapath scheduling with multiple supply voltages and level converters. ACM Trans. Design Autom. Electr. Syst. 2(3): 227-248 (1997)
31		Mark C. Johnson, Kaushik Roy: Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints. ICCD 1996: 72-77
30		Kaushik Roy, R. K. Roy: Low Power Design. VLSI Design 1996: 2
29		Chuan-Yu Wang, Kaushik Roy: Maximum power estimation for CMOS circuits using deterministic and statistic approaches. VLSI Design 1996: 364-369
28		S. C. Prasad, Kaushik Roy: Transistor reordering for power minimization under delay constraint. ACM Trans. Design Autom. Electr. Syst. 1(2): 280-300 (1996)
27		Tan-Li Chou, Kaushik Roy: Accurate power estimation of CMOS sequential circuits. IEEE Trans. VLSI Syst. 4(3): 369-380 (1996)
26		Tan-Li Chou, Kaushik Roy: Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1257-1265 (1996)
25		Tan-Li Chou, Kaushik Roy: Statistical estimation of sequential circuit activity. ICCAD 1995: 34-37
24		Chuan-Yu Wang, Kaushik Roy: Control unit synthesis targeting low-power processors. ICCD 1995: 454-
23		Tan-Li Chou, Kaushik Roy: Estimation of sequential circuit activity considering spatial and temporal correlations. ICCD 1995: 577-
22		Kevin T. Kornegay, Kaushik Roy: Integrated Test Solutions and Test Economics for MCMs. ITC 1995: 193-201
21		S. C. Prasad, Kaushik Roy: Circuit optimization for minimisation of power consumption under delay constraint. VLSI Design 1995: 305-309
20		Kaushik Roy, Sudip Nag: On Routability for FPGAs under Faulty Conditions. IEEE Trans. Computers 44(11): 1296-1305 (1995)
19		Kaushik Roy, Sharat Prasad: Logic synthesis for reliability—an early start to controlling electromigration and hot carrier effects. EURO-DAC 1994: 136-141
18		Kaushik Roy, Sudip Nag: On Channel Architecture and Routability for FPGAs Under Faulty Conditions. FPL 1994: 361-372
17		Kaushik Roy, Sharat Prasad: Power Dissipation Driven FPGA Place and Route Under Delay Constraints. FPL 1994: 57-65
16		Tan-Li Chou, Kaushik Roy, Sharat Prasad: Estimation of circuit activity considering signal correlations and simultaneous switching. ICCAD 1994: 300-303
15		Santanu Dutta, Sudip Nag, Kaushik Roy: ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits. ISCAS 1994: 61-64
14		Kaushik Roy, Abhijit Chatterjee: Guest Editors' Introduction: Low-Power VLSI Design. IEEE Design & Test of Computers 11(4): 6-7 (1994)
13		Marc E. Levitt, Kaushik Roy, Jacob A. Abraham: BiCMOS logic testing. IEEE Trans. VLSI Syst. 2(2): 241-248 (1994)
12		Kaushik Roy, Sudip Nag: Automatic synthesis of FPGA channel architecture for routability and performance. IEEE Trans. VLSI Syst. 2(4): 508-511 (1994)
11		Sudip Nag, Kaushik Roy: Iterative Wirability and Performance Improvement for FPGAs. DAC 1993: 321-325
10		Kaushik Roy, Sudip Nag, Santanu Dutta: Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs. ICCD 1993: 220-223
9		Kaushik Roy: On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs. ISCAS 1993: 1623-1626
8		Mahesh Mehendale, Kaushik Roy: Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. VLSI Design 1993: 100-103
7		Kaushik Roy, S. C. Prasad: Circuit activity based logic synthesis for low power reliable operations. IEEE Trans. VLSI Syst. 1(4): 503-513 (1993)
6		Kaushik Roy: A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues. IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1695-1705 (1993)
5		Kaushik Roy, Sharat Prasad: SYCLOP: Synthesis of CMOS Logic for Low Power Applications. ICCD 1992: 464-467
4		Kaushik Roy, Jacob A. Abraham: High level test generation using data flow descriptions. EURO-DAC 1990: 480-484
3		Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham: Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. IEEE Trans. Computers 39(9): 1132-1145 (1990)
2		Kaushik Roy, Jacob A. Abraham: A Novel Approach to Accurate Timing Verification Using RTL Descriptions. DAC 1989: 638-641
1		Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Jacob A. Abraham: An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor. FTCS 1988: 362-367