Abinash Roy (Selection)

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7		Abinash Roy, Masud H. Chowdhury: Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects. ISCAS 2008: 2426-2429
6		Jingye Xu, Abinash Roy, Masud H. Chowdhury: Optimization technique for flip-flop inserted global interconnect. ISCAS 2008: 3386-3389
5		Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury: Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew. DAC 2007: 184-187
4		Jingye Xu, Abinash Roy, Masud H. Chowdhury: Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining. DATE 2007: 1218-1223
3		Jingye Xu, Abinash Roy, Masud H. Chowdhury: Power Consumption Analysis of Flip-flop Based Interconnect Pipelining. ISCAS 2007: 3716-3719
2		Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury: Delay and Clock Skew Variation due to Coupling Capacitance and Inductance. ISCAS 2007: 621-624
1		Abinash Roy, Masud H. Chowdhury: Global Interconnect Optimization in the Presence of On-chip Inductance. ISCAS 2007: 885-888

Selection of 7 from 7 records - Abinash Roy has 3 coauthors