Carlo Roma (Selection)

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4 Carlo Roma, Pierluigi Daglio, Guido De Sandre, Marco Pasotti, Marco Poles: How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results. ISQED 2005: 107-112

3 Pierluigi Daglio, David Iezzi, Danilo Rimondi, Carlo Roma, Salvatore Santapa: Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components. DATE 2004: 336-337

2 Pierluigi Daglio, Carlo Roma: A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies. DATE 2003: 20274-20279

1 Pierluigi Daglio, M. Araldi, M. Morbarigazzi, Carlo Roma: A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies. ISQED 2001: 451-455

Selection of 4 from 4 records - Carlo Roma has 9 coauthors

4		Carlo Roma, Pierluigi Daglio, Guido De Sandre, Marco Pasotti, Marco Poles: How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results. ISQED 2005: 107-112
3		Pierluigi Daglio, David Iezzi, Danilo Rimondi, Carlo Roma, Salvatore Santapa: Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components. DATE 2004: 336-337
2		Pierluigi Daglio, Carlo Roma: A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies. DATE 2003: 20274-20279
1		Pierluigi Daglio, M. Araldi, M. Morbarigazzi, Carlo Roma: A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies. ISQED 2001: 451-455