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Srivaths Ravi (Selection)

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18Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: High-level test compaction techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 827-841 (2002)
17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana: Transient Power Management Through High Level Synthesis. ICCAD 2001: 545-552
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: TAO: regular expression-based register-transfer level testability analysis and optimization. IEEE Trans. VLSI Syst. 9(6): 824-832 (2001)
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: Testing of core-based systems-on-a-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 426-439 (2001)
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: : Reducing test application time in high-level test generation. ITC 2000: 829-838
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana: High-Level Synthesis with Variable-Latency Components. VLSI Design 2000: 220-227
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana: Integrating variable-latency components into high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1105-1117 (2000)
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 894-906 (2000)
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: A framework for testing core-based systems-on-a-chip. ICCAD 1999: 385-390
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. VTS 1999: 398-406
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. ICCAD 1998: 577-584
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: TAO: regular expression based high-level testability analysis and optimization. ITC 1998: 331-340

Selection of 12 from 94 records - Srivaths Ravi has 55 coauthors

Last update 2012-09-10 CET by the DBLP TeamThis material is Open Data Content released under the ODC-BY 1.0 license — See also our legal information page