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Jagdish C. Rao (Selection)

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8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao: Clock gating effectiveness metrics: Applications to power optimization. ISQED 2009: 482-487
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao: Clock gating for power optimization in ASIC design cycle theory & practice. ISLPED 2008: 307-308
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKaranth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji: Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. VLSI Design 2002: 781-788
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKarthikeyan Madathil, Jagdish C. Rao, Subash G. Chandar, Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar: A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. VLSI Design 2000: 468-
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAvinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash G. Chandar: A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. ICCD 1999: 340-347
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAvinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar: A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors. VLSI Design 1999: 346-349

Selection of 6 from 8 records - Jagdish C. Rao has 27 coauthors

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