Mukesh Ranjan (Selection)

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4 Mukesh Ranjan, Ranga Vemuri: Exact hierarchical symbolic analysis of large analog networks using a general interconnection template. ISCAS 2006

3 Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri: Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. VLSI Design 2006: 689-694

2 Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen: Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. ASP-DAC 2005: 230-235

1 Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen: Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. DATE 2004: 604-609

Selection of 4 from 4 records - Mukesh Ranjan has 8 coauthors

4		Mukesh Ranjan, Ranga Vemuri: Exact hierarchical symbolic analysis of large analog networks using a general interconnection template. ISCAS 2006
3		Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri: Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. VLSI Design 2006: 689-694
2		Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen: Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. ASP-DAC 2005: 230-235
1		Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen: Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. DATE 2004: 604-609