Marco Poles (Selection)

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3 Carlo Roma, Pierluigi Daglio, Guido De Sandre, Marco Pasotti, Marco Poles: How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results. ISQED 2005: 107-112

2 Michele Borgatti, L. Cali, Guido De Sandre, B. Forét, D. Iezzi, Francesco Lertora, G. Muzzi, Marco Pasotti, Marco Poles, Pier Luigi Rolandi: A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory. DAC 2003: 691-695

Selection of 2 from 3 records - Marco Poles has 12 coauthors

3		Carlo Roma, Pierluigi Daglio, Guido De Sandre, Marco Pasotti, Marco Poles: How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results. ISQED 2005: 107-112
2		Michele Borgatti, L. Cali, Guido De Sandre, B. Forét, D. Iezzi, Francesco Lertora, G. Muzzi, Marco Pasotti, Marco Poles, Pier Luigi Rolandi: A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory. DAC 2003: 691-695